Infineon Technologies TC1784, User Manual

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TC1784
LMB External Bus Unit
User´s Manual 12-32 V1.1, 2011-05
EBUT13L-A, V1.16
12.10.4 Control of ADV & Other Signal Delays During Asynchronous
Accesses
For asynchronous accesses, the Memory Controller output signals: ADV, CS, RD,
RD/WR, and BC signals can be delayed with respect to the start of the access phases
they are asserted in. The amount by which the signal is delayed depends on the setting
of the EXTCLOCK field of EBU_BUSAPx :-
•
When EXTCLOCK is set to 00
B
, control signals are asserted on the negative edge of
EBU_CLK. i.e. they are in effect delayed by an EBU_CLK high pulse width (T
PH
)with
respect to the other signals.
• When EXTCLOCK is not set to 00
B
, control signals are asserted on the next positive
edge of EBU_CLK. i.e. they are in effect delayed by an EBU_CLK cycle (T
CLK
) with
respect to the other signals.
The Memory Controller allows these delays to be enabled and disabled independently
via the register bits EBU_BUSCONx.EBSE for ADV and EBU_BUSCONCx.ECSE for
the other control signals. The default setting after reset has the delay disabled.
EBU_BUSCONx WAIT External Wait State control (OFF, asynchronous,
synchronous)
WAITINV Reversed polarity at WAIT: active low or active high
EBSE Control Signal Timing (for ADV)
ECSE Control Signal Timing (for WR, CS and Write data)
Table 12-17 ADV Signal Timing
EXTCLOCK is
set to
ADV Falling Edge Position ADV Rising Edge Position
Delay
Disabled
1)
1) See Figure 12-7 for details of this signal positioning.
Delay Enabled Delay
Disabled
1)
Delay Enabled
00
B
Start of AP1 Start of AP1 +
T
PH
Start of AP1 Start of AP1 +
T
PH
01
B
, 10
B
, 11
B
Start of AP1 End of AP1 Start of AP1 End of AP1
Table 12-16 Asynchronous Access Programmable Parameters (cont’d)
Register Parameter
(Bit/Bit field) Function