Infineon Technologies TC1784, User Manual

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TC1784
LMB External Bus Unit
User´s Manual 12-26 V1.1, 2011-05
EBUT13L-A, V1.16
12.9.3 Command Delay Phase (CD)
The Command Delay phase is optional. This means that it can also be programmed for
a length of zero EBU_CLK clock cycles. The CD phase allows for the insertion of a delay
between Address Phase (or optional Address Hold phase) and Command Phase(s).
This phase accommodates devices that are not fast enough to receive commands
immediately after getting the address or multiplexed devices which require a bus
turnaround delay on reads.
The length (number of EBU_CLK cycles) of the Command Delay phase is programmed
via the EBU_BUSAPx.CMDDELAY bit field. This parameter makes it possible to select
between zero to seven Command Delay phases.
12.9.4 Command Phase (CP)
The Command Phase is mandatory. It always consists of at least one or more EBU_CLK
cycles. The phase can optionally be extended to accommodate slower devices.
The length (number of EBU_CLK cycles) of the Command Phase is separately
programmable for read and write accesses. Bit field EBU_BUSAPx.WAITRDC
determines the basic length of Command Phases during read cycles and bit field
EBU_BUSAPx.WAITWRC determines the basic length of Command Phases during
write cycles.
Additionally, when accessing asynchronous devices, a Command Phase can also be
extended externally using the WAIT signal when the region being accessed is
programmed for external command delay control via bit EBU_BUSCONx.WAIT or
EBU_EMUBC.WAIT.
The Command Phase is further subdivided into:
•
CPi (= internally-programmed Command Phase)
• CPe (= externally-prolonged Command Phase, i.e. prolonged by the assertion of the
WAIT signal).
At the start of the Command Phase, the EBU:
•
Asserts the appropriate control signal RD or RD/WR low according to the access type
(read or write),
• Issues the data to be written on the data bus AD[15:0] (in the case of a write cycle),
• Asserts the appropriate BCx low (in the case where BCx is programmed to be
asserted with the RD or RD/WR signals).
At the end of the Command Phase during an asynchronous access, the EBU:
•
Returns the appropriate control signal RD or RD/WR high according to the type of
access type (read or write),
• Latches the data from the data bus AD[15:0] (in the case of a read cycle),
• Returns the appropriate BCx high (in the case where BCx is programmed to be
asserted with the RD or RD/WR signals).