Infineon Technologies TC1784, User Manual

Page: 869 / 2350

TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-51 V1.1, 2011-05
DMA, V3.03
DMA_CHC
Rmn DMA Channel mn
Control Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
084
H
U, SV SV 3 Page 11-86
DMA_CHI
CRmn DMA Channel mn
Interrupt Control
Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
088
H
U, SV SV 3 Page 11-91
DMA_
ADRCRmn DMA Channel mn
Address Control
Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
08C
H
U, SV SV 3 Page 11-93
DMA_SAD
Rmn DMA Channel mn
Source Address
Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
090
H
U, SV SV 3 Page 11-98
DMA_DAD
Rmn DMA Channel mn
Destination Address
Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
094
H
U, SV SV 3 Page 11-99
DMA_SHA
DRmn DMA Channel mn
Shadow Address
Register
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
098
H
U, SV BE /
SV
2)
3 Page 11-100
- Reserved
(n = 0-7, m = 0-1) (n x 20
H
) +
(m x 10
0
H
) +
09C
H
BE BE - -
Table 11-8 Registers Overview - DMA Control Registers
Short
Name Description Offset
Addr.
1)
Access Mode Reset
Class
Description
See
Read Write