Infineon Technologies TC1784, User Manual

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TC1784
CPU Subsystem
User´s Manual 2-11 V1.1, 2011-05
CPU, V3.03
signals are passed to the core along with their corresponding instruction half-words.
Whenever an attempt is made to issue an instruction containing an uncorrectable
memory integrity error a synchronous PIE trap is raised. The trap handler is then
responsible for correcting the memory entry and re-starting program execution.
For SPRAM read operations from the LMB interface, either from the DMI module or
another LMB master agent, an access that results in the detection of an uncorrectable
memory integrity error in the requested data half-words causes a bus error to be returned
for the bus transaction. Since the TriCore CPU may not be involved in the transaction, a
separate error is also flagged to the SCU module to optionally generate an NMI trap back
to the core.
Writes to program scratchpad memory are only ever performed from the bus interface.
For write operations of half-word size or greater, the ECC bit values are pre-computed
based on the 16-bit granularity and written to the scratch memory in parallel with the
data. For byte write operations the memory transaction is transformed into a half-word
read-modify-write sequence inside the PMI module. As such, byte write operations may
result in the detection of uncorrectable memory integrity errors, which are handled as
standard read operations.
Instruction Cache (ICACHE)
Since the instruction cache shares the same physical memory as the Scratchpad RAM,
it is similarly configured for memory integrity error protection: six ECC bits are stored per
half-word. ECC protection of the instruction cache is enabled by setting MIECON.PMIEE
to one. When MIECON.PMIEE is zero all uncorrectable memory integrity errors are
ignored.
For instruction fetch requests from the TriCore CPU to ICACHE, the ECC bits are read
along with the data bits of both cache ways, and an uncorrectable error signal generated
for each half-word of each cache way. In the case of a tag hit, the uncorrectable error
signals for the corresponding cache way are passed to the core along with their
corresponding instruction half-words. The corresponding program tag entry is
invalidated such that the next attempt to fetch the instruction cache line will result in a
refill. Whenever an attempt is made to issue an instruction containing an uncorrectable
error a synchronous PIE trap is raised. The trap handler is then responsible for checking
the source of the memory integrity error, and, in the case of the instruction cache, may
immediately return to re-fetch the now invalidated cache line.
Program Tag (PTag)
The program tag stores a 22-bit tag address and 1-bit valid field for each of the two cache
ways in a set. As such the program tag is written with 23-bit granularity and six ECC bits
are associated with each 23-bit tag way. ECC protection of the program tag is enabled
by setting MIECON.PTIEE to one. When MIECON.PTIEE is zero all uncorrectable
memory integrity errors are ignored.