Infineon Technologies TC1784, User Manual

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-21 V1.1, 2011-05
GPTA
®
v5, V1.14
21.3.2.2 Phase Discrimination Logic (PDL)
The GPTA
®
v5 provides two Phase Discrimination Logic cells (PDL0, PDL1) driven by
two signal lines coming from an FPC cell (for description, see Page 21-14 ):
• An event input signal
• A level input signal
Both Phase Discrimination Logic cells are controlled by the Phase Discrimination Logic
Control Register PDLCTR (see
Page 21-171 ).
Each PDL is equipped with an edge detection circuitry, a phase detection circuitry, a PDL
control circuitry, and an output multiplexer. Six output lines are provided by each PDL
Cell:
•
A forward output signal (F0, F1) is driven by one
f
GPTA
clock pulse if an input signal
edge is recognized as forward rotation. These signals can be connected to any Local
Timer Cell via the PDL bus.
• A backward output signal (B0, B1) is driven by one
f
GPTA
clock pulse if an input signal
edge is recognized as backward rotation. This signal can be connected to any Local
Timer Cell via the PDL bus.
• Two pairs of output signals, carrying the bypassed input level and event information
from the driving FPC cells or the angular velocity and error information provided by
the PDL function. These output lines are directly connected to the adjacent Duty
Cycle Measurement Cells, DCM0/DCM1(for PDL0) and DCM2/DCM3 (for PDL1).
The PDL processes the output signal of a 2-sensor or 3-sensor positioning system. With
bit PDLCTR.TSEx = 1, a 3-sensor system execution is selected providing the DCM1
and/or DCM3 cell with information concerning erroneous states in the signal input. When
PDLCTR.TSEx = 0, a 2-sensor system is selected and DCM1 and/or DCM3 are supplied
with the input event and level information from the driving FPC2 and/or FPC5.
The rotation direction, monitored by the connected sensors, is automatically derived
from the sequence in which the input signals change. Each edge detected on an input
signal line generates a pulse on the F0, F1 forward output lines or on the B0, B1
backward output lines. Input jitter, which might occur if a sensor rests near to one of its
switching points, is compensated.
If bit PDLCTR.MUXx = 1, the trigger output signal to DCM0/DCM2 (angular velocity
information) is driven by a boolean ‘OR’ operation of the corresponding forward trigger
and backward trigger signal while the level output signal at DCM0/DCM2 is at fixed high
level. In this case, every pulse at F0/B0 and F1/B1 generates a rising edge at the
DCM0/DCM trigger signal.
If bit PDLCTR.MUXx = 0, the associated DCM0/DCM2 signals are directly connected
with the input event and level signals from the driving FPC0/FPC3.
To calculate the sensor’s current position, the associated LTCs should be clocked with
the PDL forward and backward output pulses. A software operation, subtracting the
backward counter contents from the forward counter contents, provides the absolute