Infineon Technologies TC1784, User Manual

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TC1784
Program Memory Unit (PMU)
User´s Manual 5-25 V1.1, 2011-05
PMU, V1.47
In the table above, also the number of wait states for accesses with read buffer hit and
with prefetch line hit (both only in PFlash available) are shown, which are both identical
for all frequencies.
The wait state control bit in FCON for additional wait state for the ECC cycle during
PFlash and DFlash accesses need not be changed by the user.
Note: The number of wait states may be changed in register FCON at any time, as long
as the new number considers the maximum frequency as described in table
above; this change can also be performed with code executed from Program
Flash.
Mixed Accesses to PFlash and DFlash
Parallel read accesses to the Program Flash and to the Data Flash are not supported.
The accesses are serialized on LMB bus and thus also on the Flash array interface.
Therefore, a burst transfer from PFlash cannot be interrupted by a DFlash cycle. If a
DFlash request is received during prefetching the PFlash, the prefetch access is aborted
and the DFlash access is immediately started. Prefetched data or code is only inhibited
and prefetching PFlash is aborted in case of a new request (data or code) to PFlash.
99 MHz < f
LMB
≤ 118 MHz 6 0 min. 1
79 MHz < f
LMB
≤ 99 MHz 5 0 min. 1
59 MHz < f
LMB
≤ 79 MHz 4 0 min. 1
39.5 MHz < f
LMB
≤ 59 MHz 3 0 min. 1
19.5 MHz < f
LMB
≤ 39.5 MHz 2 0 min. 1
f
LMB
≤ 19.5 MHz 1 0 min. 1
1) The maximum operating frequency of a device is documented in its data sheet.
Table 5-2 Selection of Wait States in Relation to Operating Frequency for Flash
modules with Ta=50 ns
(cont’d)
Operating Frequency
1)
WS for
Initial
Access
WS for
Read Buffer
Hit Access
WS for
Prefetch
Line Hit