Infineon Technologies TC1784, User Manual

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-126 V1.1, 2011-05
DMA, V3.03
11.5 Memory Checker Module
The Memory Checker Module (MCHK) includes two parallel Cyclic Redundancy
Checkers (CRCs) that can be used to check the data consistency of two memories in
parallel.
11.5.1 Functional Description
The Memory Checker module is connected to the DMA Peripheral Interface and can be
accessed via the SPB. Preferable the module is used in combination with the DMA as it
as described hereafter: a DMA channel can be used to read 8-bit, 16-bit, or 32-bit data
from an address area and to write the data in one of the two memory checker input
register. With each write operation to the choosen memory checker input register a
polynomial checksum calculation is triggered and the result of the calculation is stored
in the corresponding memory checker result register.
In order to start a memory check sequence, the memory checker result register must be
initialized (e.g. written with FFFFFFFF
H
or with a desired start value) and a DMA
transaction must be set up (start address, length, etc.). When programming the DMA
channel for the memory checker with CHCRmn.RROAT = 1, one DMA transfer request
(software or hardware triggered) starts the DMA transaction.
During the read move operations of the DMA transaction, data is always read from the
memory and then written into the memory checker input register for the polynomial
checksum calculation. At the end of the transaction (CHSRmn.TCOUNT = 0), an
interrupt can be generated by the DMA channel (if CHCRmn.RROAT = 1), and the
memory checker result register can be read out by software.
The memory checker uses the standard Ethernet polynomial, which is given by:
G
32
= x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1 (11.1)
Note: Although the polynomial above is used for generation, the generation algorithm
differs from the one that is used by the Ethernet protocol.