Infineon Technologies TC1784, User Manual

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TC1784
Peripheral Control Processor (PCP)
User´s Manual 10-56 V1.1, 2011-05
PCP, V2.09
10.13 FPI Interface
Any FPI Bus master (on the TC1784’s System Peripheral Bus) can access the three
distinct PCP address ranges from the FPI Bus side, on the other hand the PCP master
interface can also access any address on the FPI bus. Normally, the CPU initializes the
control registers via FPI Bus access. Thereafter, the PCP should not access its control
registers itself through PCP instructions. Apart from the access via FPI Bus, there is no
direct way to the PCP control registers.
Accesses to the PCP control and status register, the PRAM, and the CMEM are detailed
in the following sections.
10.13.1 Access to the PCP Control Registers from the FPI Bus
FPI Bus accesses to the PCP control registers must always be performed in Supervisor
Mode with word accesses; byte or half-word accesses will result in a bus error.
All PCP control registers can be read at any time. Register PCP_CS can be optionally
Endinit-protected via bit PCP_CS.EIE (see
Page 67 ). If CS.EIE & ENDINIT = True, then
any write access to this register is inhibited. The clock control register PCP_CLC is
endinit-protected. The Software In-System Test register is also endinit-protected.
Additionally (see below) for High Integrity applications the entire Register content can be
ENDINIT protected (see below).
10.13.1.1 PCP Control Register Protection
To allow the PCP to handle system critical tasks it is necessary to ensure that the PCP
can operate properly regardless of a failure in another part of the system or the PCP
itself. This means that it is necessary to protect the Control and Status Registers from
such failures.
The configuration register content can only be modified via the FPI. Protection of the
PCP configuration therefore consists of prevention of unwanted FPI writes to the PCP
registers.
The normal model of PCP operation is that the PCP is configured at system initialization
and the configuration remains unchanged for the duration of operation of the system.
Protection therefore consists of a simple locking scheme to prevent any write to registers
once the PCP has been configured. Once the PCP has been configured (at system
initialization) the Registers can be locked such that, unless ENDINIT is clear, all
incoming FPI write accesses are issued with an error response and the PCP
configuration will remain unmodified.
If is required to modify content of the registers once they have been locked it is
necessary to clear the ENDINIT bit (via the system Watchdog Timer) such that the
Registers become writeable again.
Regardless of protection the entire Register content remains readable via FPI.