Infineon Technologies TC1784, User Manual

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-204 V1.1, 2011-05
GPTA
®
v5, V1.14
The Multiplexer Register Array Data In register is used to write data to the Multiplexer
Register Array FIFO. The Multiplexer Register Array Data Out register is used to read
data from the Multiplexer Register Array FIFO.
WCRES 1 w Write Count Reset
Writing WCRES with 1 while the array is disabled
(MAEN = 0), resets the write cycle counter to zero and
the FIFO written sequentially (initialized). WCRES is
always read as 0.
FIFOFULL 2 r FIFO Full Status
0
B
FIFO not completely written (write access to
MRADIN allowed).
1
B
FIFO completely written (write access to MRADIN
ignored). Must be re-enabled via WCRES before
array can be re-initialized.
FIFOFILLCNT [13:8] r FIFO Fill Count
This bit field shows the current contents of the write
cycle counter.
0 [7:3],
[31:14] r Reserved
Read as 0; should be written with 0.
GPTA0_MRADIN
GPTA0 Multiplexer Register Array Data In Register
(03C
H
) Reset Value: 0000 0000
H
31 0
DATAIN
w
Field Bits Type Description
DATAIN [31:0] w FIFO Write Data
This register contains the FIFO write data as defined for the
Output Multiplexer Control Registers and the Input Multiplexer
Control Registers.
Field Bits Type Description