Infineon Technologies TC1784, User Manual

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TC1784
Synchronous Serial Interface (SSC)
User´s Manual 17-5 V1.1, 2011-05
SSC, V1.5
17.1.2.1 Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its Control Register, CON.
Status information is contained in its Status Register, STAT.
The shift register of the SSC is connected to both the transmit pin and the receive pin via
the pin control logic (see block diagram in
Figure 17-2 ). Transmission and reception of
serial data are synchronized and take place at the same time, that is, the same number
of transmitted bits is also received. Transmit data is written into the Transmit Buffer TB.
It is moved to the shift register as soon as this is empty, including the generated parity
bit for the transmit data if transmit parity mode is enabled (CON.PARTEN = 1). An SSC
master (CON.MS = 1) immediately begins transmitting, while an SSC slave
(CON.MS = 0) will wait for an active shift clock. When the transfer starts, the busy flag
STAT.BSY is set, and the transmit interrupt request line (TIR) will be activated to indicate
that the Transmit Buffer Register (TB) may be reloaded. When the number of bits as
programmed in CON.BM have been received, the data bits of the shift register are
moved to the Receive Buffer Register (RB) right-aligned, the receive parity bit (if enabled
by CON.PARREN = 1) is loaded into STAT.PARRVAL, and the receive interrupt request
line (RIR) will be activated. If no further transfer is to take place (TB is empty), STAT.BSY
will be cleared at the same time. Software should not modify STAT.BSY, as this flag is
hardware-controlled.
Note: Only one SSC can be master at a given time.
The following features of the serial data bit transfer can be programmed:
•
The data width can be selected from 2 to 16 data bits (with parity: 1 to 15 data bits)
• A transfer may start with the LSB or the MSB of the data bits
• The shift clock may be idle low or idle high
• The data bits may be shifted with the leading or trailing edge of the clock signal
• The baud rate (shift clock) can be set from 686.65 bit/s up to 45.0Mbit/s
(@ 90 MHz module clock)
• The shift clock can be generated (master) or received (slave)
These features allow the SSC to be adapted to a wide range of applications that require
serial data transfer.
The Data Width Selection supports the transfer of frames of any data length from 2-bit
“characters” up to 16-bit “characters”. If parity is enabled, the maximum number of data
bits of a frame is 15-bit.
Starting the serial data bit transfer with the LSB (CON.HB = 0) allows communication
with devices such as an SSC device in Synchronous Mode, or 8051-like serial interfaces.
If parity mode is enabled, the parity bit preceeds the serial data bit transfer (see
Page 17-12 ).
Starting with the MSB (CON.HB = 1) allows operation compatible with the SPI interface.
If parity mode is enabled, the parity bit follows the serial data bit transfer (see
Page 17-12 ).