Infineon Technologies TC1784, User Manual

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TC1784
Peripheral Control Processor (PCP)
User´s Manual 10-130 V1.1, 2011-05
PCP, V2.09
10.18.40 Instruction Timing
This section gives some information about the duration of PCP instructions. Please note
that there are various conditions that can further affect the duration of PCP instructions
(e.g. external FPI accesses from another FPI Bus master to the PCP memories stall the
PCP Processor Core).
Note: The clock cycles listed in Table 36 are PCP core clock cycles. When running in
2:1 clocking mode the maximum allowed PCP core clock frequency is 180 MHz
(resulting in a minimum PCP core clock cycle time of 5.6ns). When running in 1:1
clocking mode the maximum PCP core clock frequency is the same as the
maximum System Peripheral Bus frequency. In the TC1784 the System
Peripheral Bus (which is an FPI Bus) is clocked with f
SYS
, resulting in a minimum
PCP core clock cycle time of 11.1ns (in 1:1 clocking mode).
Note: Where an execution time is stated for an FPI instruction this is always a minimum
value. A number of FPI instructions must wait for the completion of an FPI
transaction (or transactions). When running in 2:1 mode each FPI clock cycle
consists of two core clock frequencies. Where this applies the cycle count is
shown with an “FPI” superscript designation (e.g. “3
FPI
”). In addition there may be
an additional single core clock cycle taken according to alignment of execution of
an FPI instruction relative to an FPI clock edge.
SHR – – – yes
3)
yes
SHL – – yes yes yes
ST – – – – –
SUB – yes yes yes yes
XCH – – – yes yes
XOR – – – yes yes
1) CN1Z is only modified by the BCOPY, COPY or EXIT instructions if the instruction has been configured to
decrement R6.CNT1 (for BCOPY/COPY CNC = 1 or CNC = 2, for EXIT EC = 1). All other instructions have
no effect on the CN1Z flag.
2) For the LD.I type of instruction, flag N is always cleared, as bit 31 of the result is always 0.
3) Flag N is always cleared, as bit 31 of the result is always 0.
Table 36 Instruction Timing
Instruction Number of Clock Cycles Comments Notes
Control
NOP 1 – –
Table 35 Flag Updates (cont’d)
Instruction CN1Z V C N Z