Infineon Technologies TC1784, User Manual

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-101 V1.1, 2011-05
DMA, V3.03
11.4 DMA Module Implementation
This section describes the TC1784 DMA module interfaces with the clock control,
interrupt control, and address decoding.
Figure 11-28 shows the TC1784-specific implementation details and interconnections of
the DMA module. The DMA module is supplied with a separate clock control, address
decoding, interrupt control, and the request input wiring matrix.
Figure 11-28 DMA Module Implementation and Interconnections
The request sources of the peripheral modules (ADC0, MSC0, MLI0, FADC, MultiCAN,
and SCU) are associated with Interrupt Node Pointers and individual interrupt enable
bits. As a result, each of the internal requests of a module can be routed independently
to any of the interrupt output lines (INT_Ox) of the module.
DMA
Interrupt
Nodes
MCA06176
Clock
Control
f
DMA
SR[7:0]
DMA Controller
Arbiter/
Switch
Control
Bus
Switch
FP
I B
us
In
te
rf
ac
e
LM
B
B
us
In
te
rf
a
ce
D
M
A Pe
ri
ph
er
al
In
te
rf
ac
e
Memory
Checker
MLI0
System
Peripheral
Bus
LMB Bus
Address
Decoder
DMA Interrupt Control
CH0n_OUT
MLI Interrupt Nodes
DMA
Channels
00-07
DMA Sub-Block m
Request
Selection/
Arbitration
Transaction
Control Unitl
4
DMA
Requests
of
On-chip
Periph.
Units
Cerberus