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TC1784

Interrupt System

 

User´s Manual

13-9

V1.1, 2011-05

Interrupt, V1.4

 

IE

8

rwh

Global Interrupt Enable Bit

The interrupt enable bit globally enables the CPU 
service request system. Whether or not a service 
request is delivered to the CPU depends on the 
individual Service Request Enable Bits (SRE) in the 
SRNs, and the current state of the CPU.
IE is automatically updated by hardware on entry and 
exit of an Interrupt Service Routine (ISR).
IE is cleared to 0 when an interrupt is taken, and is 
restored to the previous value when the ISR executes 
an RFE instruction to terminate itself.
IE can also be updated through the execution of the 
ENABLE, DISABLE, MTCR, and BISR instructions.
0

Interrupt system is globally disabled

1

Interrupt system is globally enabled

PIPN

[23:16] rh

Pending Interrupt Priority Number

PIPN is a read-only bit field that is updated by the ICU 
at the end of each interrupt arbitration process. It 
indicates the priority number of the pending service 
request. PIPN is set to 0 when no request is pending, 
and at the beginning of each new arbitration process.
00

H

No valid pending request

YY

H

A request with priority YY

H

 is pending

CARBCYC

[25:24] rw

Number of Arbitration Cycles

CARBCYC controls the number of arbitration cycles 
used to determine the request with the highest priority.
00

B

4 arbitration cycles (default)

01

B

3 arbitration cycles

10

B

2 arbitration cycles

11

B

1 arbitration cycle

CONECYC

26

rw

Number of Clocks per Arbitration Cycle Control

The CONECYC bit determines the number of system 
clocks per arbitration cycle.  For the TC1784 this bit 
can be set to 1 (for SPB frequencies up to the max SPB 
frequency as defined in the Data Sheet).
0

2 clocks per arbitration cycle (default)

1

1 clock per arbitration cycle

0

[15:9], 
[31:27]

r

Reserved

Read as 0; should be written with 0.

Field

Bits

Type Description

Summary of Contents for TC1784

Page 1: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...

Page 2: ...ry terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written ap...

Page 3: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...

Page 4: ...M bit 5 PMU Enhanced description of ALSE mechanism Added ALSE disable configuration 6 Data Access Overlay OVC No functional changes 7 BootROM Content No functional changes 8 Memory Maps No functional changes Corrected name PCODE to CMEM 9 General Purpose I O Ports and Peripheral I O Lines The PDx encodings 011 and 110 in the where updated These encodings are used now for the A2 Strong Sharp and Me...

Page 5: ...nections to ECTTx and from INT_0_15 reworked removed Modified footnote about minimal required frequency at bootstraping Corrected TTFMR and TTSR reset values Added register bit FDR FDIS bit Corrected description of RXPND and TXPND Set by hardware and must be reset by software Added register CAN_EDCR 20 E Ray Corrected IOCR settings in Table of Port connections 21 GPTAv5 No functional changes Impro...

Page 6: ...ithin this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com ...

Page 7: ... 1 Clock Generation Unit 1 16 1 3 4 2 Features of the Watchdog Timer 1 16 1 3 4 3 Reset Operation 1 16 1 3 4 4 External Interface 1 17 1 3 4 5 Die Temperature Measurement 1 17 1 3 5 General Purpose I O Ports and Peripheral I O Lines 1 17 1 3 6 Program Memory Unit PMU 1 18 1 3 6 1 Boot ROM 1 19 1 3 6 2 Overlay RAM and Data Acquisition 1 19 1 3 6 3 Emulation Memory Interface 1 19 1 3 6 4 Tuning Prot...

Page 8: ... Diagram 2 3 2 2 2 Instruction Fetch Unit 2 4 2 2 3 Execution Unit 2 5 2 2 4 General Purpose Register File 2 6 2 3 CPU Implementation Specific Features 2 7 2 3 1 Context Save Areas 2 7 2 3 2 Program Counter Register PC 2 7 2 3 3 Interrupt System 2 9 2 3 4 Trap System 2 9 2 3 5 Memory Integrity Error Handling 2 10 2 3 5 1 Program Side Memories 2 10 2 3 5 2 Data Side Memories 2 12 2 3 5 3 TriCore 1 ...

Page 9: ...es 2 72 2 14 2 LMB Access Priorities 2 73 2 14 3 Scratchpad RAM 2 73 2 14 4 Instruction Cache 2 74 2 14 5 Program Line Buffer 2 75 2 14 6 PMI Registers 2 76 2 14 6 1 PMI Register Descriptions 2 77 2 15 Data Memory Interface DMI 2 83 2 15 1 DMI Features 2 83 2 15 2 LMB Access Priorities 2 84 2 15 3 Local Data RAM LDRAM 2 84 2 15 4 Data Cache 2 84 2 15 5 Data Line Buffer 2 85 2 15 6 DMI Trap Generat...

Page 10: ...2 Configuration Registers 3 71 3 3 External Interface 3 76 3 3 1 External Service Requests ESRx 3 76 3 3 1 1 ESRx as Reset Request Trigger 3 76 3 3 1 2 ESRx as Reset Output 3 77 3 3 1 3 ESR Registers 3 78 3 3 2 External Request Unit ERU 3 85 3 3 2 1 Introduction 3 85 3 3 2 2 ERU Pin Connections 3 87 3 3 2 3 External Request Select Unit ERS 3 87 3 3 2 4 Event Trigger Logic ETL 3 88 3 3 2 5 Connecti...

Page 11: ...tion During Power Saving Modes 3 138 3 8 4 4 Suspend Mode Support 3 139 3 8 5 Watchdog Timer Registers 3 139 3 8 5 1 Watchdog Timer Control Register 0 3 139 3 8 5 2 Watchdog Timer Control Register 1 3 141 3 8 5 3 Watchdog Timer Status Register 3 143 3 9 Emergency Stop Output Control 3 146 3 9 1 Emergency Stop Register 3 148 3 10 Interrupt Generation 3 150 3 10 1 Interrupt Control Registers 3 151 3...

Page 12: ...5 3 Reaction of a Busy Slave 4 23 4 5 4 Address Alignment Rules 4 24 4 5 5 FPI Bus Basic Operations 4 24 4 6 FPI Bus Control Unit SBCU 4 26 4 6 1 FPI Bus Arbitration 4 26 4 6 1 1 Arbitration on the System Peripheral Bus 4 26 4 6 1 2 Starvation Prevention 4 28 4 6 2 FPI Bus Error Handling 4 28 4 6 3 BCU Debug Support 4 31 4 6 3 1 Address Triggers 4 31 4 6 3 2 Signal Status Triggers 4 32 4 6 3 3 Gra...

Page 13: ...d Sequence Definitions 5 28 5 6 3 4 Functional Command Description 5 31 5 6 3 5 Sector Page and Block Addressing 5 40 5 6 3 6 Register Addresses and Access Restrictions 5 43 5 6 3 7 Flash Status Definition 5 46 5 6 3 8 Flash Configuration Control 5 53 5 6 3 9 Flash Identification Register 5 59 5 6 4 Error Correction and Margin Control 5 60 5 6 4 1 Dynamic Error Correction 5 60 5 6 4 2 Margin Check...

Page 14: ...7 2 7 3 External Start 7 2 7 4 Bootstrap Loading 7 3 7 4 1 Common Procedures for all Bootloaders 7 3 7 4 2 ASC Bootstrap Loader 7 4 7 4 3 CAN Bootstrap Loader 7 5 7 5 Alternate Boot Modes 7 6 7 5 1 Header Check in Alternate Boot Modes 7 6 7 6 Startup Errors Handling 7 9 7 7 Notes and usage hints 7 10 7 7 1 Conditions upon user code start 7 10 7 7 2 RAMs Handling 7 10 7 7 3 Influencing the next SSW...

Page 15: ... Registers 9 34 9 4 3 1 Port 1 Output Register 9 34 9 4 3 2 Port 1 Output Modification Register 9 34 9 4 3 3 Port 1 Input Output Control Register 12 9 35 9 4 3 4 Port 1 Input Register 9 35 9 4 3 5 Port 1 Pad Driver Mode Register and Pad Classes 9 35 9 4 3 6 Port 1 Emergency Stop Register 9 36 9 5 Port 2 9 37 9 5 1 Port 2 Configuration 9 37 9 5 2 Port 2 Function Table 9 37 9 5 3 Port 2 Registers 9 ...

Page 16: ...ster 9 66 9 9 2 2 Port 6 Emergency Stop Register 9 66 9 10 Port 7 9 67 9 10 1 Port 7 Registers 9 67 9 10 2 Port 7 Functions 9 68 9 10 2 1 Port 7 Pad Driver Mode Register 9 73 9 10 2 2 Port 7 Emergency Stop Register 9 73 9 11 Port 8 9 74 9 11 1 Port 8 Registers 9 74 9 11 2 Port 8 Functions 9 75 9 11 2 1 Port 8 Pad Driver Mode Register 9 79 9 11 2 2 Port 8 Emergency Stop Register 9 79 9 12 Port 9 9 ...

Page 17: ...and CR7 10 19 10 4 2 4 Context Save Operation for CR6 and CR7 10 23 10 4 2 5 Initialization of the Contexts 10 26 10 4 2 6 Context Save Optimization 10 26 10 4 3 Channel Programs 10 27 10 4 3 1 Channel Restart Mode 10 27 10 4 3 2 Channel Resume Mode 10 28 10 5 PCP Operation 10 30 10 5 1 PCP Initialization 10 30 10 5 2 Channel Invocation and Context Restore Operation 10 30 10 5 3 Channel Exit and C...

Page 18: ...mitives 10 48 10 12 2 Load and Store 10 49 10 12 3 Arithmetic and Logical Instructions 10 50 10 12 4 Bit Manipulation 10 52 10 12 5 Flow Control 10 52 10 12 6 Addressing Modes 10 53 10 12 6 1 FPI Bus Addressing 10 53 10 12 6 2 PRAM Addressing 10 54 10 12 6 3 Bit Addressing 10 54 10 12 6 4 Flow Control Destination Addressing 10 54 10 13 FPI Interface 10 56 10 13 1 Access to the PCP Control Register...

Page 19: ... 10 18 2 Counter Operation for COPY Instruction 10 98 10 18 3 Counter Operation for BCOPY Instruction 10 99 10 18 4 Divide and Multiply Instructions 10 100 10 18 5 ADD 32 bit Addition 10 101 10 18 6 AND 32 bit Logical AND 10 102 10 18 7 BCOPY DMA Operation 10 103 10 18 8 CHKB Check Bit 10 104 10 18 9 CLR Clear Bit 10 104 10 18 10 COMP 32 bit Compare 10 105 10 18 11 COPY DMA Instruction 10 106 10 1...

Page 20: ...of Low Priority Tasks 10 143 10 20 5 Code Reuse Across Channels Call and Return 10 143 10 20 6 Case like Code Switches Computed Go To 10 144 10 20 7 Simple DMA Operation 10 144 10 20 7 1 COPY Instruction 10 144 10 20 7 2 BCOPY Instruction Burst Copy 10 145 10 21 PCP Programming Notes and Tips 10 146 10 21 1 Notes on PCP Configuration 10 146 10 21 2 General Purpose Register Use 10 146 10 21 3 Use o...

Page 21: ...Generation 11 29 11 2 12 Interrupts 11 31 11 2 12 1 Channel Interrupts 11 31 11 2 12 2 Transaction Lost Interrupt 11 33 11 2 12 3 Move Engine Interrupts 11 34 11 2 12 4 Wrap Buffer Interrupts 11 36 11 2 12 5 Interrupt Request Compressor 11 37 11 2 13 Pattern Detection 11 38 11 2 13 1 Pattern Compare Logic 11 40 11 2 13 2 Pattern Detection for 8 bit Data Width 11 41 11 2 13 3 Pattern Detection for ...

Page 22: ... Pad Pull Up and Pull Down 12 6 12 4 External Bus Arbitration 12 7 12 4 1 Arbitration Modes 12 8 12 4 1 1 No Bus Arbitration Mode 12 8 12 4 1 2 Sole Master Arbitration Mode 12 8 12 5 Start Up Boot Process 12 9 12 6 Clocking Strategy and Local Clock Generation 12 9 12 6 1 Local Clock Divider 12 9 12 6 2 Standby Mode 12 9 12 7 External BusOperation 12 10 12 7 1 External Memory Regions 12 11 12 7 2 C...

Page 23: ...ELx 12 52 12 11 5 Bus Configuration Register BUSRCONx 12 54 12 11 6 Bus Write Configuration Register BUSWCONx 12 57 12 11 7 Bus Read Access Parameter Register BUSRAPx 12 59 12 11 8 Bus Write Access Parameter Register BUSWAPx 12 62 12 11 9 Test Control Configuration Register USERCON 12 65 13 Interrupt System 13 1 13 1 Overview 13 1 13 2 Service Request Nodes 13 3 13 2 1 Service Request Control Regi...

Page 24: ...ystem Timer STM 14 1 14 1 Overview 14 1 14 2 Operation 14 1 14 2 1 Resolution and Ranges 14 4 14 2 2 Compare Register Operation 14 5 14 2 3 Compare Match Interrupt Control 14 6 14 3 STM Registers 14 7 14 3 1 Clock Control Register 14 9 14 3 2 Timer Capture Registers 14 11 14 3 3 Compare Registers 14 14 14 3 4 Interrupt Registers 14 17 14 4 STM Module Implementation 14 21 14 4 1 On chip Service Req...

Page 25: ...us Reception 16 10 16 1 4 3 Synchronous Timing 16 11 16 1 5 Baud Rate Generation 16 12 16 1 5 1 Baud Rates in Asynchronous Mode 16 13 16 1 5 2 Baud Rates in Synchronous Mode 16 16 16 1 6 Hardware Error Detection Capabilities 16 17 16 1 7 Interrupts 16 17 16 2 ASC Kernel Registers 16 19 16 2 1 Control Registers 16 20 16 2 2 Data Registers 16 28 16 3 ASC0 ASC1 Module Implementation 16 30 16 3 1 Inte...

Page 26: ...p Connections 17 46 17 3 4 SSC0 SSC1 SSC2 Module Related External Registers 17 47 17 3 4 1 Clock Control 17 48 17 3 4 2 Port Control 17 52 17 3 4 3 Interrupt Control Registers 17 58 17 3 5 Address Map of the SSC Modules 17 59 18 Micro Second Channel MSC 18 1 18 1 MSC Kernel Description 18 3 18 1 1 Overview 18 3 18 1 2 Downstream Channel 18 5 18 1 2 1 Frame Formats and Definitions 18 6 18 1 2 2 Shi...

Page 27: ... 4 1 Input Output Function Selection 18 69 18 3 5 On Chip Connections 18 71 18 3 5 1 EMGSTOPMSC Signal from SCU 18 71 18 3 5 2 DMA Controller Service Requests 18 71 18 3 6 Interrupt Control Registers 18 72 18 3 7 MSC0 Address Map 18 73 19 Controller Area Network Controller MultiCAN 19 1 19 1 CAN Basics 19 2 19 1 1 Addressing and Bus Arbitration 19 2 19 1 2 CAN Frame Formats 19 3 19 1 2 1 Data Fram...

Page 28: ... 19 41 19 3 10 2 Frame Transmission 19 44 19 3 11 Message Object Functionality 19 47 19 3 11 1 Standard Message Object 19 47 19 3 11 2 Single Data Transfer Mode 19 47 19 3 11 3 Single Transmit Trial 19 47 19 3 11 4 Message Object FIFO Structure 19 48 19 3 11 5 Receive FIFO 19 50 19 3 11 6 Transmit FIFO 19 51 19 3 11 7 Gateway Mode 19 52 19 3 11 8 Foreign Remote Requests 19 54 19 4 MultiCAN Kernel ...

Page 29: ... 5 2 8 Identification Registers 20 162 20 5 2 9 Input Buffer 20 164 20 5 2 10 Output Buffer 20 175 20 6 Functional Description 20 192 20 6 1 Communication Cycle 20 192 20 6 1 1 Static Segment 20 192 20 6 1 2 Dynamic Segment 20 193 20 6 1 3 Symbol Window 20 193 20 6 1 4 Network Idle Time NIT 20 193 20 6 1 5 Configuration of Network Idle Time NIT Start and Offset Correction Start 20 193 20 6 2 Commu...

Page 30: ...ffers 20 222 20 6 8 4 Frame Transmission 20 223 20 6 8 5 NULL Frame Transmission 20 224 20 6 9 Receive Process 20 225 20 6 9 1 Frame Reception 20 225 20 6 9 2 NULL Frame reception 20 226 20 6 10 FIFO Function 20 226 20 6 10 1 Description 20 226 20 6 10 2 Configuration of the FIFO 20 227 20 6 10 3 Access to the FIFO 20 228 20 6 11 Message Handling 20 228 20 6 11 1 Host access to Message RAM 20 228 ...

Page 31: ...ctionality of GPTA0 21 5 21 2 2 Functionality of LTCA2 21 7 21 3 GPTA0 Kernel Description 21 8 21 3 1 GTPA Units 21 9 21 3 2 Clock Generation Cells 21 10 21 3 2 1 Filter and Prescaler Cell FPC 21 12 21 3 2 2 Phase Discrimination Logic PDL 21 21 21 3 2 3 Duty Cycle Measurement Cell DCM 21 26 21 3 2 4 Digital Phase Locked Loop Cell PLL 21 30 21 3 2 5 Clock Distribution Cell CDC 21 35 21 3 3 Signal G...

Page 32: ... 11 Service Request Registers 21 219 21 5 LTCA Kernel Description 21 229 21 5 1 Local Timer Cell LTC00 to LTC63 21 230 21 5 2 Input Output Line Sharing Block IOLS 21 230 21 5 2 1 Output Multiplexer 21 232 21 5 2 2 LTC Input Multiplexing Scheme 21 237 21 5 2 3 Multiplexer Register Array Programming 21 240 21 5 3 Interrupt Sharing Block IS 21 243 21 6 LTCA Kernel Registers 21 245 21 6 1 Bit Protecti...

Page 33: ... MLI Frame Structure 22 10 22 1 2 1 General Frame Layout 22 11 22 1 2 2 Copy Base Address Frame 22 12 22 1 2 3 Write Offset and Data Frame 22 13 22 1 2 4 Optimized Write Frame 22 14 22 1 2 5 Discrete Read Frame 22 15 22 1 2 6 Optimized Read Frame 22 16 22 1 2 7 Command Frame 22 17 22 1 2 8 Answer Frame 22 18 22 1 3 Handshake Description 22 19 22 1 3 1 Handshake Signals 22 21 22 1 3 2 Error free Ha...

Page 34: ...ormal Frame Received Move Engine Terminated Event 22 65 22 2 6 4 Interrupt Command Frame Event 22 66 22 2 6 5 Command Frame Received Event 22 67 22 2 7 Baud Rate Generation 22 68 22 2 8 Automatic Register Overwrite 22 69 22 3 Operating the MLI 22 70 22 3 1 Connection Setup 22 71 22 3 2 Local Transmitter and Pipe Setup 22 72 22 3 3 Remote Receiver Setup 22 72 22 3 4 Remote Transmitter and Local Rec...

Page 35: ...Port Control and Connections 22 145 22 5 11 1 Input Output Function Selection 22 145 22 5 12 On Chip Connections 22 148 22 5 12 1 Service Request Output Connections 22 148 22 5 12 2 Break Signals 22 149 22 5 12 3 Trigger Input Signals 22 149 22 5 13 Access Protection 22 149 22 5 14 MLI0 MLI1 Transfer Window Address Maps 22 150 22 5 15 MLI0 Address Map 22 151 23 Analog to Digital Converter ADC 23 1...

Page 36: ...equest Source Handling 23 50 23 2 9 1 Overview 23 50 23 2 9 2 Scan Sequence Operation 23 51 23 2 9 3 Request Source Event and Interrupt 23 52 23 2 10 Scan Request Source Registers 23 54 23 2 10 1 Conversion Request Control Registers 23 54 23 2 10 2 Conversion Request Pending Registers 23 56 23 2 10 3 Conversion Request Mode Registers 23 57 23 2 11 Sequential Request Source Handling 23 60 23 2 11 1...

Page 37: ...6 5 Event Flag Register 23 105 23 2 16 6 Event Flag Clear Register 23 107 23 2 16 7 Event Node Pointer Registers 23 108 23 2 17 Multiplexer Test Support 23 111 23 2 18 External Multiplexer Control 23 112 23 2 19 Synchronized Conversions for Parallel Sampling 23 115 23 2 20 Equidistant Sampling 23 118 23 2 21 Access Protection 23 120 23 2 22 Broken Wire Detection 23 121 23 2 23 Additional Feature R...

Page 38: ...4 2 9 Calibration 24 21 24 2 9 1 Offset Calibration 24 22 24 2 10 Interrupt Generation 24 23 24 3 FADC Register Description 24 26 24 3 1 System Registers 24 30 24 3 1 1 Clock Control Register 24 30 24 3 1 2 Fractional Divider Register 24 31 24 3 1 3 Module Identification Register 24 33 24 3 1 4 Service Request Control Registers 24 34 24 3 2 Global Registers 24 35 24 3 2 1 Conversion Request Status...

Page 39: ...s Manual L 33 V1 1 2011 05 24 4 Implementation of FADC 24 64 24 4 1 Register Overview 24 64 24 4 2 Interfaces of the FADC Module 24 65 24 4 3 FADC Connections 24 66 24 4 4 Service Request Connections 24 67 24 4 5 Clock Control 24 69 ...

Page 40: ... and the TriCore Architecture are documented in the section covering each such subject 1 1 1 Related Documentations A complete description of the TriCore architecture is found in the document entitled TriCore Architecture Manual The architecture of the TC1784 is described separately this way because of the configurable nature of the TriCore specification Different versions of the architecture may ...

Page 41: ...cript letter B as in 111B When the extent of register fields groups register bits or groups of pins are collectively named in the body of the document they are represented as NAME A B which defines a range for the named group from B to A Individual bits signals or pins are given as NAME C where the range of the variable C is given in the text For example CFG 2 0 and SRPN 0 Units are abbreviated as...

Page 42: ... fields are reserved The detailed description of these bit fields can be found in the register descriptions rw The bit or bit field can be read and written rwh As rw but bit or bit field can be also set or reset by hardware r The bit or bit field can only be read read only w The bit or bit field can only be written write only A read to this register will always give a default value back rh This bi...

Page 43: ...ccess to this address range generates a Bus Error nBE Indicates that no Bus Error is generated when accessing this address range even though it is either an access to an undefined address or the access does not follow the given rules nE Indicates that no Error is generated when accessing this address or address range even though the access is to an undefined address or address range True for CPU a...

Page 44: ...FADC Fast Analog to Digital Converter FAM Flash Array Module FCS Flash Command State Machine FIM Flash Interface and Control Module FPI Flexible Peripheral Interconnect Bus FPU Floating Point Unit GPIO General Purpose Input Output GPR General Purpose Register GPTA General Purpose Timer Array ICACHE Instruction Cache I O Input Output JTAG Joint Test Action Group IEEE1149 1 LBCU Local Memory Bus Con...

Page 45: ...Loop PCODE PCP Code Memory PFLASH Program Flash Memory PMI Program Memory Interface PMU Program Memory Unit PRAM PCP Parameter RAM RAM Random Access Memory RISC Reduced Instruction Set Computing SBCU System Peripheral Bus Control Unit SCU System Control Unit SFR Special Function Register SPB System Peripheral Bus SPRAM Scratch Pad RAM SRAM Static Data Memory SRN Service Request Node SSC Synchronou...

Page 46: ...ol Processor standalone data operations and interrupt servicing DMA Controller DMA operations and interrupt servicing General purpose timers High performance on chip buses On chip debugging and emulation facilities Flexible interconnections to external components Flexible power management The TC1784 is a high performance microcontroller with TriCore CPU program and data memories buses bus arbitrat...

Page 47: ...terrupts System Peripheral Bus System Peripheral Bus SPB SSC0 SBCU Bridge SMIF DMI LDRAM DCACHE CPS BCU PMU GPTA0 Multi CAN 3 Nodes 128 MO ASC0 ASC1 MSC0 LVDS SSC1 STM SCU Ports 1 3V 3 3V Ext Supply Ext Request Unit LTCA2 2 5 MB PFlash 128 KB DFlash 8 KB OVRAM 16 KB BROM ADC0 ADC1 BlockDiagram TC1784 M M S 3 3V Ext FADC Supply 24 KB SPRAM 16 KB ICACHE Configurable 124 KB LDRAM 4 KB DCACHE Configur...

Page 48: ...PU clock frequency 180 MHz1 2 Maximum PCP clock frequency 180 MHz3 2 Maximum system clock frequency 90 MHz4 2 1 For CPU frequencies 90 MHz 2 1 mode has to be enabled CPU 2 1 mode means fFPI 0 5 fCPU 2 Pls Note valid for PG LFBGA 292 2 Max frequency for the other TC1784 package variants might be lower 3 For PCP frequencies 90 MHz 2 1 mode has to be enabled PCP 2 1 mode means fFPI 0 5 fPCP 4 CPU 1 1...

Page 49: ...a operations Zero overhead loop Precise exceptions Flexible power management High efficiency TriCore Instruction Set 16 32 bit instructions for reduced code size Data types include Boolean array of bits character signed and unsigned integer integer with saturation signed fraction double word integers and IEEE 754 single precision floating point Data formats include Bit 8 bit byte 16 bit half word ...

Page 50: ...pabilities including basic MUL DIV Read move data and accumulate it to previously read data Read two data values and perform arithmetic or logical operation and store result Bit handling capabilities testing setting clearing Flow control instructions conditional unconditional jumps breakpoint Programmable write protection for Code Memory and Parameter Memory Programmable limit of FPI addresses tha...

Page 51: ...MA channels 2 DMA Sub Blocks with 8 DMA channels per DMA Sub Block DMA Sub Blocks with support of parallel channel execution 1 channel per Sub Block both Sub Blocks in parallel Up to 16 selectable request inputs per DMA channel 2 level programmable priority of DMA channels within the DMA Sub Block Software and hardware DMA request Hardware requests by selected on chip peripherals and external inpu...

Page 52: ...s of the 56 bit counter can be read synchronously Flexible service request generation based on compare match with partial STM content Driven by maximum 90 MHz fSYS default after reset fSYS 2 Counting starts automatically after a reset operation STM registers are reset by an application reset if bit ARSTDIS STMDIS is cleared If bit ARSTDIS STMDIS is set the STM registers are not reset 1 STM can be ...

Page 53: ...egisters STM_TIM0 to STM_TIM5 is read Thus STM_CAP holds the upper value of the timer at exactly the same time when the lower part is read The second read operation would then read the content of the STM_CAP to get the complete timer value The STM can also be read in sections from seven registers STM_TIM0 through STM_TIM6 that select increasingly higher order 32 bit ranges of the STM These can be ...

Page 54: ...TM Module 00H STM_CAP STM_TIM6 STM_TIM5 00H 56 bit System Timer Address Decoder Clock Control MCB06185_mod Compare Register 0 Interrupt Control Compare Register 1 PORST STM_TIM4 STM_TIM3 STM_TIM2 STM_TIM1 STM_TIM0 STM_CMP1 STM_CMP0 Enable Disable fSTM STM IR0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 STM IR1 to DMA etc ...

Page 55: ...tion Invalid password during first access or invalid guard bits during second access trigger the Watchdog reset generation Overflow Error Detection An overflow of the counter triggers the Watchdog reset generation Watchdog function can be disabled access protection and ENDINIT monitor function remain enabled Double Reset Detection If a Watchdog induced reset occurs twice a severe system malfunctio...

Page 56: ...overed by the SCU controlled pads Reset request triggers Reset indication Trap request triggers Interrupt request triggers Non SCU module triggers The first three points are covered by the ESR pads and the last two points by the ERU pads 1 3 4 5 Die Temperature Measurement The Die Temperature Sensor DTS generates a measurement result that indicates directly the current temperature The result of th...

Page 57: ...ot ROM interface The Emulation Memory interface The Local Memory Bus LMB slave interface Following memories are controlled by and belong to the PMU0 2 5 Mbyte of Program Flash memory PFlash 64 Kbyte of Data Flash memory DFlash represents 16 Kbyte EEPROM 16 Kbyte of Boot ROM BROM 8 Kbyte Overlay RAM OVRAM The following figure shows the block diagram of the PMU0 Figure 1 3 PMU0 Basic Block Diagram P...

Page 58: ...d which can fully be used for calibration via program memory or OLDA overlay The Emulation Memory interface shown in Figure 1 3 is a 64 bit wide memory interface that controls the CPU accesses to the Emulation Memory in the TC1784 Emulation Device In the TC1784 production device the EMEM interface is always disabled 1 3 6 4 Tuning Protection Tuning protection is required by the user to absolutely ...

Page 59: ...e page including 256 bytes in Program Flash and 128 bytes in Data Flash Concurrent programming and erasing in Data Flash is performed using an automatic erase suspend and resume function A basic block diagram of the Flash Module is shown in the following figure Figure 1 4 Basic Block Diagram of Flash Module All Flash operations are controlled simply by transferring command sequences to the Flash w...

Page 60: ...n sector not accessible to the user Optional read protection for whole Flash with sophisticated read access supervision Combined with whole Flash write protection thus supporting protection against Trojan horse programs Sector specific write protection with support of re programmability or locked forever Comfortable password checking for temporary disable of write or read protection User controlle...

Page 61: ...cture Two sectors of equal size Each sector separately erasable 128 byte pages to be written in one step Operational control per command sequences unlock sequences same as those of Program Flash for protection against unintended operation End of busy as well as error reporting with interrupt and bus error trap Write state machine for automatic program and erase Margin check for detection of proble...

Page 62: ...rt of 8 Kbyte embedded Overlay SRAM OVRAM in PMU Support of up to 512 Kbyte overlay calibration memory EMEM 1 Support of up to 2 MB overlay memory in external memory EBU space 2 Support of Online Data Acquisition into range of up to 32 KB and of its overlay Support of different overlay memory selections for every enabled overlay block Sizes of overlay blocks selectable depending on the overlay mem...

Page 63: ...or communication between external hardware and the system Flexible Peripheral Interconnect Buses FPI Bus for on chip interconnections and its FPI Bus control unit SBCU The System Timer STM with high precision long range timing capabilities The TC1784 includes a power management system a watchdog timer as well as reset logic ...

Page 64: ... Module with three CAN nodes MultiCAN for high efficiency data handling via FIFO buffering and gateway data transfer One Micro Link Serial Bus Interfaces MLI for serial multiprocessor communication One General Purpose Timer Arrays GPTA with a powerful set of digital signal filtering and timer functionality to accomplish autonomous and complex Input Output management One additional Local Timer Cell...

Page 65: ... or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection are provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism is included to distinguish address bytes from data bytes Testing is supported by a loop back option A 13 bit baud...

Page 66: ...le clock Double buffered transmitter receiver Interrupt generation On a transmit buffer empty condition On a transmit last bit of a frame condition On a receive buffer full condition On an error condition frame parity overrun error Implementation features Connections to DMA Controller Connections of receiver input to GPTA LTC for baud rate detection and LIN break signal measuring 1 4 2 High Speed ...

Page 67: ...ows communication with SPI compatible devices Transmission and reception of data is double buffered A shift clock generator provides the SSC with a separate serial clock signal Seven slave select inputs are available for Slave Mode operation Eight programmable slave select outputs chip selects are supported in Master Mode MCB06058_mod Clock Control Address Decoder Interrupt Control fSSC SSC Module...

Page 68: ... to 686 65 bit s 90 MHz module clock Slave Mode 22 5 Mbit s to 686 65 bit s 90 MHz module clock Interrupt generation On a transmitter empty condition On a receiver full condition On an error condition receive phase baud rate transmit error parity error Queued SSC Mode supports control and data handling by the DMA controller Flexible SSC pin configuration Hardware supported parity mode Individually...

Page 69: ...nel clock data and enable signals One out of eight input lines SDI 7 0 is used as serial data input signal for the upstream channel The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided on the ALTINL ALTINH input lines These input lines are typically connected with other on chip peripheral units for example with a timer unit...

Page 70: ...frame Software controlled timer controlled or free running Transmission with or without SEL bit Flexible chip select generation indicates status during serial frame transmission Emergency stop without CPU intervention Low speed asynchronous serial reception on upstream channel Baud rate fMSC divided by 4 8 16 32 64 128 or 256 fMSCmax 90 MHz Standard asynchronous serial frames Programmable upstream...

Page 71: ...hysical layer 1 4 4 1 E Ray Kernel Description Figure 1 4 4 1 shows a global view of the E Ray interface Figure 1 8 General Block Diagram of the E Ray Interface 1 Infineon Infineon Technologies are trademarks of Infineon Technologies AG FlexRay is a trademark of FlexRay Consortium eray_overview_32 vsd Address Decoder IR ERAY Module Kernel Channel A Channel B Port Control External Request Unit Stop...

Page 72: ...trol configure monitor the FlexRay Channel Protocol Controllers Message Handler Global Time Unit System Universal Control Frame and Symbol Processing Network Management Service Request Control and to access the Message RAM via Input Output Buffer The E Ray IP module supports the following features Conformance with FlexRay protocol specification v2 1 Data rates of up to 10 Mbit s on each channel Up...

Page 73: ...o Input Command Request Register IBCR if a data transfer from Input Shadow Buffer to Message RAM to initiated by a previous write access to the IBCR is ongoing Four Input Buffer for building up transmission Frames in parallel Flag indicating which Input Buffer is currently accessible by the host ...

Page 74: ...ge objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer The message objects are organized in double chained linked lists where each CAN node has its own list of message objects A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node and it transmits only messages belonging to this message object list A p...

Page 75: ...jects can be grouped into four priority classes for transmission and reception The selection of the message to be transmitted first can be based on frame identifier IDE bit and RTR bit according to CAN arbitration rules or on its order in the list Advanced message object functionality Message objects can be combined to build FIFO message buffers of arbitrary size limited only by the total number o...

Page 76: ...ents Figure 1 10 shows how two microcontrollers are typically connected together via their MLI interfaces Figure 1 10 Typical Micro Link Interface Connection Features Synchronous serial communication between an MLI transmitter and an MLI receiver Different system clock speeds supported in MLI transmitter and MLI receiver due to full handshake protocol 4 lines between a transmitter and a receiver F...

Page 77: ...1 2011 05 Intro V1 0 Programmable baud rates MLI transmitter baud rate max fMLI 2 45 Mbit s 90 MHz module clock MLI receiver baud rate max fMLI Address range protection scheme to block unauthorized accesses Multiple receiving devices supported ...

Page 78: ...ions are available outside the MLI module kernel as a four line output or input vector with index numbering A B C and D The MLI module internal I O control blocks define which signal of a vector is actually taken into account and also allow polarity inversions to adapt to different physical interconnection means 4 MCB06062_mod Port Control TREADY D A TVALID D A RCLK D A MLI Transmitter MLI Receive...

Page 79: ...tor control applications but can also be used to generate simple and complex signal waveforms required for other industrial applications Figure 1 12 General Block Diagram of the GPTA Modules in the TC1784 Signal Generation Cells MCB05910_TC1767_LTC32 GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GTC31 Global Timer Cell Array GTC03 GTC30 Cl ock Bu...

Page 80: ...can be logically concatenated to provide a common external port pin with a complex signal waveform Local Timer Cells LTC operating in Timer Capture or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external or internal events On chip Trigger and Gat...

Page 81: ...TA clocks FPC1 FPC4 outputs DCM clock LTC prescaler clock Signal Generation Unit Global Timers GT Two independent units Two operating modes Free Running Timer and Reload Timer 24 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency Global Timer Cell GTC 32 units related to the Global Timers Two operating modes Capture Compare and Capture after Compare 24 bit data width fG...

Page 82: ...ommon external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external or internal events The following list summarizes the specific features of the LTCA unit The Local Timer Arrays LTCA2 provides a set of hardware modules required for high speed digital signal processing Signal Generation Unit Local Timer Cell LTC 32 indep...

Page 83: ...ersions data handling and storage done by a digital part Figure 1 13 ADC Module with two ADC Kernels Features of the analog part of each ADC kernel Input voltage range from 0V to analog supply voltage Analog supply voltage range from 3 3 V to 5 V single supply 5V nominal supply voltage performance degradation accepted for lower voltages Input multiplexer width of 16 possible analog input channels ...

Page 84: ...n external analog multiplexer respecting the additional set up time Programmable sampling times for different channels Possibility to cancel running conversions on demand with automatic restart Flexible interrupt generation possibility of DMA support Limit checking to reduce interrupt load Programmable data reduction filter by adding conversion results Support of conversion data FIFO Support of su...

Page 85: ... of 1 2 4 or 8 for each channel Free running Channel Timers or triggered conversion modes Trigger and gating control for external signals Built in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable programmable digital anti aliasing and data reduction filter block with four independent filter units Figure 1 14 Block Diagram of ...

Page 86: ...ply and reference voltage lines VDDMF VSSMF FADC Analog Channel Amplifier Power Supply 3 3 V VDDIF VSSMF FADC Analog Input Stage Power Supply 3 3 5 V the VDDIF supply does not appear as supply pin because it is internally connected to the VDDM supply of the ADC that is sharing the FADC input pins VDDAF VSSAF FADC Analog Part Power Supply 1 2 V to be fed in externally VFAREF VFAGND FADC Reference V...

Page 87: ...tructure in TC1784 MCA06432_m4n FAIN0N FAIN0P Analog Input Stages Rp Rn Channel Amplifier Stages gain A D A D Control conversion control Converter Stage CHNR VDDAF VSSAF FAIN2N FAIN2P Rp Rn FAIN1N FAIN1P Rp Rn VDDIF FAIN3N FAIN3P Rp Rn VSSMF VSSMF VDDMF VSSMF VDDMF VSSMF VDDMF VSSMF VDDMF ...

Page 88: ...ic of the TriCore or part of a central peripheral known as CERBERUS 1 5 1 On Chip Debug Support The classic software debug approach start stop single stepping is supported by several features labelled OCDS Level 1 Run stop and single step execution independently for TriCore and PCP Means to request all kinds of reset without usage of sideband pins Halt after Reset for repeatable debug sessions Dif...

Page 89: ...acing of the system s behavior a pin compatible Emulation Device will be available 1 1 5 3 Calibration Support Two main use cases are catered for by resources in addition the OCDS Level 1 infrastructure Overlay of non volatile on chip memory and non intrusive signaling 8 KB SRAM for Overlay Can be split into up to 16 blocks which can overlay independent regions of on chip Data Flash Changing the c...

Page 90: ...he TC1784 for all interfaces Infineon standard DAS Device Access Server implementation for seamless transparent tool access over any supported interface Lock mechanism to prevent unauthorized tool access to critical application code 1 5 5 Self Test Support Some manufacturing tests can be invoked by the application e g after power on if needed Hardware accelerated checksum calculation e g for Flash...

Page 91: ...subsystem Figure 1 TC1784 Processor Subsystem Block Diagram Floating Point Unit FPU TriCoreTM CPU DMI 124 KB LDRAM 4 KB DCACHE Configurable LDRAM Local Data RAM SPRAM Scratch Pad RAM ICACHE Instruction Cache OVRAM Overlay RAM PMI 24 KB SPRAM 16 KB ICACHE Configurable CPU Slave Interface CPS LMB Local Memory Bus System Peripheral Bus SPB MCB06068 PFlash Program Memory Flash DFlash Data Memory Flash...

Page 92: ...tic comparison address comparison logical MAC shift coprocessor bit logical branch bit field load store packed data system General Purpose Register Set GPRS Sixteen 32 bit data registers Sixteen 32 bit address registers Three 32 bit status and program counter registers PSW PC PCXI Core Debug support OCDS Level 1 supported in conjunction with the CPS block Level 3 supported in conjunction with the ...

Page 93: ...PS and Floating Point Unit FPU Figure 2 CPU Block Diagram Execution Unit MCB06069 To Program Memory Interface PMI Integer Pipeline General Purpose Register File GPR Instruction Fetch Unit Core Register Access Address Registers Data Registers To Data Memory Interface DMI Coprocessor Interface Floating Point Unit FPU CPU Slave Interface CPS Interrupts System Control Test Debug Emulation Loop Pipelin...

Page 94: ... fetched ahead of the current program counter The Issue Unit directs the instruction to the appropriate pipeline The Instruction Protection Unit checks the validity of accesses to the PMI and also checks for instruction breakpoint conditions The Program Counter Unit PC is responsible for updating the program counters Figure 3 Instruction Fetch Unit MCA06070 Issue Unit To Loop Pipeline Injection PC...

Page 95: ...perations such as load instructions The Loop Pipeline has two stages Decode and Write back All three pipelines operate in parallel permitting up to three instructions to be executed in one clock cycle Figure 4 Execution Unit MCA06071 Loop Exec To Register File EA Address ALU ALU Bit Processor MAC Load Store Decode IP Decode Integer Pipeline Loop Pipeline Load Store Pipeline Decode Execute Loop Dec...

Page 96: ...ata flow for instructions issued to the Load Store Pipeline is steered through the Address Register File The data flow for instructions issued to from the Integer Pipeline and for data load store instructions issued to the Load Store Pipeline is steered through the Data Register File Figure 5 General Purpose Register File General Purpose Register File MCA06072 Data Register File Address Register F...

Page 97: ... LDRAM When they are not full the shadow registers allow a complete Upper Context to be saved in as few as two clock cycles When the shadow registers are full the upper context save takes up to five cycles On average an upper context save takes 2 7 cycles CSA Placement in Cached External Memory In this case the timing is also dependent on the state of the Data Cache The following values assume bes...

Page 98: ...Manual 2 8 V1 1 2011 05 CPU V3 03 The CPU must not perform Load Store instructions to the mapped address of the PC in Segment 15 A MEM trap will be generated in such a case Bit 0 of the PC register is read only and hard wired to 0 ...

Page 99: ...uctions OPD Invalid Operand TIN 3 The CPU does not raise OPD traps DSE Data Access Synchronous Error TIN 2 The Data Access Synchronous Bus Error DSE trap is generated by the DMI module when a load access from the CPU encounters certain error conditions such as an LMB Bus error or an out of range access to LDRAM When a DSE trap is generated the exact cause of the error can be determined by reading ...

Page 100: ...may be interrogated to determine the source of any error more precisely 2 3 5 Memory Integrity Error Handling The TriCore 1 3 1 contains integrated support for the detection and handling of memory integrity errors The handling of memory integrity errors for the various memory types in TriCore 1 3 1 is as follows 2 3 5 1 Program Side Memories The program side memories of the TriCore 1 3 1 core supp...

Page 101: ...he ICACHE Since the instruction cache shares the same physical memory as the Scratchpad RAM it is similarly configured for memory integrity error protection six ECC bits are stored per half word ECC protection of the instruction cache is enabled by setting MIECON PMIEE to one When MIECON PMIEE is zero all uncorrectable memory integrity errors are ignored For instruction fetch requests from the Tri...

Page 102: ...Cache is converted to a halfword Read Modify Write sequence The transformation of such byte accesses to atomic sequences is performed within the DMI rather than the CPU core itself In normal operation isolated byte write transactions to the data memories result in no additional stall cycles Local Data RAM LDRAM The Local Data RAM of TriCore 1 3 1 is protected from memory integrity errors on a per ...

Page 103: ... reset if correction of the data is not possible For write operations of half word size or greater the check bits are pre calculated and written to the memory in parallel with the data bits For byte write operations the memory transaction is transformed into a half word read modify write sequence inside the DMI module As such byte write operations may result in the detection of uncorrectable memor...

Page 104: ...ent to the TriCore CPU the CCDIE_R counter is incremented to allow counting of such error corrections if required In the case where one cache way flags a cache hit and the other way detects an uncorrectable error the error condition is masked and has no effect on the memory integrity error handling mechanisms If a cache miss occurs with an uncorrectable error detected on the associated data tag wa...

Page 105: ...ng the COMPAT PIE DIE bit s to one When the COMPAT PIE DIE bit is set the memory integrity error handling is modified Memory integrity errors are never flagged directly to the TriCore 1 3 1 core such that PIE DIE traps are not generated LMB bus errors are not generated for SPRAM LDRAM accesses The CCPIE_R CCDIE_R counters are not updated When COMPAT PIE DIE is set along with the corresponding MIEC...

Page 106: ...d Data Registers see Page 2 24 CPU Memory Protection Registers CSFRs Memory protection control and mode selection see Page 2 27 FPU Registers CSFRs Support for the standard floating point instructions see Page 2 33 Memory Integrity Registers CSFRs Integrity and Protection Core Special Function Registers see Page 2 35 CPU Slave Interface CPS Registers Software break control and software service req...

Page 107: ...H U SV 32 SV 32 Class 3 Reset 0000 0B80H PC Program Counter Register FE08H U SV 32 SV 32 Class 3 Reset XXXX XXXXH SYSCON System Configuration Register FE14H U SV 32 SV 32 Class 3 Reset 0000 0000H CPU_ID CPU Identification Register FE18H U SV 32 U SV 32 NC Class 3 Reset 000A C0XXH BIV Interrupt Vector Table Pointer Register FE20H U SV 32 SV E 32 Class 3 Reset 0000 0000H BTV Trap Vector Table Pointe...

Page 108: ...ass 3 Reset 0000 0000H FCX Free Context List Head Pointer Register FE38H U SV 32 SV 32 Class 3 Reset 0000 0000H LCX Free Context List Limit Pointer Register FE3CH U SV 32 SV 32 Class 3 Reset 0000 0000H COMPAT Compatibility Control Register 9400H U SV 32 SV E 32 Class 3 Reset FFFF FFFFH Table 2 Core Special Function Registers cont d Short Name Description Offset Address Access Mode Reset Value Read...

Page 109: ... in the TriCore Architecture Manual PSW Program Status Word Register F7E1 FE04H Reset Value 0000 0B80H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C or FS V or FI SV or FV AV or FZ SAV or FU FX RM 0 rwh rwh rwh rwh rwh rwh rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PRS IO IS GW CDE CDC r rwh rwh rwh rwh rwh rwh Field Bits Type Description RM 25 24 rw FPU Rounding Mode Selection FX 26 rwh FPU...

Page 110: ...5 24 23 22 21 20 19 18 17 16 0 C ONE CYC CARBCYC PIPN r rw rw rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IE CCPN r rwh rwh Field Bits Type Description CARBCYC 25 24 rw Number of Arbitration Cycles CARBCYC controls the number of arbitration cycles used to determine the request with the highest priority 00B 4 arbitration cycles default 01B 3 arbitration cycles 10B 2 arbitration cycles 11B 1 arbitrat...

Page 111: ... define the implementation specific bits bit fields The shaded areas are defined in the TriCore Architecture Manual MMU_CON MMU Configuration Register F7E1 8000H Reset Value 0000 8000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NO MMU 0 TSZ SZB SZA V r r r rw rw rw Field Bits Type Description NO MMU 15 r MMU Exists 0B MMU is available 1B MMU is not av...

Page 112: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_32B REV xx rh rh Field Bits Type Description MOD_REV 7 0 rh Revision Number 01H For version numbering The value of the revision starts with 01H first revision up to FFH FFH Last revision MOD_32B 15 8 rh 32 Bit Module Enable C0H A value of C0H in this field indicates a 32 bit module with a 32 bit module ID register MOD 31 16 rh Module Identification Number 0AH ...

Page 113: ...19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RM BP DIE PIE r rw rw rw rw Field Bits Type Description PIE 0 rw Program Integrity Error Compatibility 0B Errors handled by CPU 1B Errors flagged off core TriCore 1 3 backwards compatibility DIE 1 rw Data Integrity Error Compatibility 0B Errors handled by CPU 1B Errors flagged off core TriCore 1 3 backwards compatibility BP 2 rw Branch Predic...

Page 114: ...s 3 Reset XXXX XXXXH D2 Data Register 2 FF08H U SV 32 SV 32 Class 3 Reset XXXX XXXXH D3 Data Register 3 FF0CH U SV 32 SV 32 Class 3 Reset XXXX XXXXH D4 Data Register 4 FF10H U SV 32 SV 32 Class 3 Reset XXXX XXXXH MCA06075 Address General Purpose Registers AGPR Data General Purpose Registers DGPR E14 E12 E10 E8 E6 E4 E2 E0 64 bit Extended Data Registers D15 implicit data D14 D13 D12 D11 D10 D9 D8 D...

Page 115: ...ster 12 FF30H U SV 32 SV 32 Class 3 Reset XXXX XXXXH D13 Data Register 13 FF34H U SV 32 SV 32 Class 3 Reset XXXX XXXXH D14 Data Register 14 FF38H U SV 32 SV 32 Class 3 Reset XXXX XXXXH D15 Data Register 15 FF3CH U SV 32 SV 32 Class 3 Reset XXXX XXXXH A0 Address Register 0 Global Address Register FF80H U SV 32 SV 32 Class 3 Reset XXXX XXXXH A1 Address Register 1 Global Address Register FF84H U SV 3...

Page 116: ... Register FFA4H U SV 32 SV 32 Class 3 Reset XXXX XXXXH A10 Address Register 10 Stack Pointer FFA8H U SV 32 SV 32 Class 3 Reset XXXX XXXXH A11 Address Register 11 Return Address FFACH U SV 32 SV 32 Class 3 Reset XXXX XXXXH A12 Address Register 12 FFB0H U SV 32 SV 32 Class 3 Reset XXXX XXXXH A13 Address Register 13 FFB4H U SV 32 SV 32 Class 3 Reset XXXX XXXXH A14 Address Register 14 FFB8H U SV 32 SV...

Page 117: ...ectionSet 1 DPM1 31 24 DPR1_3U DPR1_3L Range3 DPM1 23 16 DPR1_2U DPR1_2L Range2 DPM1 15 8 DPR1_1U DPR1_1L Range1 DPM1 7 0 DPR1_0U DPR1_0L Range0 CodeMemoryProtectionSet 1 CPM1 15 8 CPR1_1U CPR1_1L Range1 CPM1 7 0 CPR1_0U CPR1_0L Range0 DataandCodeMemory ProtectionSets0 areselectedwith PSW PRS 00 B DataandCodeMemory ProtectionSets1 areselectedwith PSW PRS 01B DataMemoryProtectionSet 2 DPM2 31 24 DP...

Page 118: ... 0000 0000H DPR0_2L Data Segment Protection Register Set 0 Range 2 Lower Boundary C010H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR0_2U Data Segment Protection Register Set 0 Range 2 Upper Boundary C014H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR0_3L Data Segment Protection Register Set 0 Range 3 Lower Boundary C018H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR0_3U Data Segment Protection Register Se...

Page 119: ... 3 Reset 0000 0000H DPR2_0L Data Segment Protection Register Set 2 Range 0 Lower Boundary C800H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR2_0U Data Segment Protection Register Set 2 Range 0 Upper Boundary C804H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR2_1L Data Segment Protection Register Set 2 Range 1 Lower Boundary C808H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR2_1U Data Segment Protection Reg...

Page 120: ... 3 Reset 0000 0000H DPR3_1U Data Segment Protection Register Set 3 Range 1 Upper Boundary CC0CH U SV 32 SV 32 Class 3 Reset 0000 0000H DPR3_2L Data Segment Protection Register Set 3 Range 2 Lower Boundary CC10H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR3_2U Data Segment Protection Register Set 3 Range 2 Upper Boundary CC14H U SV 32 SV 32 Class 3 Reset 0000 0000H DPR3_3L Data Segment Protection Reg...

Page 121: ... 3 Reset 0000 0000H CPR1_1L Code Segment Protection Register Set 1 Range 1 Lower Boundary D408H U SV 32 SV 32 Class 3 Reset 0000 0000H CPR1_1U Code Segment Protection Register Set 1 Range 1 Upper Boundary D40CH U SV 32 SV 32 Class 3 Reset 0000 0000H CPR2_0L Code Segment Protection Register Set 2 Range 0 Lower Boundary D800H U SV 32 SV 32 Class 3 Reset 0000 0000H CPR2_0U Code Segment Protection Reg...

Page 122: ...et 0 E000H U SV 32 SV 32 Class 3 Reset 0000 0000H DPM1 Data Protection Mode Register Set 1 E080H U SV 32 SV 32 Class 3 Reset 0000 0000H DPM2 Data Protection Mode Register Set 2 E100H U SV 32 SV 32 Class 3 Reset 0000 0000H DPM3 Data Protection Mode Register Set 3 E180H U SV 32 SV 32 Class 3 Reset 0000 0000H CPM0 Code Protection Mode Register Set 0 E200H U SV 32 SV 32 Class 3 Reset 0000 0000H CPM1 C...

Page 123: ...0000H FPU_TRAP _PC Trapping Instruction Program Counter Register A004H U SV 32 SV 32 Class 3 Reset 0000 0000H FPU_TRAP _OPC Trapping Instruction Opcode Register A008H U SV 32 SV 32 Class 3 Reset 0000 0000H FPU_TRAP _SRC1 Trapping Instruction Operand Register A010H U SV 32 SV 32 Class 3 Reset 0000 0000H FPU_TRAP _SRC2 Trapping Instruction Operand Register A014H U SV 32 SV 32 Class 3 Reset 0000 0000...

Page 124: ...054 rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_32B REV xx rh rh Field Bits Type Description MOD_REV 7 0 rh Revision Number 01H For version numbering The value of the revision starts with 01H first revision up to FFH FFH Last revision MOD_32B 15 8 rh 32 Bit Module Enable C0H A value of C0H in this field indicates a 32 bit module with a 32 bit module ID register MOD 31 16 rh Module Identification ...

Page 125: ...er 2 9048H U SV 32 SV E 32 Class 3 Reset 0000 0000H CCPIER Count of Corrected Program Integrity Errors Register 9218H U SV 32 SV 32 Class 3 Reset 0000 0000H CCDIER Count of Corrected Data Integrity Errors Register 9028H U SV 32 SV 32 Class 3 Reset 0000 0000H PIEAR Program Integrity Error Address Register 9210H U SV 32 SV 32 Class 3 Reset 0000 0000H PIETR Program Integrity Error Trap Register 9214H...

Page 126: ... Integrity Error Trap Register 9024H U SV 32 SV 32 Class 3 Reset 0000 0000H SMACON SIST Mode Access Control Register 900CH U SV 32 SV E 32 Class 3 Reset 0000 0000H Table 2 1 Memory cont d Integrity Registers Short Name Description Offset Address Access Mode Reset Read Write ...

Page 127: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PMIE E 0 DMI EE r rw r rw Field Bits Type Description DMIEE 0 rwh Data Memory Integrity Error Enable Enables handling of uncorrectable integrity errors for the Data Memories 0B Uncorrectable integrity error handling disabled all memory accesses interpreted as error free 1B Uncorrectable integrity error handling enabled PMIEE 8 rwh Program Memory Integrity Error En...

Page 128: ...cesses interpreted as error free 1B Uncorrectable integrity error handling enabled PTIEE 18 rw Program Tag Integrity Error Enable Enables handling of uncorrectable integrity errors for the Program Tag 0B Uncorrectable integrity error handling disabled all memory accesses interpreted as error free 1B Uncorrectable integrity error handling enabled 0 7 1 15 9 17 31 19 r Reserved Read as 0 should be w...

Page 129: ...n all zeroes MIECON2 Memory Integrity Error Control Register 2 F7E1 9048H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PTS ECE 0 DTS ECE r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PMS ECE 0 DMS ECE r rw r rw Field Bits Type Description DMSECE 0 rwh Data Memory Single Error Correction Enable Enables single bit error correction for the Data Memories PMSECE 8 rwh Pr...

Page 130: ... bits interact to perform the following general functions Table 6 Functions xxSECE xxIEE Description 0 0 No Memory Integrity Handling All single and double bit memory integrity errors ignored 0 1 Error Detection Mode Single and double bit errors treated as uncorrectable errors 1 0 SEC Only Mode Single bit errors corrected by ECC double bit errors ignored 1 1 SECDED Mode Single bit errors corrected...

Page 131: ...program memory integrity error condition detected either during a bus access or a CPU instruction pre fetch Since instruction pre fetches are speculative the PIETR and PIEAR registers may be updated without a corresponding PIE trap The Program Integrity Error Trap Register PIETR contains flags to support software in localising the source of the last detected uncorrectable program memory integrity ...

Page 132: ...etected Read Operation 0B No program integrity error condition occurred 1B Program integrity error condition detected PIETR and PIEAR contents valid further PIETR and PIEAR updates disabled Write Operation 0B Clear IED bit re enable PIETR and PIEAR updates 1B No effect IE_T 1 rh Integrity Error Tag Memory IE_C 2 rh Integrity Error Cache Memory IE_S 3 rh Integrity Error Scratchpad Memory IE_B 4 rh ...

Page 133: ...e program memory integrity error This register is only updated if PIETR IED is zero PIEAR Program Integrity Error Address Register F7E1 9210H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TA rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TA rh Field Bits Type Description TA 31 0 rh Transaction Address Physical address being accessed by operation that encountered program integrit...

Page 134: ...grity error Where an uncorrectable data memory integrity error condition is detected during a CPU Load Store access the IE_S IE_C IE_T and TRTYP bits are updated to denote in which memory structure the error was detected and the nature of the DIE trap whilst BUS_ID and IE_B are cleared Where the error is detected during a bus access IE_B is set and BUS_ID updated to denote the master tag ID of the...

Page 135: ...a integrity error condition occurred 1B Data integrity error condition detected PIETR and DIEAR contents valid further DIETR and DIEAR updates disabled Write Operation 0B Clear IED bit re enable DIETR and DIEAR update 1B No effect IE_T 1 rh Integrity Error Tag Memory IE_C 2 rh Integrity Error Cache Memory IE_S 3 rh Integrity Error Scratchpad Memory IE_B 4 rh Integrity Error Bus Access BUS_ID 8 5 r...

Page 136: ...TC1784 CPU Subsystem User s Manual 2 46 V1 1 2011 05 CPU V3 03 0 31 10 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 137: ...able data memory integrity error This register is only updated if DIETR IED is zero DIEAR Data Integrity Error Address Register F7E1 9020H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TA rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TA rh Field Bits Type Description TA 31 0 rh Transaction Address Physical address being accessed by operation that encountered data integrity erro...

Page 138: ...s space and the enabling of other SIST related features is controlled by the setting of bits within the SIST Mode Access Control Register SMACON The fields of the SMACON register are implementation specific The embedded memory arrays are mapped into the program and data scratch areas Segments CH and DH of the address map by setting bits in the SMACON register Program side embedded memories are map...

Page 139: ...detection correction enabled PS 5 4 rw Program Scratch Memory SIST Mode Access Control 00B Normal Operation No Mapping 01B Data Array Mapping no error detection correction 10B Check Array Mapping no error detection correction 11B Data Array Mapping error detection correction enabled DC 9 8 rw Data Cache Memory SIST Mode Access Control 00B Normal Operation No Mapping 01B 1xB Data cache memory confi...

Page 140: ...ping error detection correction enabled IODT 24 rw In Order Data Transactions 0B Normal operation Non dependent loads bypass stores 1B In order operation Loads always flush preceding stores processor store buffer disabled 0 7 6 23 14 31 25 r Reserved Read as 0 should be written with 0 1 When the Flash Read Protection mechanism is active the value of SMACON PC is overridden and treated as 00B norma...

Page 141: ...t affect the check bits Error correction detection for the memory is disabled Performance optimisations are disabled such that memory accesses are guaranteed to be performed to the actual memory Check Array Mapping no error detection correction The check bit array only of the memory is made visible in the address map Writes to the memory will not affect the data bits Error correction detection for...

Page 142: ...rite CPS_ID CPS Module Identification Register FF08H U SV 32 U SV 32 NC Class 3 Reset 0015 C0XXH CPU_SBSRC CPU Software Breakpoint Service Request Control Register FFBCH U SV 32 SV 32 Class 3 Reset 0000 0000H CPU_SRC3 CPU Service Request Control 3 Register FFF0H U SV 32 SV 32 Class 3 Reset 0000 0000H CPU_SRC2 CPU Service Request Control 2 Register FFF4H U SV 32 SV 32 Class 3 Reset 0000 0000H CPU_S...

Page 143: ...lementation specific bits bit fields The shaded areas are defined in the TriCore Architecture Manual CPU_SRCn n 0 3 CPU Service Request Control Register n F7E0 FFFCH n 4 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description TOS 10 rw Type of Service Control 0B...

Page 144: ...rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_32B REV xx rh rh Field Bits Type Description MOD_REV 7 0 rh Revision Number 01H For version numbering The value of the revision starts with 01H first revision up to FFH FFH Last revision MOD_32B 15 8 rh 32 Bit Module Enable C0H A value of C0H in this field indicates a 32 bit module with a 32 bit module ID register MOD 31 16 rh Module Identification Numb...

Page 145: ...s are defined in the TriCore Architecture Manual CPU_SBSRC CPU Software Breakpoint Service Request Control Register F7E0 FFBCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description TOS 10 rw Type of Service Control 0B Service Provider CPU 1B Reserved 0 11 r Re...

Page 146: ...eset 0000 0000H CCNT CPU Clock Count Register FC04H U SV 32 SV 32 Class 1 Reset 0000 0000H ICNT Instruction Count Register FC08H U SV 32 SV 32 Class 1 Reset 0000 0000H M1CNT Multi Count Register 1 FC0CH U SV 32 SV 32 Class 1 Reset 0000 0000H M2CNT Multi Count Register 2 FC10H U SV 32 SV 32 Class 1 Reset 0000 0000H M3CNT Multi Count Register 3 FC14H U SV 32 SV 32 Class 1 Reset 0000 0000H DBGSR Debu...

Page 147: ...TR1EVT Trigger Event 1 Register FD24H U SV 32 SV 32 Class 1 Reset 0000 0000H DMS Debug Monitor Start Address Register FD40H U SV 32 U SV 32 NC Class 1 Reset DE00 0000H DCX Debug Context Save Area Pointer FD44H U SV 32 SV 32 Class 1 Reset DE80 0000H DBGTCR Debug Trap Control Register FD48H U SV 32 SV 32 Class 1 Reset 0000 0000H CPU_SBSR C CPU Software Breakpoint Service Request Control Register FFB...

Page 148: ... registers not defined in this chapter Table 9 Implementation Specific Reset Values Register Address Reset Value PCXI F7E1 FE00H 0000 0000H PCX F7E1 FE00H 0000 0000H CPU_ID F7E1 FE18H 000A C0XXH FCX F7E1 FE38H 0000 0000H LCX F7E1 FE3CH 0000 0000H COMPAT F7E1 9400H FFFF FFFFH ISP F7E1 FE28H 0000 0100H BIV F7E1 FE20H 0000 0000H BTV F7E1 FE24H A000 0100H FPU_ID F7E1 A020H 0054 C003H ...

Page 149: ... different subsequent instruction Result Latency The number of clock cycles from the cycle when the instruction is issued to the cycle when the result value is available to be used as an operand to a subsequent instruction or written into a GPR Result latency is not meaningful for instructions that do not write a value into a GPR Address Latency The number of clocks cycles from the cycle when the ...

Page 150: ...struction Result Latency Repeat Rate Integer Pipeline Arithmetic Instructions ABS 1 1 MAX H 1 1 ABS B 1 1 MAX HU 1 1 ABS H 1 1 MAX U 1 1 ABSDIF 1 1 MIN 1 1 ABSDIF B 1 1 MIN B 1 1 ABSDIF H 1 1 MIN BU 1 1 ABSDIFS 1 1 MIN H 1 1 ABSDIFS H 1 1 MIN HU 1 1 ABSS 1 1 MIN U 1 1 ABSS H 1 1 RSUB 1 1 ADD 1 1 RSUBS 1 1 ADD B 1 1 RSUBS U 1 1 ADD H 1 1 SAT B 1 1 ADDC 1 1 SAT BU 1 1 ADDI 1 1 SAT H 1 1 ADDIH 1 1 SA...

Page 151: ... LT W 1 1 GE 1 1 LT WU 1 1 GE U 1 1 NE 1 1 LT 1 1 Count Instructions CLO 1 1 CLS H 1 1 CLO H 1 1 CLZ 1 1 CLS 1 1 CLZ H 1 1 Extract Instructions DEXTR 1 1 INS T 1 1 EXTR 1 1 INSN T 1 1 EXTR U 1 1 INSERT 1 1 IMASK 1 1 Logical Instructions AND 1 1 OR EQ 1 1 AND AND T 1 1 OR GE 1 1 AND ANDN T 1 1 OR GE U 1 1 AND EQ 1 1 OR LT 1 1 AND GE 1 1 OR LT U 1 1 Table 10 Simple Arithmetic Instruction Timing cont...

Page 152: ...R GE U 1 1 NOR T 1 1 XOR LT 1 1 OR 1 1 XOR LT U 1 1 OR AND T 1 1 XOR NE 1 1 OR ANDN T 1 1 XOR T 1 1 Move Instructions CMOV 1 1 MOV U 1 1 CMOVN 1 1 MOVH 1 1 MOV 1 1 Shift Instructions SH 1 1 SH NE 1 1 SH AND T 1 1 SH NOR T 1 1 SH ANDN T 1 1 SH OR T 1 1 SH EQ 1 1 SH ORN T 1 1 SH GE 1 1 SH XNOR T 1 1 SH GE U 1 1 SH XOR T 1 1 SH H 1 1 SHA 1 1 SH LT 1 1 SHA H 1 1 SH LT U 1 1 SHAS 1 1 Table 10 Simple Ar...

Page 153: ... 4 4 BSPLIT 1 1 DVSTEP U 4 4 DVADJ 1 1 IXMAX 1 1 DVINIT 1 1 IXMAX U 1 1 DVINIT U 1 1 IXMIN 1 1 DVINIT B 1 1 IXMIN U 1 1 DVINIT H 1 1 PACK 1 1 DVINIT BU 1 1 PARITY 1 1 DVINIT HU 1 1 UNPACK 1 1 Table 10 Simple Arithmetic Instruction Timing cont d Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate ...

Page 154: ... 2 Multiply Instruction Timings Each instruction is single issued Table 11 Multiply Instruction Timing Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate MUL 2 1 MUL Q 2 1 MUL U 2 1 MULM H 2 1 MULS 2 1 MULR H 2 1 MULS U 2 1 MULR Q 2 1 MUL H 2 1 ...

Page 155: ...2 1 MADD U 2 1 MSUB U 2 1 MADDS 2 1 MSUBS 2 1 MADDS U 2 1 MSUBS U 2 1 MADD H 2 1 MSUB H 2 1 MADD Q 2 1 MSUB Q 2 1 MADDM H 2 1 MSUBM H 2 1 MADDMS H 2 1 MSUBMS H 2 1 MADDR H 2 1 MSUBR H 2 1 MADDR Q 2 1 MSUBR Q 2 1 MADDRS H 2 1 MSUBRS H 2 1 MADDRS Q 2 1 MSUBRS Q 2 1 MADDS H 2 1 MSUBS H 2 1 MADDS Q 2 1 MSUBS Q 2 1 MADDSU H 2 1 MSUBAD H 2 1 MADDSUM H 2 1 MSUBADM H 2 1 MADDSUMS H 2 1 MSUBADMS H 2 1 MADD...

Page 156: ...operations no pending stores For All Control Flow Instructions Table 13 Integer Pipeline Control Flow Instruction Timing Instruction Flow Latency Repeat Rate Instruction Flow Latency Repeat Rate Branch Instructions JEQ 1 2 3 1 2 3 JLTZ 1 2 3 1 2 3 JGE 1 2 3 1 2 3 JNE 1 2 3 1 2 3 JGE U 1 2 3 1 2 3 JNED 1 2 3 1 2 3 JGEZ 1 2 3 1 2 3 JNEI 1 2 3 1 2 3 JGTZ 1 2 3 1 2 3 JNZ 1 2 3 1 2 3 JLEZ 1 2 3 1 2 3 J...

Page 157: ...DSC A 1 1 NE A 1 1 ADDSC AT 1 1 NEZ A 1 1 EQ A 1 1 SUB A 1 1 EQZ A 1 1 NOP 1 1 Trap and Interrupt Instructions DEBUG 1 TRAPSV1 1 Execution cycles when no TRAP is taken The execution timing in the case of raising these TRAPs is the same as other TRAPs such as SYSCALL 1 DISABLE 1 TRAPV1 1 ENABLE 1 RSTV 1 Move Instructions MFCR 1 1 MOV A 1 1 MTCR 1 MOV AA 1 1 MOVH A 1 1 MOV D 1 1 Sync Instructions DS...

Page 158: ... 2 3 CSA Instructions CALL1 1 The range is 2 5 for LDRAM and 3 9 for Cached External Memory The average latency is 2 7 cycles for LDRAM and 5 cycles for Cached External Memory 2 9 2 9 SYSCALL1 2 9 2 9 CALLA1 2 9 2 9 SVLCX4 4 16 4 16 CALLI1 2 9 2 9 RSLCX2 2 The range is 4 for LDRAM and 8 for Cached External Memory 4 8 4 8 RET3 3 The range is 2 5 for LDRAM and 2 9 for Cached External Memory 2 9 2 9 ...

Page 159: ...ingle issued The memory references is naturally aligned The memory accessed takes a single cycle to return a data item Timing is best case no cache misses no pending stores Flow Latency Repeat Rate Correctly predicted not taken 1 1 Correctly predicted taken 2 2 Wrongly predicted 3 2 Table 16 Load Instruction Timing Instruction Address Latency Result Latency Repeat Rate Instruction Address Latency ...

Page 160: ...ed takes a single cycle to accept a data item Timing is best case no cache misses no pending stores Table 17 Cache and Store Instruction Timing Instruction Address Latency Repeat Rate Instruction Address Latency Repeat Rate Cache Instructions CACHEA I 1 1 CACHEA WI1 1 Repeat rate assumes that no memory writeback operation occurs Otherwise the repeat rate will depend upon the time for the castout b...

Page 161: ...mplemented Each instruction is single issued Table 18 Floating Point Instruction Timing Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate Floating Point Instructions ADDF 2 2 ITOF 2 2 CMP F 1 1 MADD F 3 3 DIV F 15 15 MSUB F 3 3 FTOI 2 2 MUL F 2 2 FTOIZ 2 2 Q31TOF 2 2 FTOQ31 2 2 QSEED F 1 1 FTOQ31Z 2 2 SUB F 2 2 FTOU 2 2 UPDFL 1 FTOUZ 2 2 UTOF 2 2 ...

Page 162: ...0 Kbyte total Program Memory PMEM with software configurable split between SPRAM and ICACHE The following configurations are supported SPRAM ICACHE 24 16 32 8 36 4 38 2 40 0 MCC06078 To From Local Memory Bus 128 Data Switch Data Alignment Interface Control PMI Control Registers LMB Interface Slave Master CPU Interface To From CPU Program Memory Interface PMI PMEM Tag RAM ICACHE SPRAM PMEM Program ...

Page 163: ...ess Priorities The TC1784 contains a common local memory bus shared between the Program Memory Interface PMI Data Memory Interface DMI DMA controller and LMB FPI Interface FPI bus masters In such systems the DMI is the default bus master whilst LMB arbitration priorities are as follows 1 DMA High 2 LFI 3 DMA Medium 4 DMI 5 PMI 6 DMA Low 2 14 3 Scratchpad RAM The TC1784 contains up to 40 Kbyte of s...

Page 164: ...associated instruction are found in the cache Cache Hit the instruction is passed to the CPU Fetch Unit without incurring any wait states If the address is not found in the cache Cache Miss the PMI cache controller issues a cache refill sequence and wait states are incurred whilst the cache line is refilled The CPU fetch interface will generate unaligned accesses 16 bit aligned which will normally...

Page 165: ...ched in the ICACHE are not detected Software must provide the cache coherency in such a case The PMI supports this via the cache invalidation function The ICACHE contents may be globally invalidated by writing a 1 to PMI_CON1 PCINV The ICACHE invalidation is performed over multiple cycles by a hardware state machine which cycles through the ICACHE entries marking each as invalid The status of the ...

Page 166: ...dress Access Mode Reset Read Write PMI_ID PMI Identification Register FD08H U SV 32 SV 32 Class 3 Reset 000B C0XXH PMI_CON0 PMI Control Register 0 FD10H U SV 32 SV 32 Class 3 Reset 0000 0002H PMI_CON1 PMI Control Register 1 FD14H U SV 32 SV 32 Class 3 Reset 0000 0000H PMI_CON2 PMI Control Register 2 FD18H U SV 32 SV E 32 Class 3 Reset 0280 0284H PMI_STR PMI Synchronous Trap Register FD20H U SV 32 ...

Page 167: ...0 PMI Control Register 0 F87F FD10H Reset Value 0000 0002H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PC BYP 0 r rw r Field Bits Type Description PCBYP 1 rw Instruction Cache Bypass 0B Cache enabled 1B Cache bypassed disabled 0 31 2 0 r Reserved Read as 0 should be written with 0 ...

Page 168: ...Instruction Cache Invalidate Write Operation 0B No effect Normal instruction cache operation 1B Initiate invalidation of entire instruction cache Read Operation 0B Normal operation Instruction cache available 1B Instruction cache invalidation in progress Instruction cache unavailable PBINV 1 rw Program Buffer Invalidate Write Operation 0B No effect Normal program line buffer operation 1B Invalidat...

Page 169: ...tection active are ignored Setting Flash read protection inactive then active again does not allow further Flash read protection enabled PMI_CON2 writes only a reset will re enable the single Flash read protection enabled write PMI_CON2 PMI Control Register 2 F87F FD18H Reset Value 0280 0284H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMEM_SZ_CFG PC_SZ_CFG rwh rwh 15 14 13 12 11 10 9 8 7 6 5 ...

Page 170: ...um PMEM size available PMEM_SZ_AV This field may subsequently be written to force a smaller PMEM size to be visible to software3 PMEM_SZ_CFG specifies the configured PMEM size in Kbytes 000H Reserved 004H 4Kbyte Program Memory 008H 8Kbyte Program Memory 00CH 12Kbyte Program Memory 100H 256Kbyte Program Memory 1 Configuration of program memory and instruction cache size is not intended to be perfor...

Page 171: ... 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FME STF 0 FPE STF 0 FBE STF 0 FRE STF r rh r rh r rh r rh Field Bits Type Description FRESTF 0 rh Fetch Range Error Synchronous Trap Flag FBESTF 2 rh Fetch Bus Error Synchronous Trap Flag FPESTF 12 rh Fetch Peripheral Error Synchronous Trap Flag FMESTF 14 rh Fetch MSIST Error Synchronous Trap Flag 0 1 11 3 15 31 16 r Reserved Read as 0...

Page 172: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_32B REV xx rh rh Field Bits Type Description MOD_REV 7 0 rh Revision Number 01H For version numbering The value of the revision starts with 01H first revision up to FFH FFH Last revision MOD_32B 15 8 rh 32 Bit Module Enable C0H A value of C0H in this field indicates a 32 bit module with a 32 bit module ID register MOD 31 16 rh Module Identification Number 0BH ...

Page 173: ... features 128 Kbyte total Data Memory DMEM with software configurable split between LDRAM and DCache The following configurations are supported Data Cache features LDRAM DCache 124 4 126 2 128 0 DCache CPU Interface DMI Control Registers DMI_BlockDiag To From Data Local Memory Bus 128 Data Switch Data Alignment Interface Control 64 DLMB Interface Slave Master 128 128 LDRAM 128 Data Memory Interfac...

Page 174: ...o matter the alignment then the requested data is returned to the CPU in a single cycle If the data access is made to the end of an LDRAM line such that the requested data would span two LDRAM lines a single wait cycle is incurred The LDRAM may also be accessed from the LMB Slave interface by another bus master with both read and write transactions supported The LDRAM may be accessed by the LMB Sl...

Page 175: ...e refill sequence started immediately If the line has been modified then the dirty data is first written back to main memory before the refill is initiated Due to the single dirty bit per cache line 128 bits of data will always be written back resulting in LMB Burst Transfer 2 BTR2 transactions Data Cache refills always result in the full cache line being refilled with the critical double word of ...

Page 176: ...st the DMI Asynchronous Trap Flag Register DMI_ATR holds the flags indicating the cause of a DAE trap The possible error conditions and their corresponding trap flag register bits are as follows Range Error Range errors are caused by accesses to LDRAM space D000 0000H D3FF FFFFH outside the range of the LDRAM Load accesses which generate a range error will result in the DMI_STR LRESTF flag being s...

Page 177: ... CWLESTF flag being set whilst store accesses will result in the DMI_ATR CWSEATF flag being set Cache Flush Error Cache flush errors are detected when a data cache or DLB writeback sequence initiated by a cache management instruction cachea w cachea wi cachei w cachei wi encounters a bus error on the LMB Cache management instructions which encounter such errors will result in the DMI_ATR CFEATF fl...

Page 178: ...agged in DMI_STR DMI_ATR register in case of a CPU load store access Table 20 DMI Registers Short Name Description Offset Address Access Mode Reset Read Write DMI_ID DMI Identification Register FC08H U SV 32 SV 32 Class 3 Reset 0008 C0XXH DMI_CON DMI Control Register FC10H U SV 32 SV E 32 Class 3 Reset 0800 0802H DMI_STR DMI Synchronous Trap Flag Register FC18H U SV 321 1 Reading these registers i...

Page 179: ...e Available Size of the maximum available Data Cache Encoding is as per DC_SZ_CFG DMEM_SZ_AV 15 4 r Maximum Data Memory Size Available Size of the maximum available Data Memory where size of DMEM size of LDRAM size of DCACHE Encoding is as per DMEM_SZ_CFG DC_SZ_CFG 19 16 rwh Data Cache Size Configuration Configuration of the Data Cache Size Any data memory not utilised as data cache is configured ...

Page 180: ...rce a smaller DMEM size to be visible to software2 DMEM_SZ_CFG specifies the configured DMEM size in Kbytes 000H Reserved 004H 4Kbyte Data Memory 008H 8Kbyte Data Memory 00CH 12Kbyte Data Memory 100H 256Kbyte Data Memory 1 Writing this field with a value larger than the maximum available DCache size DC_SZ_AV resets this field to DC_SZ_AV 2 Writing this field with a value larger than the maximum av...

Page 181: ...s contents DMI_STR DMI Synchronous Trap Flag Register F87F FC18H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 LME STF 0 CWL EST F 0 CRL EST F 0 LBE STF 0 LRE STF r rh r rh r rh rh r rh Field Bits Type Description LRESTF 0 rh Load Range Synchronous Error Trap Flag LBESTF 2 rh Bus Load Synchronous Error Trap Flag CRLESTF 6 rh Cach...

Page 182: ...0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SME ATF 0 CME ATF CFE ATF CWS EAT F 0 CRS EAT F 0 SBE ATF 0 SRE ATF 0 rh r rh rh rh r rh r rh r rh r Field Bits Type Description SREATF 1 rh Store Range Asynchronous Error Trap Flag SBEATF 3 rh LMB Bus Store Asynchronous Error Trap Flag CRSEATF 7 rh Cache Refill Store Asynchronous Error Trap Flag CWSEATF 9...

Page 183: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_32B REV xx rh rh Field Bits Type Description MOD_REV 7 0 rh Revision Number 01H For version numbering The value of the revision starts with 01H first revision up to FFH FFH Last revision MOD_32B 15 8 rh 32 Bit Module Enable C0H A value of C0H in this field indicates a 32 bit module with a 32 bit module ID register MOD 31 16 rh Module Identification Number 08H ...

Page 184: ...al sub blocks Clock Control see Section 3 1 Reset Operation see Section 3 2 External Interface see Section 3 3 Power Management see Section 3 4 Software Boot Support see Section 3 5 SRAM ECC Control see Section 3 6 Die Temperature Measurement see Section 3 7 Watchdog Timer see Section 3 8 Emergency Stop Control see Section 3 9 Interrupt Generation see Section 3 10 NMI Trap Generation see Section 3...

Page 185: ...dules Figure 3 1 shows the structure of the TC1784 clock system The master clock fPLL is generated by the oscillator circuit and the PLL phase locked loop unit see Section 3 2 The functionality of the control blocks shown in Figure 3 1 varies depending on the functional unit being controlled Some functional units such as the watchdog timer are directly driven by the system clock The implemented cl...

Page 186: ...CAN GPTA0 LTCA 2 MSC0 MSC1 MLI0 ADC0 ADC1 FADC STM SBCU SCU DMI DMU PMI PMU TriCore TM CPU ICU fLMB fFPI fMCDS fPLL_ERAY DMA MCDS ERAY PORTs PCP2 fLMB PCP2 Domain ERAY Domain FPI BUS Domain TC1784 Toplevel _clock_1784 fREFCLK2 fREFCLK1 fPCP fPCP XTAL1 XTAL2 EXTCLK1 EXTCLK0 CGU fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS fSYS SSC2 ...

Page 187: ...or circuit OSC two Phase Locked Loop modules PLL and PLL_ERAY and a Clock Control Unit CCU The CGU can convert a low frequency external clock signal to a high speed internal clock The CGU provides clock signals for the different parts of the device that can be configured depending on the application needs within certain limits Figure 3 2 Clock Generation Unit Block Diagram The following sections d...

Page 188: ...ck signal directly not using an external crystal ceramic resonator and bypassing the oscillator the input frequency needs to be equal or greater than PLL VCO input frequency the value is listed in the Data Sheet When using an external clock signal it must be connected to XTAL1 XTAL2 is left open unconnected Figure 3 3 TC1784 Direct Clock Input External Crystal Ceramic Resonator Mode Figure 3 4 sho...

Page 189: ... The C1 and C2 values shown in the Data Sheet can be used as starting points for the negative resistance evaluation and for non productive systems The exact values and related operating range are dependent on the crystal ceramic resonator frequency and have to be determined and optimized together with the crystal ceramic resonator vendor using the negative resistance method Oscillation measurement...

Page 190: ...ing too low input frequencies Detecting too high input frequencies Spike detection for the OSC input frequency Different operating modes Prescaler Mode Freerunning Mode Normal Mode VCO Power Down Glitchless switching between both K Dividers Glitchless switching between Normal Mode and Prescaler Mode PLL Functional Description The PLL consists of a Voltage Controlled Oscillator VCO with a feedback ...

Page 191: ... frequency fOSC is divided down by a factor P multiplied by a factor N and then divided down by a factor K2 The output frequency is given by 3 1 Prescaler Mode In Prescaler Mode the reference frequency fOSC is only divided down by a factor K1 PLL_block P Divider VCO f OSC N Divider Lock Detection OSC WDG K1 Divider K2 Divider M U X f PLL f DIV fK2 fK1 PLLCON0 VCOBYP PLLSTAT FINDISC fVCO fREF OSCCO...

Page 192: ... to obtain a stabile master clock from the VCO part The expected input frequency is selected via the bit field OSCCON OSCVAL The OSC_WDT checks for too low frequencies and for too high frequencies The frequency that is monitored is fOSCREF which is derived for fOSC 3 4 The divider value OSCCON OSCVAL has to be selected in a way that fOSCREF is 2 5 MHz Note fOSCREF has to be within the range of 2 M...

Page 193: ...tion and Operation of the Freerunning Mode In Freerunning Mode the PLL is running at its VCO base frequency and fPLL is derived from fVCO only by the K2 Divider The Freerunning Mode is entered after each System Reset Figure 3 6 PLL Free Running Mode Diagram The output frequency is given by 3 5 The Freerunning Mode is selected by the following settings PLLCON0 VCOBYP 0 PLLCON0 SETFINDIS 1 The Freer...

Page 194: ...e this has to be done carefully Depending on the selected divider value of the K2 Divider the duty cycle of the clock is selected This can have an impact for the operation with an external communication interface The duty cycles values for the different K2 divider values are defined in the Data Sheet Configuration and Operation of the Prescaler Mode In Prescaler Mode the PLL is running at the exte...

Page 195: ...ng on the selected divider value of the K1 Divider the duty cycle of the clock is selected This can have an impact for the operation with an external communication interface The duty cycles values for the different K1 divider values are defined in the Data Sheet The Prescaler Mode is requested from the Freerunning or Normal Mode by setting bit PLLCON VCOBYP The Prescaler Mode is entered when the s...

Page 196: ...n the Normal Mode does require an input clock frequency of fOSC Therefore it is recommended to check and monitor if an input frequency fOSC is available at all by checking OSCCON PLLLV For a better monitoring also the upper frequency can be monitored via OSCCON PLLHV The system operation frequency is controlled in the Normal Mode by the values of the three dividers P N and K2 A modification of the...

Page 197: ...ghtly reduced power consumption but to a slightly increased jitter Selecting P and N in a way that fVCO is in the upper area of its allowed values leads to a slightly increased power consumption but to a slightly reduced jitter After the P N and K2 dividers are updated for the first configuration the indication of the VCO Lock status should be await PLLSTAT VCOLOCK 1 Note It is recommended to rese...

Page 198: ...remains connected to the VCO VCO Power Down Mode The PLL offers a VCO Power Down Mode This mode can be entered to save power within the PLL The VCO Power Down Mode is entered by setting bit PLLCON0 VCOPWD While the PLL is in VCO Power Down Mode only the Prescaler Mode is operable Please note that selecting the VCO Power Down Mode does not automatically switch to the Prescaler Mode So before the VC...

Page 199: ...ontrolled Oscillator VCO with a feedback path A divider in the feedback path N Divider divides the VCO frequency down The resulting frequency is then compared with the externally provided frequency The phase detection logic determines the difference between the two clocks and accordingly controls the frequency of the VCO fVCO A PLL_ERAY lock detection unit monitors and signals this condition The p...

Page 200: ...e Bypass Mode Normal Mode Prescaler Mode Freerunning Mode Normal Mode In Normal Mode the input frequency fOSC is multiplied by a factor N and then divided down by a factor K2 The output frequency is given by 3 8 Prescaler Mode PLLERAY _block VCO fOSC N Divider Lock Detection K1 Divider M U X fPLL_ERAY f DIV PLLERAYCON0 VCOBYP PLLERAYCON0 FINDIS f VCO fREF PLLERAYSTAT VCOLO CK PLLERAYSTAT K1RDY PLL...

Page 201: ...down by a factor K2 The output frequency is given by 3 10 Configuration and Operation of the Freerunning Mode In Freerunning Mode the PLL_ERAY is running at its VCO base frequency and fPLL_ERAY is derived from fVCO only by the K2 Divider The Freerunning Mode is entered after each System Reset Figure 3 10 PLL_ERAY Free Running Mode Diagram fPLL fOSC K1 fPLL fVCObase K2 PLLERAY _FreeRunning _Mode vs...

Page 202: ...LERAYCON0 OSCDISCDIS is cleared This mechanism allows a fail safe operation of the PLL_ERAY as in emergency cases still a clock is available The frequency of the Freerunning Mode fVCObase is listed in the Data Sheet Depending on the selected divider value of the K2 Divider the duty cycle of the clock is selected This can have an impact for the operation with an external communication interface The...

Page 203: ...tter monitoring also the upper frequency can be monitored via OSCCON PLLHV For the Prescaler Mode there are no requirements regarding the frequency of fOSC The system operation frequency is controlled in the Prescaler Mode by the value of the K1 Divider When the value of PLLERAYCON1 K1DIV was changed the next update of this value should not be done before bit PLLERAYSTAT K1RDY is set Depending on ...

Page 204: ...requested to be left by clearing bit PLLERAYCON VCOBYP The Prescaler Mode is left when the status bit PLLERAYSTAT VCOBYST is cleared Configuration and Operation of the Normal Mode In Normal Mode the PLL_ERAY is running at the external frequency fOSC and fPLL_ERAY is multiplied by a factor N and then divided down by a factor K2 Figure 3 12 PLL_ERAY Normal Mode Diagram The output frequency is given ...

Page 205: ...quency of the Normal Mode should be selected in a way that it matches or is only slightly higher as the one used in the Prescaler Mode This avoids big changes in the system operation frequency and therefore power consumption when switching later from Prescaler Mode to Normal Mode The N divider should be selected in the following way Selecting N in a way that fVCO is in the lower area of its allowe...

Page 206: ...a case an NMI trap is generated if the according NMI trap is enabled Additionally the OSC clock input fOSC is disconnected from the PLL_ERAY VCO to avoid unstable operation due to noise or sporadic clock pulses coming from the oscillator circuit Without a clock input fOSC the PLL_ERAY gradually slows down to its VCO base frequency and remains there This automatic feature can be disabled by setting...

Page 207: ...allows the MCDS to generate time stamps independent of the selected LMB Bus and FPI Bus clock speeds Clock Divider Limitations There are several limitation and relations between the different clocks that could be configured via the CCUCON0 and CCUCON1 registers fLMB fFPI or fLMB 2 fFPI fLMB fMCDS OR 2 fMCDS fLMB fPCP OR 2 fPCP fPLL 24 fREFCLK1 fPLL_ERAY 24 fREFCLK2 fMCDS fFPI fPCP fFPI f PLL CCU f...

Page 208: ...an lead to spikes at pins EXTCLK0 1 Note Only the burst flash clock of the EBU is not included as the EBU provides a separate pin here Additionally a connection to the GPTA module is implemented to support the start up control of an external crystal for the device clock generation The first time before the master clock is generated based on a external crystal 1000 cycles of the crystal clock fOSC ...

Page 209: ...uty cycle and outputs the clock fOUT The fractional divider is controlled by the FDR register Figure 3 15 shows the fractional divider block diagram The adder logic of the fractional divider can be configured for two operating modes Reload counter addition of 1 generating an output clock pulse on counter overflow Adder that adds a STEP value to the RESULT value and generates an output clock pulse ...

Page 210: ...es an output clock pulse on counter overflow Fractional Divider Operating Modes The fractional divider has two operating modes Normal Divider Mode Fractional Divider Mode Normal Divider Mode In Normal Divider Mode FDR DM 01B the fractional divider behaves as a reload counter addition of 1 that generates an output clock pulse on the transition from 3FFH to 000H FDR RESULT represents the counter val...

Page 211: ...er accuracy than in Normal Divider Mode In Fractional Divider Mode a pulse is generated depending on the result of the addition FDR RESULT FDR STEP If the addition leads to an overflow over 3FFH a pulse is generated for the divider by two Note that in Fractional Divider Mode the clock fOUT can have a maximum period jitter of one fFPI clock period The output frequencies in Fractional Divider Mode a...

Page 212: ...cy can be selected in small steps fOUT always provides complete output periods Register EXTCON provides control over the output generation frequency activation extclk EXTCON EN1 f MA M U X P1 0 EXTCON SEL1 fOUT EXTCON DIV1 f FPI Reserved Reserved 1 M U X Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EXTCON NSEL fOSC f PLL_ERAY ...

Page 213: ... bit indicates if the frequency output of OSC is usable for the VCO part of the PLL This is checked by the Oscillator Watchdog of the PLL 0B The OSC frequency is not usable Frequency fREF is too low 1B The OSC frequency is usable OSCRES 2 w Oscillator Watchdog Reset 0B The Oscillator Watchdog of the PLL is not cleared and remains active 1B The Oscillator Watchdog of the PLL is cleared and restarte...

Page 214: ...requency output of OSC is usable for the VCO part of the PLL This is checked by the Oscillator Watchdog of the PLL 0B The OSC frequency is not usable Frequency fOSC is too high 1B The OSC frequency is usable PLLSP 9 rh Oscillator for PLL Valid Spike Status Bit This bit indicates if the frequency output of OSC is usable for the VCO part of the PLL This is checked by the Oscillator Watchdog of the P...

Page 215: ...uld be written with 0 0 0 15 12 31 21 r Reserved Read as 0 should be written with 0 PLLSTAT PLL Status Register 014H Reset Value 0000 0009H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 K2R DY K1R DY FIN DIS VCO LOC K PWD STA T VCO BY ST r rh rh rh rh rh rh Field Bits Type Description VCOBYST 0 rh VCO Bypass Status 0B Freerunning Normal Mode is entered...

Page 216: ...k the fVCO goes to the lower boundary of the VCO frequency if the reference clock input is lower than expected FINDIS 3 rh Input Clock Disconnect Select Status 0B The input clock from the oscillator is connected to the VCO part 1B The input clock from the oscillator is disconnected from the VCO part Note This bit can be set by setting bit PLLCON0 SETFINDIS Note This bit can be cleared by setting b...

Page 217: ...CON0 PLL Configuration 0 Register 018H Reset Value 0001 C600H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDIV 0 RES LD 0 PLL PWD rw rw r w r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDIV 0 0 OSC DISC DIS CLR FIN DIS SET FIN DIS 0 VCO PWD VCO BYP rw rw r rw w w rw rw rw Field Bits Type Description VCOBYP 0 rw VCO Bypass 0B Normal operation VCO is not bypassed 1B Prescaler Mode VCO is bypasse...

Page 218: ...lock case 0B In case of a PLL loss of lock bit PLLSTAT FINDIS is set 1B In case of a PLL loss of lock bit PLLSTAT FINDIS is cleared NDIV 15 9 rw N Divider Value The value the N Divider operates is NDIV 1 PLLPWD 16 rw PLL Power Saving Mode 0B The complete PLL block is put into a Power Saving Mode and can no longer be used Only the Bypass Mode is active if previously selected 1B Normal behavior RESL...

Page 219: ... 8 7 6 5 4 3 2 1 0 0 K2DIV r rw Field Bits Type Description K2DIV 6 0 rw K2 Divider Value The value the K2 Divider operates is K2DIV 1 K1DIV 22 16 rw K1 Divider Value The value the K1 Divider operates is K1DIV 1 0 15 7 31 23 r Reserved Read as 0 should be written with 0 PLLERAYSTAT PLL_ERAY Status Register 024H Reset Value 0000 0038H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 ...

Page 220: ...ncy 1B The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation Note In case of a loss of VCO lock the fVCO goes to the upper boundary of the VCO frequency if the reference clock input is greater than expected Note In case of a loss of VCO lock the fVCO goes to the lower boundary of the VCO frequency if the reference clock input is lower than expected FINDIS 3 rh ...

Page 221: ... value or not this is of interest if the values is changed 0B K2 Divider is not ready to operate with the new value 1B K2 Divider is ready to operate with the new value 0 31 6 r Reserved Read as 0 should be written with 0 PLLERAYCON0 PLL_ERAY Configuration 0 Register 028H Reset Value 0001 2E00H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 RES LD 0 1 r w r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 222: ... clock from the oscillator is connected to the VCO part OSCDISCDIS 6 rw Oscillator Disconnect Disable This bit is used to disable the control PLLERAYSTAT FINDIS in a PLL_ERAY loss of lock case 0B In case of a PLL loss of lock bit PLLERAYSTAT FINDIS is set 1B In case of a PLL loss of lock bit PLLERAYSTAT FINDIS is cleared NDIV 13 9 rw N Divider Value The value the N Divider operates is NDIV 1 RESLD...

Page 223: ...3 2 1 0 0 K2DIV r rw Field Bits Type Description K2DIV 6 0 rw K2 Divider Value The value the K2 Divider operates is K2DIV 1 K1DIV 22 16 rw K1 Divider Value The value the K1 Divider operates is K1DIV 1 0 15 7 31 23 r Reserved Read as 0 should be written with 0 CCUCON0 CCU Clock Control Register 0 030H Reset Value 8000 0001H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LCK 0 PCPDIV 0 0 rh r rw r ...

Page 224: ...8 1000B fFPI fPLL 9 1001B fFPI fPLL 10 1010B fFPI fPLL 11 1011B fFPI fPLL 12 1100B fFPI fPLL 13 1101B fFPI fPLL 14 1110B fFPI fPLL 15 1111B fFPI fPLL 16 LMBDIV 11 8 rw LMB Bus Divider Reload Value 0000B fLMB fPLL 0001B fLMB fPLL 2 0010B fLMB fPLL 3 0011B fLMB fPLL 4 0100B fLMB fPLL 5 0101B fLMB fPLL 6 0110B fLMB fPLL 7 0111B fLMB fPLL 8 1000B fLMB fPLL 9 1001B fLMB fPLL 10 1010B fLMB fPLL 11 1011B...

Page 225: ...CP fPLL 11 1011B fPCP fPLL 12 1100B fPCP fPLL 13 1101B fPCP fPLL 14 1110B fPCP fPLL 15 1111B fPCP fPLL 16 LCK 31 rh Lock Status This bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect 0B The register is unlocked and can be updated 1B The register is locked and can not be updated 0 19 16 rw Reserved Should be...

Page 226: ... 8 7 6 5 4 3 2 1 0 0 REFCLKDIV 0 MCDSDIV r r r rw Field Bits Type Function MCDSDIV 3 0 rw MCDS Divider Reload Value 0000B fMCDS fPLL 0001B fMCDS fPLL 2 0010B fMCDS fPLL 3 0011B fMCDS fPLL 4 0100B fMCDS fPLL 5 0101B fMCDS fPLL 6 0110B fMCDS fPLL 7 0111B fMCDS fPLL 8 1000B fMCDS fPLL 9 1001B fMCDS fPLL 10 1010B fMCDS fPLL 11 1011B fMCDS fPLL 12 1100B fMCDS fPLL 13 1101B fMCDS fPLL 14 1110B fMCDS fPL...

Page 227: ...CLK1 fPLL 12 0110B fREFCLK1 fPLL 14 0111B fREFCLK1 fPLL 16 1000B fREFCLK1 fPLL 18 1001B fREFCLK1 fPLL 20 1010B fREFCLK1 fPLL 22 1011B fREFCLK1 fPLL 24 1100B fREFCLK1 fPLL 26 1101B fREFCLK1 fPLL 28 1110B fREFCLK1 fPLL 30 1111B fREFCLK1 fPLL 32 LCK 31 rh Lock Status This bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side ha...

Page 228: ...B The configured external clock is provided SEL0 5 2 rw External Clock Select for EXTCLK0 This bit field defines the clock source that is selected as output for pin EXTCLK0 0000B fOUT is selected for the external clock 0001B fPLL is selected for the external clock 0010B Reserved do not use this combination 0110B Reserved do not use this combination 0111B fPLL_ERAY is selected for the external cloc...

Page 229: ...18 rw External Clock Select for EXTCLK1 This bit field defines the clock source that is selected as output for pin EXTCLK1 0000B fOUT is selected for the external clock 0001B fPLL is selected for the external clock 0010B Reserved do not use this combination 0110B Reserved do not use this combination 0111B fPLL_ERAY is selected for the external clock signal 1000B fOSC is selected for the external c...

Page 230: ...h each input clock cycle DM 15 14 rw Divider Mode This bit fields determines the functionality of the fractional divider block 00B Fractional divider is switched off no output clock is generated The Reset External Divider signal is 1 RESULT is not updated default after System Reset 01B Normal Divider Mode selected 10B Fractional Divider Mode selected 11B Fractional divider is switched off no outpu...

Page 231: ...d No change except when writing bit field DM This bit is cleared when external clock enable input is asserted In case of a conflict between hardware clear and software set of DISCLK the software set wins Any write or read modify write action leads to the described behavior As a result read modify write operations should be avoided 0 13 10 30 26 r Reserved Read as 0 should be written with 0 Field B...

Page 232: ...Generation The TC1784 on chip modules have two registers for clock control Clock Control Register CLC Fractional Divider Register FDR The following sections describes the general functionality of CLC and FDR The module specific implementation details are described in the corresponding module chapters ...

Page 233: ...ays indicates whether a module is currently switched off DISS 1 or switched on DISS 0 Write operations to the non CLC registers of disabled modules are not allowed However the CLC of a disabled module can be written An attempt to write to any of the other writable registers of a disabled module except CLC will cause the corresponding Bus Control Unit BCU to generate a bus error A read operation of...

Page 234: ...t should only count the time when the user s application is running Note that it is never appropriate for application software to set the SPEN bit The Suspend Mode should only be set by a debug software To guard against application software accidently setting SPEN bit SPEN is specially protected by the mask bit SBWE The SPEN bit can only be written if during the same write operation SBWE is set to...

Page 235: ... debugging of the application s program On the other hand if a problem is observed to relate to the operation of the external analog to digital converter itself it might be necessary to stop the unit as fast as possible in order to monitor its current instantaneous state To do this the Fast Shut off Mode option would be selected Although proper continuation of the application s program might not b...

Page 236: ...er may result in a longer read cycle access time on the FPI Bus for peripheral units with destructive read access e g the ASC Module Clock Register Implementations Table 3 1 shows which of the CLC register bits bit fields are implemented for each peripheral module in the TC1784 and which modules are equipped with a fractional divider Table 3 1 Clock Generation Implementation of the TC1784 Peripher...

Page 237: ...erflow Normal Divider Mode In Normal Divider Mode MOD_FDR DM 01B the fractional divider behaves as a reload counter addition of 1 that generates an output clock pulse at fMOD on the transition from 3FFH to 000H MOD_FDR RESULT represents the counter value and MOD_FDR STEP determines the reload value The output frequencies in Normal Divider Mode are defined according to the following formulas with n...

Page 238: ... 1023 3 18 Note Each write to register FDR with bit field DM 01B or 10B sets bit field RESULT to 3FFH Suspend Mode The operation of the fractional divider can be controlled by the Suspend Mode Request input This input is activated in Suspend Mode by the on chip debug control logic In Suspend Mode module registers are accessible for read and write actions but other module internal functions are fro...

Page 239: ...unchanged inactive switched off 01B continuously updated active Normal Divider Mode 10B Fractional Divider Mode 11B unchanged inactive switched off Suspend Mode 00B 00B unchanged inactive switched off 01B continuously updated active Normal Divider Mode 10B Fractional Divider Mode 11B unchanged inactive switched off 01B 00B unchanged switched off 01B loaded with 3FFH halted 10B 11B unchanged inacti...

Page 240: ...ly from module state from MultiCAN 1 This column shows whether a suspend acknowledge from a FDR controlled module depends on the module s state or not If a suspend acknowledge depends from the module state typically module operations such as serial transmissions are terminated before a suspend request is acknowledged back to the fractional divider Note that bit FDR SM must be cleared granted suspe...

Page 241: ...ble is requested DISS 1 rh Module Disable Status Bit Bit indicates the current status of the module 0B Module is enabled 1B Module is disabled If the RMC field is implemented and if it is 0 DISS is set automatically SPEN 2 rw Module Suspend Enable Used for enabling the Suspend Mode 0B Module cannot be suspended suspend is disabled 1B Module can be suspended suspend is enabled This bit can be writt...

Page 242: ... via Disable Control Feature Secure Clock Switch Off selected 1B Fast clock switch off in Suspend Mode selected This bit can be written only if SBWE is set during the same write operation RMC 15 8 rw 8 Bit Clock Divider Value in RUN Mode This is a maximum 8 bit divider value for clock fFPI If RMC is set to 0 the module is disabled 0 7 6 31 16 r Reserved Read as 0 should be written with 0 MOD_FDR F...

Page 243: ...EQ and SUSACK set 00B Clock generation continues 01B Clock generation is stopped and the clock output signal is not generated RESULT is not changed except when writing bit field DM with 01B or 10B 10B Clock generation is stopped and the clock output signal is not generated RESULT is loaded with 3FFH 11B Same as SC 10B but signal Reset External Divider is 1 independently of bit field DM DM 15 14 rw...

Page 244: ...d SUSREQ are set SUSREQ 29 rh Suspend Mode Request 0B Suspend Mode is not requested 1B Suspend Mode is requested Suspend Mode is entered when SUSREQ and SUSACK are set ENHW 30 rw Enable Hardware Clock Control 0B Bit DISCLK cannot be cleared by a high level of the External Clock Enable input 1B Bit DISCLK is cleared while the External Clock Enable input is at high level DISCLK 31 rwh Disable Clock ...

Page 245: ...an asynchronous reset assertion independently of any clock The activation of an asynchronous reset is asynchronous to the system clock whereas its de assertion is synchronized Trigger sources that need a clock in order to be asserted such as the input signals ESR0 ESR1 the WDT trigger TP trigger or the SW trigger Note A PORST reset should only triggered for power related issue and not for pure fun...

Page 246: ... some register bits that are affected by this reset Table 3 4 Effects of Resets for Reset Signal Activation Reset Request Trigger Application Reset Debug Reset System Reset PORST Activated Activated Activated ESR0 Configurable Not Activated Configurable ESR1 Configurable Not Activated Configurable WDT Configurable Not Activated Configurable SW Configurable Not Activated Configurable OCDS Reset Not...

Page 247: ...thout modification of the application setting On chip Static RAMs1 OVRAM Not affected reliable Not affected reliable Affected un reliable Affected un reliable LDRAM Not affected reliable Not affected reliable Affected un reliable Affected un reliable DCACHE Not affected reliable Not affected reliable Affected un reliable Affected un reliable SPRAM Not affected reliable Not affected reliable Affect...

Page 248: ... dedicated resets Figure 3 18 Reset State Machine Block Diagram 3 2 7 Reset Counters RSTCNTA and RSTCNTD There are two reset counters implemented RSTCNTA is the reset counter that controls the reset length for all non debug relevant resets System Reset and Application Reset RSTCNTD is the reset counter that controls the reset length for the Debug Reset The reset counters can be used for the follow...

Page 249: ...s configurable But if a reset request trigger is asserted continuously longer than the counter needs for the complete count down process the reset cannot be deasserted before the reset request trigger is also deasserted Anyway the counter is not started again instead the control block informs the distribution logic DIST that the reset still has to be asserted until the reset request trigger is dea...

Page 250: ...equest trigger B is also configured to result in an Application Reset If the reset request trigger B is de asserted before RSTCNTA reached zero the Application Reset is de asserted when RSTCNTA reaches zero If the reset request trigger B is de asserted after RSTCNTA reached zero the Application Reset is de asserted when the reset request trigger B is de asserted 3 2 8 3 Example3 Reset request trig...

Page 251: ...guration of the dedicated bit field for this trigger in register RSTCON 3 2 10 Debug Specific Behavior For safety reasons it is required by the debugger that if the OCDS system is disabled a Debug Reset is also asserted every time an Application Reset is asserted 3 2 11 EEC Reset Specific Behavior The complete EEC part is reset with the Power on Reset For safety reasons it is required by the debug...

Page 252: ... 26 25 24 23 22 21 20 19 18 17 16 0 TP CB3 CB1 CB0 OCD S POR ST r rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SW WDT 0 ESR 1 ESR 0 r rh rh r rh rh Field Bits Type Description ESR0 0 rh Reset Request Trigger Reset Status for ESR0 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger Note This bit is set if the ESR0 pin is confi...

Page 253: ...0H or RSTCON ESR1 00B WDT 3 rh Reset Request Trigger Reset Status for WDT 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger SW 4 rh Reset Request Trigger Reset Status for SW 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger PORST 16 rh Reset Request Trigger Reset Status for P...

Page 254: ...eset Request Trigger Reset Status for Cerberus Debug Reset 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger CB3 20 rh Reset Request Trigger Reset Status for Cerberus Application Reset 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger TP 21 rh Reset Request Trigger Reset Stat...

Page 255: ... Application Reset Counter Reload Value This bit field defines the reload value of RSTCNTA This value is always used when counter RSTCNTA is started RELD 31 16 rw Debug 1 Reset Counter Reload Value This bit field defines the reload value of RSTCNTD This value is always used when counter RSTCNTD is started RSTCON Reset Configuration Register 058H Reset Value 0000 02A2H 31 30 29 28 27 26 25 24 23 22...

Page 256: ... is generated for a trigger of ESR1 reset 10B An Application Reset is generated for a trigger of ESR1 reset 11B Reserved do not use this combination WDT 7 6 rw WDT Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from WDT reset 00B No reset is generated for a trigger of WDT 01B A System Reset is generated for a trigger of WDT rese...

Page 257: ...er 05CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 STM DIS r rw rw Field Bits Type Description STMDIS 0 rw STM Disable Reset This bit field defines if an Application Reset leads to an reset for the STM 0B An Application Reset resets the STM 1B An Application Reset has no effect for the STM 0 7 1 rw Reserved Should be written...

Page 258: ...with the content of SWCFG upon an Application Reset 1B Bit field STSTAT HWCFG is updated with the content of SWCFG upon an Application Reset SWRSTREQ 1 w Software Reset Request 0B No SW Reset is requested 1B A SW Reset request trigger is generated This bit is automatically cleared and read always as zero SWCFG 15 8 rw Software Boot Configuration A software boot configuration different from the ext...

Page 259: ...ication Trap request triggers Interrupt request triggers Non SCU module triggers The first three points are covered by the ESR pads and the last two points by the ERU pads 3 3 1 External Service Requests ESRx The ESR pins can be used to trigger either a reset a trap NMI as reset output or as data pin Figure 3 19 ESR Operation 3 3 1 1 ESRx as Reset Request Trigger An ESR0 ESR1 reset request trigger...

Page 260: ...push pull An enable function for the output driver input and or output capability An enable function for the pull up down resistance 3 3 1 2 ESRx as Reset Output The external pins ESR0 ESR1 can serve as an reset output open drain for the Application Reset Note The reset output is only asserted for the duration the reset counter RSTCNTA is active During a possible reset extension the reset output i...

Page 261: ... 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EDCON 0 DF EN 0 r rw r rw r Field Bits Type Description DFEN 4 rw Digital Filter Enable This bit defines if the 3 stage median filter of the ESR0 is used or bypassed 0B The filter is bypassed 1B The filter is used EDCON 8 7 rw Edge Detection Control This bit field defines the edges that lead to an ESR0 trigger of the ...

Page 262: ... 21 20 19 18 17 16 0 0 0 r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC1 0 PC0 0 rw r rw r Field Bits Type Description PC0 7 4 rw Control for ESR0 Pin This bit field defines the ESR0 pin functionality according to the coding table see Table 3 9 PC1 15 12 rw Control for ESR1 Pin This bit field defines the ESR1 pin functionality according to the coding table see Table 3 10 0 23 20 rw Reserved Have ...

Page 263: ...ll up device connected 0X11B No input pull device connected 1000B Input is active and not inverted Output is active Push pull General purpose Output 1001B Output drives a 0 for System Resets a weak pull up is active otherwise 1010B Output drives a 0 for Application Resets a weak pull up is active otherwise 1011B Reserved do not use this combination 1100B the input is active and not inverted Output...

Page 264: ... Table 3 10 PC1 Coding PC1 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 0X00B Input is active and not inverted Output is inactive No input pull device connected 0X01B Input pull down device connected 0X10B Input pull up device connected 0X11B No input pull device connected 1000B Input is active and not inverted Output is active Push pull General purpose Output...

Page 265: ...4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 P1 P0 r rwh rwh rwh Field Bits Type Description Px x 0 1 x rwh Output Bit x This bit determines the level at the output pin ESRx if the output is selected as GPIO output 0B The output level of ESRx is 0 1B The output level of ESRx is 1 Px can also be set cleared by control bits o...

Page 266: ...r toggle the corresponding bit in the output register OUT The function of this bit is shown in Table 3 11 PRx x 0 1 x 16 w Clear Bit x Setting this bit will clear or toggle the corresponding bit in the port output register OUT The function of this bit is shown in Table 3 11 0 2 18 w Reserved Read as 0 have to be written with 0 0 15 3 31 19 r Reserved Read as 0 should be written with 0 Table 3 11 F...

Page 267: ...cal value at the GPIO pin independently whether the pin is selected as input or output IN Input Register 0ACH Reset Value 0000 000XH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 P1 P0 r rh rh Field Bits Type Description Px x 0 1 x rh Input Bit x This bit indicates the level at the input pin ESRx 0B The input level of ESRx is 0 1B The input level of ES...

Page 268: ... Output Channel y 4 independent Output Channels y for combination of events definition of their effects and distribution to the system interrupt generation Figure 3 20 External Request Unit Overview These tasks are handled by the following building blocks An External Request Select Unit ERSx per Input Channel allows the selection of one input vector out of the 4 possible inputs available An Event ...

Page 269: ...he Input Channels to the Output Channels An Output Gating Unit OGUy per Output Channel that combines the available trigger events and status information from the Input Channels An event of one Input Channel can lead to reactions of several Output Channels or also events of several Input Channels can be combined to a reaction of one Output Channel pattern detection Different types of reactions are ...

Page 270: ...ain trigger functions eventually combined with other signals e g to generate an interrupt trigger in case a start of frame is detected at a selected communication 3 3 2 3 External Request Select Unit ERS Each ERS combines four inputs to the one input signal of the respective input channel Figure 3 22 shows the structure of this block In addition to the direct choice of either input Ax or Bx or the...

Page 271: ...y the associated ERSx unit Each ETLx is based on an edge detection block where the detection of a rising or a falling edge can be individually enabled Both edges lead to a trigger event if both enable bits are set e g to handle a toggling input Each pair of the four ETL units has an associated EICRy register that controls all options of an ETL the register also holds control bits for the associate...

Page 272: ... Gating Units OGUz in parallel see Figure 3 24 to provide pattern detection capability of all OGUz units based on different or the same status flags In addition to the modification of the status flag a trigger pulse output TRxz of ETLx can be enabled by bit EICRy EIENx and selected to trigger actions in one of the OGUz units The target OGUz for the trigger is selected by bit field EICRy INPx The t...

Page 273: ...CU V1 18 3 3 2 5 Connecting Matrix The connecting matrix distributes the trigger signals TRxy and status signals EIFR INPFx from the different ETLx units between the OGUy units Figure 3 24 provides a complete overview of the connections between the ETLx and the OGUz units ...

Page 274: ...13 EIFR INTF1 TR20 TR21 TR22 TR23 EIFR INTF2 TR30 TR31 TR32 TR33 EIFR INTF3 Pattern Detection Inputs Trigger Inputs TRx0 OGU1 Pattern Detection Inputs Trigger Inputs TRx1 OGU3 Pattern Detection Inputs Trigger Inputs TRx3 OGU2 Pattern Detection Inputs Trigger Inputs TRx2 ERU_IOUT3 ERU_TOUT3 ERU_PDOUT3 ERU_IOUT2 ERU_TOUT2 ERU_PDOUT2 ERU_IOUT1 ERU_TOUT1 ERU_PDOUT1 ERU_IOUT0 ERU_TOUT0 ERU_PDOUT0 ERU_G...

Page 275: ...nels that are enabled and directed to OGUy and a pattern change event if enabled are logically OR combined Pattern detection The status flags EIFR INTFx of the Input Channels can be enabled to take part in the pattern detection A pattern match is detected while all enabled status flags are set Figure 3 25 Output Gating Unit for Output Channel y Each OGUy units generates 4 output signals that are d...

Page 276: ...ed a trigger event is generated to indicate a pattern detection result event if enabled by IGCRm GEENy The trigger combination offers the possibility to program different trigger criteria for several input signals independently for each Input Channel or peripheral signals and to combine their effects to a single output e g to generate an interrupt or to start e g an ADC conversion This combination...

Page 277: ...onditions Pattern match IGCRm IGPy 10B An interrupt request is issued when a trigger event occurs while the pattern detection shows a pattern match Pattern miss IGCRm IGPy 11B An interrupt request is issued when the trigger event occurs while the pattern detection shows a pattern miss Independent of pattern detection IGCRm IGPy 01B In this mode each occurring trigger event leads to an interrupt re...

Page 278: ...tput ERU_ IOUT0 Interrupt Generation DMA channel 00 DMA channel 04 O interrupt output OGU1 Outputs ERU_ PDOUT1 not connected O pattern detection output ERU_ GOUT1 not connected O gated pattern detection output ERU_ TOUT1 not connected O trigger output ERU_ IOUT1 Interrupt Generation DMA channel 01 DMA channel 05 GPTA0 input INT1 O interrupt output OGU2 Outputs ERU_ PDOUT2 ADC gating input FADC inp...

Page 279: ...on DMA channel 02 DMA channel 06 ADC trigger input FADC input FADC_TSC GPTA0 input INT2 O interrupt output OGU3 Outputs ERU_ PDOUT3 ADC gating input FADC input FADC_GSD O pattern detection output ERU_ GOUT3 not connected O gated pattern detection output ERU_ TOUT3 not connected O trigger output ERU_ IOUT3 Interrupt Generation DMA channel 03 DMA channel 07 ADC trigger input FADC input FADC_TSD GPTA...

Page 280: ...ld determines which input line is selected for Input Channel 0 00B Input 00 is selected 01B Input 01 is selected 10B Input 02 is selected 11B Input 03 is selected FEN0 8 rw Falling Edge Enable 0 This bit determines if the falling edge of Input Channel 0 is used to set bit INTF0 0B The falling edge is not used 1B The detection of a falling edge of Input Channel 0 generates a trigger event INTF0 bec...

Page 281: ...Input Node Pointer This bit field determines the destination output channel for trigger event 0 if enabled by EIEN0 000B The event of input channel 0 triggers output channel 0 signal INT00 001B The event of input channel 0 triggers output channel 1 signal INT01 010B The event of input channel 0 triggers output channel 2 signal INT02 011B The event of input channel 0 triggers output channel 3 signa...

Page 282: ... is not used 1B The detection of a rising edge of Input Channel 1 generates a trigger event INTF1 becomes set LDEN1 26 rw Level Detection Enable 1 This bit determines if bit INTF1 is cleared automatically if an edge of the input Input Channel 1 is detected which has not been selected rising edge with REN1 0 or falling edge with FEN1 0 0B Bit INTF1 will not be cleared 1B Bit INTF1 will be cleared E...

Page 283: ...2 011B The event of input channel 1 triggers output channel 3 signal INT13 100B Reserved do not use this combination 101B Reserved do not use this combination 110B Reserved do not use this combination 111B Reserved do not use this combination 0 3 0 7 6 19 15 23 22 31 r Reserved Read as 0 should be written with 0 EICR1 External Input Channel Register 1 084H Reset Value 0000 0000H 31 30 29 28 27 26 ...

Page 284: ...EN2 9 rw Rising Edge Enable 2 This bit determines if the rising edge of signal Input Channel 2 is used to set bit INTF2 0B The rising edge is not used 1B The detection of a rising edge of Input Channel 2 generates a trigger event INTF2 becomes set LDEN2 10 rw Level Detection Enable 2 This bit determines if bit INTF2 is cleared automatically if an edge of the input Input Channel 2 is detected which...

Page 285: ...ot use this combination 111B Reserved do not use this combination EXIS3 21 20 rw External Input Selection 3 This bit field determines which input line is selected for Input Channel 3 00B Input 30 is selected 01B Input 31 is selected 10B Input 32 is selected 11B Input 33 is selected FEN3 24 rw Falling Edge Enable 3 This bit determines if the falling edge of Input Channel 3 is used to set bit INTF3 ...

Page 286: ...r event for request channel 3 e g for interrupt generation when a selected edge is detected 0B The trigger event is disabled 1B The trigger event is enabled INP3 30 28 rw Interrupt Node Pointer This bit field determines the destination output channel for trigger event 3 if enabled by EIEN3 000B The event of input channel 3 triggers output channel 0 signal INT30 001B The event of input channel 3 tr...

Page 287: ...rrupt Flag of Channel x This bit monitors the status flag of the event trigger condition for the input channel x This bit is automatically cleared when the selected condition see RENx FENx is no longer met if LDENx 1 or remains set until it is cleared by software if LDENx 0 0 31 4 r Reserved Read as 0 should be written with 0 FMR Flag Modification Register 08CH Reset Value 0000 0000H 31 30 29 28 2...

Page 288: ... for Channel x Setting this bit will clear the corresponding bit INTFx in register EIFR Reading this bit always delivers a 0 0B The bit x in register EIFR is not modified 1B The bit x in register EIFR is cleared 0 15 4 31 20 r Reserved Read as 0 should be written with 0 PDRR Pattern Detection Result Register 090H Reset Value 0000 000FH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 1...

Page 289: ...ern Enable for Channel 0 Bit IPEN0x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN0 13 rw Generate Event Enable 0 Bit GEEN0 enables the generation of a trigger ev...

Page 290: ...he pattern is not detected IPEN1x x 0 3 16 x rw Interrupt Pattern Enable for Channel 1 Bit IPEN1x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN1 29 rw Generate E...

Page 291: ...tivation of IOUT1 is only possible due to a trigger event while the pattern is detected 11B The detected pattern is taken into account An activation of IOUT1 is only possible due to a trigger event while the pattern is not detected 0 9 8 25 24 r Reserved Have to be written with 00 0 7 4 12 10 23 20 28 26 r Reserved Read as 0 should be written with 0 IGCR1 Interrupt Gating Register 1 098H Reset Val...

Page 292: ...ed during the first clock cycle when a pattern is detected or when it is no longer detected 0B The trigger generation at a change of the pattern detection result is disabled 1B The trigger generation at a change of the pattern detection result is enabled IGP2 15 14 rw Interrupt Gating Pattern 2 Bit field IGP2 determines how the pattern detection influences the output lines GOUT2 and IOUT2 00B The ...

Page 293: ...ected 0B The trigger generation at a change of the pattern detection result is disabled 1B The trigger generation at a change of the pattern detection result is enabled IGP3 31 30 rw Interrupt Gating Pattern 3 Bit field IGP3 determines how the pattern detection influences the output lines GOUT3 and IOUT3 00B The detected pattern is not taken into account An activation of IOUT3 is always possible d...

Page 294: ...uring Run Mode Idle Mode and Sleep Mode This flexibility in power management provides minimum power consumption for any application In typical operation Idle Mode and Sleep Mode may be entered and exited frequently during the run time of an application For example system software will typically cause Table 3 13 Power Management Mode Summary Mode Description Run Mode The system is fully operational...

Page 295: ...e shut off Other system components that are able to write to register PMCSR can also request the Idle Mode For example the PCPDMA controller can request Idle Mode by writing to the PMCSR register During Idle Mode memory accesses to the DMI and PMI cause these units to awaken automatically to handle the transactions When memory transactions are complete the DMI and PMI return to Idle Mode again The...

Page 296: ...on was in progress when the signal was received The unit functions are suspended Depending on bit MOD_CLC FSOE the module is either immediately stopped MOD_CLC FSOE 1 or the unit is allowed to finish ongoing operations MOD_CLC FSOE 0 before the Sleep Mode is entered For example setting MOD_CLC FSOE to 1 for a serial port will stop all actions in the serial port immediately when the sleep request i...

Page 297: ...28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PMST 0 REQSLP r rh r rwh Field Bits Type Function REQSLP 1 0 rwh Idle Mode and Sleep Mode Request 00B Normal Run Mode 01B Request Idle Mode 10B Request Sleep Mode 11B Reserved do not use this combination In Idle Mode or Sleep Mode these bits are cleared in response to an interrupt for the CPU or when bit 15 of the W...

Page 298: ...TC1784 System Control Unit SCU User s Manual 3 115 V1 1 2011 05 32 bit SCU V1 18 0 7 2 31 11 r Reserved Read as 0 should be written with 0 Field Bits Type Function ...

Page 299: ...y for Infineon internal usage not for any customer and has nothing to do with debugging If the Normal Mode was selected the next decision is which debug interface type issued for debugging for this session until the next power on event After these two decisions were made the detailed decision has to be made to define the real startup configuration Most is made via the software and can be supported...

Page 300: ...e Configuration Setting This bit field contains the value that is used by the boot software This bit field is updated in case of an Application Reset with the content by register SWRSTCON SWCFG if bit SWRSTCON SWBOOT AND RSTSTAT SW are set This bit field is updated in case of an Application Reset with the content of the latches of P0 0 to P 0 7 if bit SWRSTCON SWBOOT OR RSTSTAT SW are cleared and ...

Page 301: ...FCBAE This bit can be set by setting bit STCON SFCBAE LUDIS 17 rh Latch Update Disable 0B Bit field STSTAT HWCFG is automatically updated with the latched value of pins P0 0 to P0 7 1B Bit field STSTAT HWCFG is not updated with the latched value of pins P0 0 to P0 7 This bit can be set by setting bit SYSCON SETLUDIS EXTBEN 18 rh External Boot Enable 0B No Boot Configuration Value is fetched by the...

Page 302: ...eturns zero SFCBAE 13 w Set Flash Config Sector Access Enable Setting this bit sets bit STSTAT FCBAE Reading this bit returns always a zero Note This bit may not be set in parallel with bit CFCBAE CFCBAE 14 w Clear Flash Config Sector Access Enable Setting this bit clears bit STCON FCBAE Reading this bit returns always a zero Note This bit may not be set in parallel with bit SFCBAE STP 15 rw Start...

Page 303: ...ol Logic 3 6 1 ECC Software Testing Support This can be done for each module individually by simply disabling the ECC protection in the module change the content of a memory address enable ECC again and read the memory address again For more information see the different module chapters ecc_error MEM0 ecc_trap ECC error ECCSTAT MEM0 ECCCLR MEM0 clear set MEM1 ECC error ECCSTAT MEM1 ECCCLR MEM1 cle...

Page 304: ...ther a trap is requested if an uncorrected ECC error is detected in the LDRAM DCACHE memory 0B No ECC error trap trigger is requested 1B A ECC error trap trigger is requested ECCENDTAG 1 rw ECC Error Trap Enable for Data Cache TAG RAM Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the data cache TAG RAM memory 0B No ECC error trap trigger is reques...

Page 305: ...ror is detected in the PCP Parameter RAM 0B No ECC error trap trigger is requested 1B A ECC error trap trigger is requested ECCENCMEM 6 rw ECC Error Trap Enable for PCP Code Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the PCP Code memory 0B No ECC error trap trigger is requested 1B A ECC error trap trigger is requested ECCENCAN 7 rw ECC Error Tr...

Page 306: ... rh Field Bits Type Description LDRAM 0 rh ECC Error Flag for LDRAM and DCACHE Memory This bit indicate whether an ECC error has been detected in the LDRAM DCACHE memory 0B No ECC error detected 1B ECC error is detected DTAG 1 rh ECC Error Flag for Data Cache TAG RAM Memory This bit indicate whether an ECC error has been detected in the data TAG RAM memory 0B No ECC error detected 1B ECC error is ...

Page 307: ...dicate whether an ECC error has been detected in the Parameter RAM memory 0B No ECC error detected 1B ECC error is detected CMEM 6 rh ECC Error Flag for Code Memory This bit indicate whether an ECC error has been detected in the code memory 0B No ECC error detected 1B ECC error is detected CAN 7 rh ECC Error Flag for CAN Memory This bit indicate whether an ECC error has been detected in the CAN me...

Page 308: ...TAG 1 w Clear Data Cache TAG RAM EEC Error Status 0B No action 1B Setting this bit clears bit EECSTAT DTAG This bit always read as 0 SPRAM 2 w Clear SPRAM and ICACHE EEC Error Status 0B No action 1B Setting this bit clears bit EECSTAT SPRAM This bit always read as 0 PTAG 3 w Clear Program Cache TAG RAM EEC Error Status 0B No action 1B Setting this bit clears bit EECSTAT PTAG This bit always read a...

Page 309: ... bit EECSTAT CMEM This bit always read as 0 CAN 7 w Clear CAN Memory EEC Error Status 0B No action 1B Setting this bit clears bit EECSTAT CAN This bit always read as 0 ERAY 8 w Clear ERAY Memory EEC Error Status 0B No action 1B Setting this bit clears bit EECSTAT ERAY This bit always read as 0 0 31 9 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 310: ...000 When a measurement is started the result is available after the measurement time passed If the DTS is ready to start a measurement can be checked via bit DTSSTAT RDY If a started measurement is finished or still in progress is indicated via the status bit DTSSTAT BUSY The measurement time is also defined in the Data Sheet In order to adjust production variations bit field DTSCON CAL should be ...

Page 311: ...rw r w rw Field Bits Type Description PWD 0 rw Sensor Power Down This bit defines the DTS power state 0B The DTS is powered 1B The DTS is not powered START 1 w Sensor Measurement Start This bit starts a measurement of the DTS 0B No DTS measurement is started 1B A DTS measurement is started If set this bit is automatically cleared This bit always reads as zero CAL 23 4 rw Calibration Value This bit...

Page 312: ...e given is directly related to the die temperature Only the bit 9 2 have to be evaluated The formula for mapping the result to a temperature will follow later RDY 14 rh Sensor Ready Status This bit indicate the DTS is ready or not 0B The DTS is not ready 1B The DTS is ready BUSY 15 rh Sensor Busy Status This bit indicate the DTS is currently busy or not If the sensor is busy currently a measuremen...

Page 313: ...hat requires a password and guard bits during accesses to the WDT control register Any write access that does not deliver the correct password or the correct value for the guard bits is regarded as a malfunction of the system and a Watchdog reset is requested In addition even after a valid access has been performed and the ENDINIT bit has been cleared to provide access to the critical registers th...

Page 314: ... The TC1784 provides one more level of protection for such registers via the Endinit feature This is a highly secure write protection scheme that makes unintentional modifications of registers protected by this feature nearly impossible The Endinit feature consists of an ENDINIT bit incorporated in the WDT control register WDT_CON0 Registers protected via Endinit determine whether or not writes ar...

Page 315: ...nit protected mod_FDR All clock fractional divider registers of the individual peripheral modules are Endinit protected BTV BIV ISP Trap and interrupt vector table pointer as well as the interrupt stack pointer are Endinit protected MIECON SMACON COMPAT CPU Control Registers FLASH0_FCON FLASH0_MARP Flash configuration registers WDT_CON1 The Watchdog Timer Control Register 1 which controls the disa...

Page 316: ... to the contents SCU_ESRCFG0 SCU_ESRCFG1 All ESR control registers are protected SCU_EMSR The emergency stop register SCU_TRAPSET SCU_TRAPDIS The trap set and disable register SCU_ECCCON The ECC control register Px_ESR Px_PDR Port Control Registers DMA_MExARR DMA_MExAENR DMA_OCDSR DMA_SUSPMR DMA Control Registers PCP_CS PCP Control Registers DMI_CON DMI Control Registers Table 3 16 Password Access...

Page 317: ...ware loops or to monitor the execution sequence of routines 3 8 3 2 Modify Access to WDT_CON0 If WDT_CON0 is successfully unlocked the following write access to WDT_CON0 can modify it However this access must also meet certain requirements in order to be accepted and regarded as valid Table 3 17 lists the required bit patterns If the access does not follow these rules a Watchdog Access Error condi...

Page 318: ...N1 or WDT_SR are necessary However it is recommended that the WDT be used in an application for safety reasons For debugging support the Cerberus module can override the ENDINIT control to ease the debug flow If bit CBS_OSTATE ENIDIS is set the ENDINIT protection is disabled independent of the current status configured by the WDT If CBS_OSTATE ENIDIS is cleared the complete control is within the W...

Page 319: ...erflows Servicing is performed through a proper access sequence to the control register WDT_CON0 This enters the Time Out Mode If the WDT is not serviced before the timer overflows a system malfunction is assumed Normal Mode is terminated a WDT_NMI is requested and Prewarning Mode is entered Disable Mode Disable Mode is provided for applications which truly do not require the WDT function It can b...

Page 320: ...et Behavior WDT reset requests are generated for three cases Invalid password access to register WDT_CON0 Not finishing a password access before a timer overflow occurs in the Time Out Mode Not serving the WDT before a timer overflow occurs in the Normal Mode If a reset is generated on a WDT reset request and the kind of the reset can be configured via bit field RSTCON WDT Note The WDT itself is r...

Page 321: ...eset will result During the next Modify Access the strict requirement is that WDT_CON0 ENDINIT as well as bit 1 and bits 7 4 are written with 1 while bits 3 2 are written with 0 Note ENDINIT must be written with 1 to perform a proper service even if it is already set to 1 Changes to the reload value WDT_CON0 REL or the user definable password WDT_CON0 PW are not required However changing WDT_CON0 ...

Page 322: ...he maximum WDT period 3 8 4 4 Suspend Mode Support In an enabled and active debug session the Watchdog functionality can lead to unintended resets Therefore to avoid these resets the OCDS can control if the WDT is enabled or disabled default after Application Reset via bit CBS_OSTATE WDTSUS if it is not already stopped 3 8 5 Watchdog Timer Registers 3 8 5 1 Watchdog Timer Control Register 0 Regist...

Page 323: ...it protected registers is not permitted LCK 1 rwh Lock Bit to Control Access to WDT_CON0 0B Register WDT_CON0 is unlocked 1B Register WDT_CON0 is locked default after Application Reset The actual value of LCK is controlled by hardware It is cleared after a valid Password Access to WDT_CON0 and automatically set again after a valid Modify Access to WDT_CON0 During a write to WDT_CON0 the value writ...

Page 324: ...re Password 1 This bit field must be written with 1111B during both Password Access and Modify Access to WDT_CON0 When read these bits always return 0 PW 15 8 rw User Definable Password Field for Access to WDT_CON0 This bit field must be written with its current contents during a Password Access It can be changed during a Modify Access to WDT_CON0 REL 31 16 rw Reload Value for the WDT If the Watch...

Page 325: ...f WDT_CON0 ENDINIT is cleared The internal flag is cleared when ENDINIT is set again As long as ENDINIT is cleared the internal flag is unchanged and controls the current past error status of the WDT When ENDINIT is set again with a Valid Modify Access the internal flag is cleared together with this bit IR 2 rw Input Frequency Request Control Bit 0B Request to set input frequency to fFPI 16384 1B ...

Page 326: ...e WDT This bit can only be modified if WDT_CON0 ENDINIT is cleared WDT_SR DS is updated when ENDINIT is set again As long as ENDINIT is cleared bit WDT_SR DS controls the current enable disable status of the WDT When ENDINIT is set again with a Valid Modify Access WDT_SR DS is updated with the state of DR 0 1 31 4 r Reserved Read as 0 should be written with 0 WDT_SR WDT Status Register F000 05F8H ...

Page 327: ...as occurred This bit is set when the WDT overflows from FFFFH to 0000H This bit is only cleared when WDT_CON0 ENDINIT is set to 1 during a Valid Modify Access However it is not possible to clear this bit if the WDT is in Prewarning Mode IS 2 rh Watchdog Input Clock Status Flag 0B The timer operation clock is fFPI 16384 default after Application Reset 1B The timer operation clock is fFPI 256 This b...

Page 328: ... cleared when Time Out Mode is left PR 5 rh Watchdog Prewarning Mode Flag 0B The Watchdog is not operating in Prewarning Mode 1B The Watchdog is operating in Prewarning Mode This bit is set when a Watchdog error is detected The WDT has issued a trap trigger and is in Prewarning Mode A reset of the chip occurs after the prewarning period has expired if it is enabled in bit field RSTCON WDT TIM 31 1...

Page 329: ... The emergency stop control logic for the ports can basically operate in two modes Synchronous Mode default after reset Emergency case is activated by hardware and released by software Asynchronous Mode Emergency case is activated and released by hardware In Synchronous Mode selected by EMSR MODE 0 the port signal is sampled for a inactive to active level transition and an emergency stop flag EMSR...

Page 330: ... the port input immediately activates the emergency stop signal Of course a valid to invalid transition of the port input emergency case is released also immediately deactivates the emergency stop signal The EMSR POL bit determines the active level of the input signal The EMSR MODE bit selects Synchronous or Asynchronous Mode for emergency stop signal generation ...

Page 331: ...w rw Field Bits Type Description POL 0 rw Input Polarity This bit determines the polarity of the input line 0B Input is high active 1B Input is low active MODE 1 rw Mode Selection This bit determines the operating mode of the emergency stop signal 0B Synchronous Mode selected emergency stop is derived from the state of flag EMSF 1B Asynchronous Mode selected emergency stop is directly derived from...

Page 332: ...urred 1B An emergency stop has occurred and signal emergency stop becomes active if MODE 0 EMSFM 25 24 w Emergency Stop Flag Modification This bit field set or clear flag EMSF via software 00B EMSF remains unchanged 01B EMSF becomes set 10B EMSF becomes cleared 11B EMSF remains unchanged EMSFM is always read as 00B 0 15 3 23 17 31 26 r Reserved Read as 0 should be written with 0 Field Bits Type De...

Page 333: ...erated independently from the interrupt flag in register INTSTAT The interrupt flag can be cleared by software by writing to the corresponding bit in register INTCLR If more than one interrupt source is connected to the same interrupt node pointer in register INTNP the requests are combined to one common line Figure 3 28 Interrupt Generation int_struct O R interrupt_event A N D INTSTAT X INTNP X O...

Page 334: ...t if the WDT Prewarning Mode is entered and bit is INTDIS WDTI 0 0B No interrupt was requested since this bit was cleared the last time 1B An interrupt was requested since this bit was cleared the last time This bit can be cleared by bit INTCLR WDTI This bit can be set by bit INTSET WDTI ERUI0 1 rh ERU Channel 0 Interrupt Request Flag This bit is set if the ERU channel 0 is active and bit is INTDI...

Page 335: ...ed since this bit was cleared the last time This bit can be cleared by bit INTCLR ERUI2 This bit can be set by bit INTSET ERUI2 ERUI3 4 rh ERU Channel 3 Interrupt Request Flag This bit is set if the ERU channel 3 is active and bit is INTDIS ERUI3 0 0B No interrupt was requested since this bit was cleared the last time 1B An interrupt was requested since this bit was cleared the last time This bit ...

Page 336: ...by bit INTSET DTSI 0 6 15 8 rh Reserved Read as 0 This bit can be cleared by bit INTCLR x This bit can be set by bit INTSET x Note x 6 13 8 15 0 31 16 r Reserved Read as 0 should be written with 0 INTSET Interrupt Set Register 114H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DTSI 0 FL0I ERUI 3 ERUI 2 ERUI 1 ERUI 0 WDT I w w w w...

Page 337: ... ERUI2 Clearing this bit has no effect Reading this bit returns always zero ERUI3 4 w Set Interrupt Request Flag ERUI3 Setting this bit set bit INTSTAT ERUI3 Clearing this bit has no effect Reading this bit returns always zero FL0I 5 w Set Interrupt Request Flag FL0I Setting this bit set bit INTSTAT FL0I Clearing this bit has no effect Reading this bit returns always zero DTSI 7 w Set Interrupt Re...

Page 338: ...ting this bit clears bit INTSTAT ERUI0 Clearing this bit has no effect Reading this bit returns always zero ERUI1 2 w Clear Interrupt Request Flag ERUI1 Setting this bit clears bit INTSTAT ERUI1 Clearing this bit has no effect Reading this bit returns always zero ERUI2 3 w Clear Interrupt Request Flag ERUI2 Setting this bit clears bit INTSTAT ERUI2 Clearing this bit has no effect Reading this bit ...

Page 339: ... Register 11CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DTSI 0 FL0I ERUI 3 ERU TI2 ERUI 1 ERUI 0 WDT I rw rw rw rw rw rw rw rw rw Field Bits Type Description WDTI 0 rw Disable Interrupt Request WDT 0B An interrupt request can be generated for this source 1B No interrupt request can be generated for this source ERUI0 1 rw Dis...

Page 340: ...RUI3 4 rw Disable Interrupt Request ERU3 0B An interrupt request can be generated for this source 1B No interrupt request can be generated for this source FL0I 5 rw Disable Interrupt Request Flash 0 0B An interrupt request can be generated for this source 1B No interrupt request can be generated for this source DTSI 7 rw Disable Interrupt Request DTS 0B An interrupt request can be generated for th...

Page 341: ...01B Interrupt node 1 is selected 10B Interrupt node 2 is selected 11B Interrupt node 3 is selected ERU0 3 2 rw Interrupt Node Pointer for Interrupt ERU0 This bit field defines the interrupt node that is requested due to the set condition for bit INTSTAT ERUI0 if enabled by bit INTDIS ERUI0 00B Interrupt node 0 is selected 01B Interrupt node 1 is selected 10B Interrupt node 2 is selected 11B Interr...

Page 342: ...cted 01B Interrupt node 1 is selected 10B Interrupt node 2 is selected 11B Interrupt node 3 is selected FL0 11 10 rw Interrupt Node Pointer for Interrupt FL0 This bit field defines the interrupt node that is requested due to the set condition for bit INTSTAT FL0I if enabled by bit INTDIS FL0I 00B Interrupt node 0 is selected 01B Interrupt node 1 is selected 10B Interrupt node 2 is selected 11B Int...

Page 343: ... TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number 00H Service request is never serviced 01H Service request is on lowest priority FFH Service request is on highest priority TOS 10 rw Type of Service Control 0B CPU service is initiated 1B PCP request is initiated SRE 12 rw Service Request Enable 0B Service request is disabled 1B Service request ...

Page 344: ...05 32 bit SCU V1 18 SETR 15 w Request Set Bit SETR is required to set SRR 0B No action 1B Set SRR bit value is not stored read always returns 0 no action if CLRR is set also 0 9 8 11 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 345: ...ise only the trap status flag is set but no NMI request is generated Figure 3 29 NMI Trap Generation Handling NMI Traps As an NMI trap is generated while the trap source is enable AND the trap status flag is set it is recommended to clear the trap status flag before the trap source is enabled The trap status flag can be set before the trap source is enabled and simply enabling the trap source can ...

Page 346: ...t is set if an ESR0 event is triggered and bit is TRAPDIS ESR0T is cleared 0B No trap was requested since this bit was cleared the last time 1B A trap was requested since this bit was cleared the last time This bit can be cleared by setting bit TRAPCLR ESR0T This bit can be set by setting bit TRAPSET ESR0T ESR1T 1 rh ESR1 Trap Request Flag This bit is set if an ESR1 event is triggered and bit is T...

Page 347: ...error is indicated and bit is TRAPDIS ECCT is cleared 0B No trap was requested since this bit was cleared the last time 1B A trap was requested since this bit was cleared the last time This bit can be cleared by setting bit TRAPCLR ECCT This bit can be set by setting bit TRAPSET ECCT OSCLWDTT 5 rh OSCWDT Low Trap Request Flag This bit is set if a oscillator WDT of the PLL detects a low event and b...

Page 348: ...cillator WDT of the PLL detects a spike event and bit is TRAPDIS OSCSPWDTT cleared 0B No trap was requested since this bit was cleared the last time 1B A trap was requested since this bit was cleared the last time This bit can be cleared by setting bit TRAPCLR OSCSPWDTT This bit can be set by setting bit TRAPSET OSCSPWDTT SYSVCOLCK T 8 rh SYSVCOWDT Trap Request Flag This bit is set if a PLL VCO Lo...

Page 349: ...e last time This bit can be cleared by setting bit TRAPCLR ERAYVCOLCKT This bit can be set by setting bit TRAPSET ERAYVCOLCKT 0 2 15 10 rh Reserved Read as 0 This bit can be cleared by bit TRAPCLR x This bit can be set by bit TRAPSET x Note x 2 15 10 0 31 16 r Reserved Read as 0 TRAPSET Trap Set Register 128H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11...

Page 350: ...no effect Reading this bit returns always zero OSCLWDTT 5 w Set Trap Request Flag OSCLWDTT Setting this bit set bit TRAPSTAT OSCLWDTT Clearing this bit has no effect Reading this bit returns always zero OSCHWDTT 6 w Set Trap Request Flag OSCHWDTT Setting this bit set bit TRAPSTAT OSCHWDTT Clearing this bit has no effect Reading this bit returns always zero OSCSPWDTT 7 w Set Trap Request Flag OSCSP...

Page 351: ...ield Bits Type Description ESR0T 0 w Clear Trap Request Flag ESR0T Setting this bit clears bit TRAPSTAT ESR0T Clearing this bit has no effect Reading this bit returns always zero ESR1T 1 w Clear Trap Request Flag ESR1T Setting this bit clears bit TRAPSTAT ESR1T Clearing this bit has no effect Reading this bit returns always zero WDTT 3 w Clear Trap Request Flag WDTT Setting this bit clears bit TRA...

Page 352: ...r Trap Request Flag OSCSPWDTT Setting this bit clears bit TRAPSTAT OSCSPWDTT Clearing this bit has no effect Reading this bit returns always zero SYSVCOLCK T 8 w Clear Trap Request Flag SYSVCOLCKT Setting this bit clears bit TRAPSTAT SYSVCOLCKT Clearing this bit has no effect Reading this bit returns always zero ERAYVCOLC KT 9 w Clear Trap Request Flag ERAYVCOLCKT Setting this bit clears bit TRAPS...

Page 353: ...e generated for this source 1B No trap request can be generated for this source ESR1T 1 rw Disable Trap Request ESR1T 0B A trap request can be generated for this source 1B No trap request can be generated for this source WDTT 3 rw Disable Trap Request WDTT 0B A trap request can be generated for this source 1B No trap request can be generated for this source ECCT 4 rw Disable Trap Request ECCT 0B A...

Page 354: ...ted for this source 1B No trap request can be generated for this source SYSVCOLCK T 8 rw Disable Trap Request SYSVCOLCKT 0B A trap request can be generated for this source 1B No trap request can be generated for this source ERAYVCOLC KT 9 rw Disable Trap Request ERAYVCOLCKT 0B A trap request can be generated for this source 1B No trap request can be generated for this source 0 2 15 10 rw Reserved ...

Page 355: ...TA This feature is controlled by SYSCON GPTAIS Figure 3 30 GPTA0 LTCA2 Input IN1 Control 3 12 2 System Control Register This register controls various functionality used by the SCU but that are located outside of the module Additionally some functions for other modules are included Table 3 19 GPTA0 LTCA2 Input Line IN1 Connections SYSCON GPTAIS GPTA0 LTCA2 Input IN1 Connected to 00B P0 1 IN1 defau...

Page 356: ... input that is used for IN1 of the GPTA module For more information see either Section 3 12 1 or the GPTA chapter 00B IN0 is selected 01B IN1 is selected 10B IN2 is selected 11B IN3 is selected SETLUDIS 4 w Set Latch Update Disable Setting this bit sets bit STSTAT LUDIS Clearing this bit has no effect This bit reads always as zero SETEXTBEN 5 w Set External Boot Enable Setting this bit sets bit ST...

Page 357: ...he TC1784 Data Sheet CHID 15 8 rw Chip Identification Number This bit field defines the product by a unique number 93H 1782 EEA 16 rh Emulation Extension Available Indicates if the emulation extension is available or not 0B EEC is not available 1B EEC is available FSIZE 27 24 rw Program Flash Size this bit field indicates available program flash size for this device Detailed information is shown i...

Page 358: ...s the revision number of the TC1784 device The value of this bit field is defined in the TC1784 Data Sheet CHID 15 8 rw Chip Identification Number This bit field defines the product by a unique number 94H 1783 EEA 16 rh Emulation Extension Available Indicates if the emulation extension is available or not 0B EEC is not available 1B EEC is available FSIZE 27 24 rw Program Flash Size this bit field ...

Page 359: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHID CHREV rw r Field Bits Type Description CHREV 7 0 r Chip Revision Number This bit field indicates the revision number of the TC1784 device The value of this bit field is defined in the TC1784 Data Sheet CHID 15 8 rw Chip Identification Number This bit field defines the product by a unique number 96H 1784 EEA 16 rh Emulation Extension Available Indicates if...

Page 360: ...be written at all 0 23 17 r Reserved Read as 0 should be written with 0 ID Identification Register 008H Reset Value 0052 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MODNUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODTYPE MODREV r r Field Bits Type Description MODREV 7 0 r Module Revision Number This bit field indicates the revision number of the TC1784 module 01H first revision MODTYPE...

Page 361: ... Type Description DEPT 4 0 r Department Identification Number 00H indicates the Automotive Industrial microcontroller department within Infineon Technologies MANUF 15 5 r Manufacturer Identification Number This is a JEDEC normalized manufacturer code MANUF C1H stands for Infineon Technologies 0 31 16 r Reserved Read as 0 RTID Redesign Tracing Identification Register 148H Reset Value 0000 XXXXH 31 ...

Page 362: ...0B No change indicated 1B A change has been made without changing bit field CHIPID CHREV RTx can be used e g for minor redesign stepping identification purposes 0 31 16 r Reserved Read as 0 Table 3 20 Register Overview of SCU Short Name Long Name Offset Addr 1 Access Mode Reset Description See Read Write Reserved 000H 004H BE BE ID Identification Register 008H U SV BE System Reset Page 3 177 Reser...

Page 363: ...m Reset Page 3 47 EXTCON External Clock Control Register 03CH U SV U SV System Reset Page 3 45 SYSCON System Control Register 040H U SV U SV System Reset Page 3 173 Reserved 044H 04CH BE BE RSTSTAT Reset Status Register 050H U SV BE Power on Reset Page 3 69 RSTCNTC ON Reset Counter Control Register 054H U SV SV E Power on Reset Page 3 72 RSTCON Reset CON Register 058H U SV SV E Power on Reset Page...

Page 364: ...R Flag Modification Register 08CH U SV U SV Application Reset Page 3 104 PDRR Pattern Detection Result Register 090H U SV U SV Application Reset Page 3 105 IGCR0 Interrupt Gating Register 0 094H U SV U SV Application Reset Page 3 106 IGCR1 Interrupt Gating Register 1 098H U SV U SV Application Reset Page 3 108 Reserved 09CH BE BE IOCR Input Output Control Register 0A0H U SV U SV System Reset Page ...

Page 365: ...0D4H U SV BE Application Reset Page 3 123 ECCCLR ECC Clear Register 0D8H U SV U SV Application Reset Page 3 125 DTSSTAT Die Temperature Sensor Status Register 0E0H U SV BE Application Reset Page 3 129 DTSCON Die Temperature Sensor Control Register 0E4H U SV U SV Application Reset Page 3 128 Reserved 0E8H 0ECH BE BE WDT_ CON0 WDT Control Register 0 0F0H U SV U SV Application Reset Page 3 140 WDT_ C...

Page 366: ...er 120H U SV U SV Application Reset Page 3 158 TRAPSTA T Trap Status Register 124H U SV BE System Reset Page 3 163 TRAPSET Trap Set Register 128H U SV SV E System Reset Page 3 166 TRAPCLR Trap Clear Register 12CH U SV U SV System Reset Page 3 168 TRAPDIS Trap Disable Register 130H U SV SV E Application Reset Page 3 170 Reserved 134H 13FH BE BE CHIPID Chip Identification Register 140H U SV ST Syste...

Page 367: ...plication Reset Page 3 160 SRC1 Service Request Control Register 1 1F8H U SV SV Application Reset Page 3 160 SRC0 Service Request Control Register 0 1FCH U SV SV Application Reset Page 3 160 1 The absolute register address is calculated as follows Module Base Address Offset Address shown in this column Table 3 20 Register Overview of SCU Short Name Long Name Offset Addr 1 Access Mode Reset Descrip...

Page 368: ...em Control Unit SCU User s Manual 3 185 V1 1 2011 05 32 bit SCU V1 18 3 12 5 SCU Address Area Table 3 21 Registers Address Space SCU Kernel Registers Module Base Address End Address Note SCU F000 0500H F000 06FFH ...

Page 369: ...he LFI Bridge Floating Point Unit FPU TriCore TM CPU DMI 124 KB LDRAM 4 KB DCACHE Configurable LDRAM Local Data RAM SPRAM Scratch Pad RAM ICACHE Instruction Cache OVRAM Overlay RAM PMI 24 KB SPRAM 16 KB ICACHE Configurable CPU Slave Interface CPS LMB Local Memory Bus System Peripheral Bus SPB MCB06068 PFlash Program Memory Flash DFlash Data Memory Flash BROM Boot ROM Test ROM To Emulation Memory E...

Page 370: ...ons on the LMB bus The DMA does not forward directly transactions from the FPI bus to the LMB bus or vice versa no LMB FPI bridge functionality Further DMA details and or DMA changes compared to AudoNG can be found in the DMA chapter The DMA module is now able to access the LMB SPB bus with three priorities see Page 4 6 and Page 4 26 Priority of DMA access is controlled by the OCDS for DMA OCDS ac...

Page 371: ... bit data transactions 4 2 2 Transaction Types There are three transaction types of the LMB 4 2 2 1 Single Transfers Single transfers are all transactions that are initiated by any instruction code or data of the TriCore 1 CPU and that require a system resource which is not part of the TriCore 1 PMI or DMI The only exceptions are the following instructions LDMST ST T and SWAP W generate atomic tra...

Page 372: ...he address alignment of an LMB transfer 1 Byte accesses must always be located on byte address boundaries 2 Half word accesses must be aligned to addresses with address line A0 0 3 Word accesses must be aligned to addresses with address lines A 1 0 00B 4 Double word accesses must be aligned to addresses with address lines A 2 0 000B 5 Block transfers must be aligned identical as double word addres...

Page 373: ...he LMB which is read by the LMB slave write cycle or vice versa read cycle Transfers 2 and 3 show the conflict when two masters try to use the LMB and how the conflict is resolved In the example the LMB master of transfer 2 has a higher priority than the LMB master of transfer 3 During a block transfer the address cycle of a second transfer is extended until the data cycles of the block transfer a...

Page 374: ...le that precedes a possible address cycle Each LMB master device has a fixed priority as shown in Table 4 2 For all the masters requesting the LMB during any one cycle the granted master is the one with the highest priority Table 4 2 Priority of Master LMB Agents Priority LMB Master Comment Highest Lowest DMA high priority DMA Requests from modules Cerberus high priority1 DMA channels with high pr...

Page 375: ...captured and stored in the following registers The LMB Error Address Register LEADDR stores the LMB address that has been captured during the last erroneous LMB transaction The LMB Error Data Registers LEDATL LEDATH stores the LMB data bus information that has been captured during the last erroneous LMB transaction The LMB Error Attribute Register LEATT stores status information of the bus error e...

Page 376: ...s Space Module Base Address End Address Note LBCU F87F FE00H F87F FEFFH Table 4 4 Registers Overview LBCU Module Control Registers Short Name Description Offset Addr 1 Access Mode Reset Class Description See Read Write Reserved 000H 004H BE BE LBCU_ID LBCU Module Identification Register 008H U SV BE Page 4 10 Reserved 00CH 01CH BE BE LBCU_LE ATT LBCU LMB Error Attribute Register 020H U SV 32 SV 32...

Page 377: ...ster 02CH U SV BE 3 Page 4 14 Reserved 030H 0F8H BE BE LBCU_SR C LBCU Service Request Control Register 0FCH U SV 32 SV 32 3 Page 4 15 1 The absolute register address is calculated as follows Module Base Address Table 4 3 Offset Address shown in this column Table 4 4 Registers Overview LBCU Module Control Registers Short Name Description Offset Addr 1 Access Mode Reset Class Description See Read Wr...

Page 378: ...Reset Value 000F C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type The bit field is set to C0H which defines the module...

Page 379: ...l be captured 1B The error capture mechanism is locked The registers LEADDR and bits 31 4 of LEATT contain valid data The registers LEADTL and LEDATH contain valid data if LEATT UIS 0 LEC is automatically set when an LMB bus error has been captured Any further LMB bus error is not captured if LEC 1 When writing a 1 to LEC the error capture mechanism becomes unlocked and is ready for the next LMB b...

Page 380: ...her the LMB bus error occurred by an un implemented address 0B LMB slave address is valid 1B Invalid LMB slave address occurred SVM 21 rh LMB Bus Supervisor Mode This bit indicates whether the LMB bus error occurred in Supervisor Mode or in User Mode 0B Transfer was initiated in Supervisor Mode 1B Transfer was initiated in User Mode WR 22 rh LMB Bus Write Error Indication This bit indicates whethe...

Page 381: ...are reserved 0 3 1 13 8 20 27 r Reserved Read as 0 should be written with 0 1 Pls note that this bit field represents bit 0 2 of the master TAG as shown in Table 4 15 This as bit 3 of the On Chip Bus master TAGs is always 0 for master interfaces connected to the LMB Bus Table 4 5 LMB Bus Read Write Error Indication RD WR LMB Bus Cycle 0 0 LMB bus error occurred at the read cycle of an atomic trans...

Page 382: ...ing register LEATT is set LBCU_LEDATL LBCU LMB Error Data Low Register 028H Reset Value XXXX XXXXH 31 0 LEDAT 31 0 rh Field Bits Type Description LEDAT 31 0 31 0 rh LMB Bus Address Bits 31 0 This bit field holds the lower 32 bit part of the 64 bit LMB data that has been captured at an LMB bus error LEDAT 31 0 only contains valid read data when bit LEC in the corresponding register LEATT is set LBC...

Page 383: ...equest Control Register 0FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE TOS 0 SRPN w w rh rw r r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 11 10 r Type of Service State Always read as 00B This means type of service is associated with interrupt bus 0 CPU interrupt arbitrati...

Page 384: ... or the PCP via the LFI Bridge that address an LMB slave device are translated into an LMB address according to Table 4 6 Bus Errors at Writes via the LFI Bridge When a write operation has been initiated and directed to the LFI Bridge by an SPB bus master the LFI Bridge handles the write transaction at the LMB autonomously If the write operation at the LMB results in a bus error the LBCU detects t...

Page 385: ...s and Bus Bridges User s Manual 4 17 V1 1 2011 05 Buses V1 9 Note that this behavior occurs only at write operations via the LFI Bridge It can also be triggered by an erroneous write cycle of a read modify write bus transaction ...

Page 386: ...ss End Address Note LFI F87F FF00H F87F FFFFH Table 4 8 Registers Overview LFI Bridge Module Control Registers Short Name Description Offset Addr 1 1 The absolute register address is calculated as follows Module Base Address Table 4 7 Offset Address shown in this column Access Mode Reset Class Description See Read Write Reserved 000H 004H BE BE LFI_ID LFI Module Identification Register 008H U SV B...

Page 387: ...e Identification Register 008H Reset Value 000C C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type The bit field is set ...

Page 388: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FTAG 0 LTAG 0 0 r rh r rh r rw Field Bits Type Description 0 0 rw Reserved Returns 0 if read must be written with 0 LTAG 6 4 rh LMB Bus Tag ID In the TC1784 the bit field LTAG 000B FTAG 11 8 rh FPI Bus SPB Tag ID In the TC1784 the bit field FTAG 1011B which reflects the tag number of the LFI Bridge on the SPB 0 3 1 7 31 12 r Reserved Returns 0 if read must be writ...

Page 389: ... bandwidth Additional features of the FPI Bus include Optimized for high speed and high performance Support of multiple bus masters and pipelined transactions 32 bit wide address and data buses 8 16 and 32 bit data transfers 64 128 and 256 bit block transfers Central simple per cycle arbitration Slave controlled wait state insertion Support of atomic operations LDMST ST T and SWAP W The functional...

Page 390: ...I Bus In the TC1784 DMI and PMI via the LFI Bridge PCP and DMA including Cerberus and MLI s operate as FPI Bus masters On chip peripheral units are typically FPI Bus slaves FPI Bus arbitration is performed by the Bus Control Unit SBCU of the FPI Bus In case of bus errors the SBCU generates an interrupt request to the CPU and provides debugging information about the actual bus error to the CPU ...

Page 391: ...block transfer transaction on the FPI Bus Atomic Transfers Atomic transfers are generated by LDMST ST T and SWAP W instructions that require two single transfers The read and write transfer of an atomic transfer are always locked and cannot be interrupted by another bus masters Atomic transfers are also referenced as read modify write transfers Note See also Table 4 11 for available FPI Bus transf...

Page 392: ...controller 2 Address Cycle After the request grant cycle the master puts the address on the FPI Bus and all FPI Bus slave devices check whether they are addressed for the following data cycle 3 Data Cycle In the data cycle either the master puts write data on the FPI Bus which is read by the FPI Bus slave write cycle or vice versa read cycle Transfers 2 and 3 show the conflict when two master try ...

Page 393: ...User s Manual 4 25 V1 1 2011 05 Buses V1 9 Figure 4 7 FPI Bus Block Transactions Request Grant Data Cycle Address Cycle Bus Cycle 1 2 3 4 Request Grant Address Cycle 5 MCA06110 Transfer 1 Transfer 2 6 Data Cycle 7 Data Cycle Data Cycle Data Cycle ...

Page 394: ...rbitration priority as shown in Table 4 9 DMA controller agent can be assigned to low medium or high priority by software via DMA Channel and OCDS control registers Table 4 9 Priority of TC1784 SPB Bus Agents Priority Agent Comment highest lowest Any bus requestor meeting the starvation protection criteria is assigned this priority Highest priority used only for starvation protection DMA high prio...

Page 395: ... System Buses and Bus Bridges User s Manual 4 27 V1 1 2011 05 Buses V1 9 If there is no request from an SPB bus master the SPB is granted to a default master LFI Bridge or PCP which has been at last the active master ...

Page 396: ...est flag was set a starvation event happened This master will now be set to the highest priority and will be granted service If there are several masters to which this starvation condition applies they are served in the order of their hard wired priority ranking If a master that is processing its transaction under starvation condition is retried its corresponding request flag is automatically agai...

Page 397: ...and SBCU_EDAT respectively are self explanatory the captured FPI Bus control information needs some more explanation Register SBCU_ECON captures the state of the read RDN write WRN Supervisor Mode SVM acknowledge ACK ready RDY abort ABT time out TOUT bus master identification lines TAG and transaction operation code OPC lines of the FPI Bus The SVM signal is set to 1 for an access in Supervisor Mo...

Page 398: ...le 4 11 FPI Bus Operation Codes OPC OPC Description 0000B Single Byte Transfer 8 bit 0001B Single Half Word Transfer 16 bit 0010B Single Word Transfer 32 bit 0100B 2 Word Block Transfer 0101B 4 Word Block Transfer 0110B 8 Word Block Transfer 1111 No operation 0011B 0111B 1000B 1110B Reserved ...

Page 399: ... Address triggers Signal triggers Grant triggers 4 6 3 1 Address Triggers The address debug trigger event conditions are defined by the contents of the SBCU_DBADR1 SBCU_DBADR2 and SBCU_DBCNTL registers A wide range of possibilities arise for the creation of debug trigger events based on addresses The following debug trigger events can be selected Match on one signal address Match on one of two sig...

Page 400: ...nations are Match on a single signal status Match on a multiple signal status With the multiple signal match conditions all single signal match conditions are combined with a logical AND to the signal status debug trigger event signal The selection whether or not a single match condition is selected can be enabled disabled selectively for each condition via the SBCU_DBCNTL ONBOSx bits Figure 4 9 S...

Page 401: ...n be configured Only the enabled masters in the SBCU_DBGRNT register are of interest for the grant debug trigger event condition The grant debug trigger event condition can be enabled disabled via bit SBCU_DBCNTL ONG see Figure 4 10 Figure 4 10 Grant Trigger Generation MCA06116 Grant Trigger 1 SBCU_DBGRNT DMA M LFI DMA L PCP DMA H SBCU_DBCNTL ONG DMAisgrantedasbus master lowpriority LFIBridgeisgra...

Page 402: ... a BCU debug trigger event on any SPB write access to address 00002004H or 000020A0H by SPB master of the LFI Bridge or the PCP For this task the following programming settings for the BCU breakpoint logic must be executed 1 Writing SBCU_DBADR1 0000 2004H 2 Writing SBCU_DBADR2 0000 20A0H 3 Writing SBCU_DBCNTL C1115010H a ONBOS 3 0 1100B means that no signal status trigger is generated disabled for...

Page 403: ... 1 Writing SBCU_DBADR1 01FFFFFFH 2 Writing SBCU_DBADR2 02FFFFFFH 3 Writing SBCU_DBCNTL 32206010H a ONBOS 3 0 0011B means that the signal status trigger is disabled for a read or for write signal status match but enabled for Supervisor Mode match AND opcode match conditions according to the settings of bit SVM and bit field OPC in register SBCU_DBBOS b ONA2 10B means that the address 2 trigger is g...

Page 404: ...ode b ONA2 00B means that no address 2 trigger is generated c ONA1 10B means that the address 1 trigger is generated if the FPI Bus address is greater or equal to SBCU_DBADR1 d ONG 1 means that the grant debug trigger is enabled e CONCOM 2 0 101B means that the address trigger is created by address trigger 1 OR address trigger 2 CONCOM1 0 and that the grant trigger is AND ed with the address trigg...

Page 405: ...01FFH Table 4 13 Registers Overview SBCU Control Registers Short Name Description Offset Addr 1 Access Mode Reset Class Description See Read Write Reserved 000H 004H BE BE SBCU_ID SBCU Module Identification Register 008H U SV BE Page 4 39 Reserved 00CH BE BE SBCU_ CON SBCU Control Register 010H U SV SV 3 Page 4 40 Reserved 014H 01CH BE BE 3 SBCU_reg_its SBCU_CON Control Registers Interrupt Registe...

Page 406: ...3CH U SV SV 1 Page 4 50 SBCU_ DBBOS SBCU Debug Bus Operation Signals Register 040H U SV SV 1 Page 4 50 SBCU_ DBGNTT SBCU Debug Trapped Master Register 044H U SV BE 1 Page 4 52 SBCU_ DBADRT SBCU Debug Trapped Address Register 048H U SV BE 1 Page 4 54 SBCU_ DBBOST SBCU Debug Trapped Bus Operation Signals Register 04CH U SV BE 1 Page 4 54 SBCU_ DBDAT SBCU Debug Data Status Register 050H U SV BE 1 Pag...

Page 407: ...ion Register 008H Reset Value 0000 6AXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MOD_NUMBER 15 8 r Module Number Value This bit field defines a...

Page 408: ...8 7 6 5 4 3 2 1 0 TOUT rw Field Bits Type Description TOUT 15 0 rw SBCU Bus Time Out Value The bit field determines the number of System Peripheral Bus time out cycles Default after reset is FFFFH 65536 bus cycles DBG 16 rw SBCU Debug Trace Enable 0B SBCU debug trace disabled 1B SBCU debug trace enabled default after reset SPE 19 rw SBCU Starvation Protection Enable 0B SBCU starvation protection d...

Page 409: ...or conditions is disabled SBCU_CON DBG 0 the SBCU error capture registers remain untouched Note The SBCU error capture registers store only the parameters of the first error In case of multiple bus errors an error counter SBCU_ECON ERRCNT shows the number of bus errors since the first error occurred An application reset clears this bit field to zero but the counter can be set to any value through ...

Page 410: ...wh State of FPI Bus Abort Signal This bit indicates the state of the abort signal at an FBI Bus error 0B Master has aborted an FPI Bus transfer Abort signal was active 1B Abort signal was inactive ACK 20 19 rwh State of FPI Bus Acknowledge Signals This bit field indicates the acknowledge code that has been output by the selected slave at an FPI Bus error Coding see Table 4 10 SVM 21 rwh State of F...

Page 411: ... Indication RD WR FPI Bus Cycle 0 0 FPI Bus error occurred at the read transfer of a read modify write transfer 0 1 FPI Bus error occurred at a read cycle of a single transfer 1 0 FPI Bus error occurred at a write cycle of a single transfer or at the write cycle of a read modify write transfer 1 1 Does not occur SBCU_EADD SBCU Error Address Capture Register 024H Reset Value 0000 0000H 31 0 FPIADR ...

Page 412: ...ta Capture Register 028H Reset Value 0000 0000H 31 0 FPIDAT rwh Field Bits Type Description FPIDAT 31 0 rwh Captured FPI Bus Address This bit field holds the 32 bit FPI Bus data that has been captured at an FPI Bus error Note that if multiple bus errors occurred only the data of the first bus error is captured ...

Page 413: ...Bits Type Description EO 0 r Status of SBCU Debug Support Enable This bit is controlled by the Cerberus and enables the SBCU debug support 0B SBCU debug support is disabled 1B SBCU debug support is enabled default after reset OA 1 r Status of SBCU Breakpoint Logic 0B The SBCU breakpoint logic is disarmed Any further breakpoint activation is discarded 1B The SBCU breakpoint logic is armed The OA bi...

Page 414: ... address trigger condition for further control see Figure 4 11 CONCOM2 14 rw Address and Signal Trigger Relation 0B Address trigger condition see CONCOM1 and signal status trigger conditions are combined with a logical OR for further control 1B Address phase trigger condition see CONCOM1 and the signal status trigger conditions are combined with a logical AND for further control see Figure 4 11 ON...

Page 415: ... in DBBOS OPC see Figure 4 9 ONBOS1 29 rw Supervisor Mode Signal Trigger Condition 0B The signal status trigger generation for the FPI Bus Supervisor Mode signal is disabled 1B A signal status trigger is generated if the FPI Bus Supervisor Mode signal state is equal to the value of DBBOS SVM see Figure 4 9 ONBOS2 30 rw Write Signal Trigger Condition 0B The signal status trigger generation for the ...

Page 416: ...w Cerberus Grant Trigger Enable High Priority1 0B FPI Bus transactions with high priority DMA as bus master are enabled for grant trigger event generation 1B FPI Bus transactions with high priority DMA as bus master are disabled for grant trigger event generation ONE ONE 2 1 15 7 rw Reserved Read as 1 after reset reading these bits will return the value last written PCP 3 rw PCP Grant Trigger Enab...

Page 417: ...er are disabled for grant trigger event generation DMAL 6 rw DMA Grant Trigger Enable Low Priority3 0B FPI Bus transactions with low priority DMA channels as bus master are enabled for grant trigger event generation 1B FPI Bus transactions with low priority DMA channels as bus master are disabled for grant trigger event generation 0 31 16 r Reserved Read as 0 should be written with 0 1 Including D...

Page 418: ...BCU_DBADR2 SBCU Debug Address 2 Register 03CH Reset Value 0000 0000H 31 0 ADR2 rw Field Bits Type Description ADR2 31 0 rw Debug Trigger Address 2 This register contains the address for the address 2 trigger event generation SBCU_DBBOS SBCU Debug Bus Operation Signals Register 040H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RD...

Page 419: ...or Status Debug Trigger This bit determines the mode of an FPI Bus transaction for which a signal status debug trigger event is generated if enabled by DBCNTL ONBOS1 1 0B Trigger on User Mode selected 1B Trigger on Supervisor Mode selected WR 8 rw Write Signal for Status Debug Trigger This bit determines the state of the WR signal of an FPI Bus transaction for which a signal status debug trigger e...

Page 420: ...2 1 0 ONE DMA L LFI DMA M PCP ONE DMA H r rh rh rh rh r rh Field Bits Type Description DMAH 0 rh High Priority DMA FPI Bus Master Status1 This bit indicates whether the DMA with a high priority request was FPI Bus master when the break trigger event occurred 0B The high priority DMA was not the FPI bus master 1B The high priority DMA was the FPI Bus master PCP 3 rh PCP FPI Bus Master Status This b...

Page 421: ...th a low priority request was the FPI Bus master when the break trigger event occurred 0B The low priority DMA was not the FPI Bus master 1B The low priority DMA was the FPI Bus master CHNR0y y 0 7 16 y rh DMA Channel Number Status These bits indicate which DMA channel with number 0y was active when a DMA break trigger event occurred 0B DMA channel 0y was not active at a DMA break trigger event 1B...

Page 422: ...s Address Status This register contains the FPI Bus address that was captured when the OCDS break trigger event occurred SBCU_DBBOST SBCU Debug Trapped Bus Operation Signals Register 04CH Reset Value 0000 3180H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 FPI TAG r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FPI T OUT FPI ABO RT FPI RD FPI OPS FPI RST FPI WR FPI RDY FPI ACK FPI SVM FPI OPC r r...

Page 423: ...mbinations are reserved FPISVM 4 rh FPI Bus Supervisor Mode Status This bit indicates the state of the Supervisor Mode signal captured from the FPI Bus signal lines when the BCU break trigger event occurred 0B User mode 1B Supervisor mode FPIACK 6 5 rh FPI Bus Acknowledge Status This bit field indicates the acknowledge signal status captured from the FPI Bus signal lines when the BCU break trigger...

Page 424: ...aptured from the FPI Bus signal lines when the BCU break trigger event occurred 0B No OCDS suspend request is pending 1B An OCDS suspend request is pending FPIRD 12 rh FPI Bus Read Indication Status This bit indicates the read signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred 0B Single read transfer or read cycle of an atomic transfer 1B No operation or...

Page 425: ...ed see Table 4 15 The master TAG identifies the master of the transfer which generated BCU break trigger event 0 15 31 20 rh Reserved Read as 0 should be written with 0 SBCU_DBDAT SBCU Debug Data Status Register 050H Reset Value 0000 0000H 31 0 FPIDATA rh Field Bits Type Description FPIDATA 31 0 rh FPI Bus Data Status This register contains the FPI Bus data that was captured when the OCDS break tr...

Page 426: ...bed in the Interrupt Chapter of this TC1784 User s Manual SBCU_SRC SBCU Service Request Control Register 0FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control 0B CPU service is ...

Page 427: ... bit field in the register LBCU_LEATT on Page 4 11 represents only bit 0 2 of the TAG Number as the TAG number of all On Chip Bus master interfaces connected to LMB is 0 Table 4 15 On Chip Bus Master TAG Assignments TAG Number Module Location Description 0000B LFI LMB LFI Master Interface to LMB 0001B Reserved 0010B PMI LMB Program Memory Interface 0011B Reserved 0100B DMI LMB Data Memory Interfac...

Page 428: ...The Flash command and fetch control interface for Program Flash and Data Flash The Overlay RAM interface with Online Data Acquisition OLDA support The Boot ROM interface The Emulation Memory interface The Local Memory Bus LMB slave interface Following memories are controlled by and belong to the PMU0 2 5 Mbyte of Program Flash memory PFLASH 128 Kbyte of Data Flash memory DFLASH It can represent up...

Page 429: ... 5 1 PMU0 Basic Block Diagram PMU0 PMU0_BasicBlockDiag _generic PMU Control Overlay RAM Interface Emulation Memory ED chip only Flash Interface Module DFLASH PFLASH 64 ROM Control BROM 64 Emulation Memory Interface OVRAM 64 To From Local Memory Bus LMB Interface Slave 64 64 64 64 ...

Page 430: ...procedure is stored and started Another start location after reset is not supported guaranteeing that always the only one startup firmware within the BootROM is executed after reset 5 1 2 Firmware Program Structure The different sections of the firmware in BootROM provide startup and boot operations after reset such as The startup SW which is the main control firmware in the BootROM executed after...

Page 431: ...e any read access is performed Also byte or half word write accesses to the OVRAM may result in ECC error detection due to read modify write if the memory has not been initialized before the access1 An ECC error is reported to the SCU for control of error indication and of NMI trap disabled after reset 5 2 2 Online Data Acquisition OLDA Calibration is additionally supported by an OLDA memory range...

Page 432: ...M Control register OVRCON Bit protection allows independent control of OLDA and ECC function Write accesses to this register are permitted only in Supervisor Mode SV read accesses in User Mode or SV The OVRCON register is cleared with the application class 3 reset The SCU controls if detected ECC errors trigger an NMI trap The register is defined as follows PMU0_OVRCON Overlay RAM Control Register...

Page 433: ...s to the OVRAM use an ECC calculated from the data 1B Write accesses to the OVRAM use the content of OVRCON ECCW instead of generating an ECC from the data DBERINTDIS 13 rw ECC Double Bit Error Interrupt Disable 0B Double bit errors are reported to the SCU for NMI triggering and to the redundancy wrapper 1B Double bit errors are not reported to the SCU and to the redundancy wrapper ECCDBER 15 rwh ...

Page 434: ...1784 production device the EMEM interface is always disabled A CPU read access from the Emulation Memory region causes a DSE trap and an LMB bus error If the Emulation Memory region read access is initiated by a SPB master e g PCP additionally a SPB error interrupt is generated Per default write accesses to the Emulation Memory by any master cause an LMB bus error trap in production device In the ...

Page 435: ...egister F800 0508H Reset Value 0060 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number MOD_REV defines the module revision number The value of a module revision starts with 01H first rev MOD_TYPE 15 8 r Module Type This bit field is C0H It defines the module a...

Page 436: ...e special tuning protection support represents a security function provided additionally to Flash read write OTP protection see Page 5 21 and Chapter 5 6 5 and additionally to the Alternate Boot Mode see BootROM spec For details on the tuning protection please contact your Infineon representative ...

Page 437: ...for Program Flash with buffer hit control and a separate read buffer for Data Flash Single cycle burst transfers of up to 4 double words and sequential prefetching with control of prefetch hit are additionally supported for Program Flash Accesses to Data Flash do not disturb buffered data and prefetched data in Program Flash for hit control The minimum programming width is one page consisting of 2...

Page 438: ...ockable for protection against erase and program write protection One additional configuration sector not accessible to the user Read protection for whole Flash Combined with whole Flash write protection thus supporting protection against Trojan horse programs Multi level sector write protection with support of re programmability one level dedicated to OTP protection with ROM functionality locked ...

Page 439: ...KB sector Operating lifetime incl Retention 20 years with endurance 1000 For further operating conditions see data sheet Summary of Data Flash Features and Functions 128 Kbyte on chip Flash configured in two independent Flash banks of equal size Sector architecture one sector per bank 64 bit read interface Erase program one bank while data read access from the other bank Programming one bank while...

Page 440: ...am Memory Unit PMU User s Manual 5 13 V1 1 2011 05 PMU V1 47 Other characteristics Same as Program Flash 1 This number of cycles requires a specific robust EEPROM emulation algorithm as described in Section 5 6 6 3 ...

Page 441: ...ddresses Sector Partitioning in Program Flash The Program Flash memory is divided into the following sectors Eight 16 Kbyte logical sectors together building two 64 Kbyte physical sectors one 128 Kbyte physical sector and nine 256 Kbyte physical sectors Additionally a configuration sector is implemented which is not user accessible Physical and Logical Sectors The maximum number of program erase c...

Page 442: ...EPROM In this context the main difference between a Flash memory and an EEPROM is the endurance combined with a shorter retention For EEPROM an endurance of e g 120 000 write erase cycles is required what is not supported with the standard Flash memory For EEPROM emulation and thus for increasing the endurance the Data Flash is used like a circular buffer memory The newest data updates are program...

Page 443: ...ntered all active regions are copied into the new bank so that the old DFLASH bank can be erased It is recommended to delay the copy and erase operation so that more active regions in the old bank are renewed updated in the new bank anyway Depending on the number of pages used for dynamic programming of EEPROM data the endurance of an EEPROM region can additionally be optimized If only that part o...

Page 444: ...double word read data is selected by the CPU The Flash addresses are mapped into the total address space of the controller with different base addresses see Address Mapping on Page 5 26 The physical address range of the 24 Kbyte configuration sector starts also with address zero and it is mapped to the same base address as the Program Flash but read and direct write accesses to the config sector a...

Page 445: ...hat writes command sequences to the Data Flash can be located in and executed from the Program Flash Note The write cycles belonging to a command sequence may be buffered on its way to the Flash in store write buffers To maintain data coherency strictly in order sequence of command cycles is mandatory and to guarantee immediate transfer of the command cycles to the PMU all write cycles to the Flas...

Page 446: ...he old contents of the assembly buffer for several page write operations if always the Enter Page Mode command is directly followed by the Write Page command Command cycles addressing a busy Flash bank cause a stall of the bus system and the sending master until the busy clears After receiving the Write Page command the module executes the program operation The page of 256 Data Flash 128 bytes is ...

Page 447: ...n also the sector erase operation includes an erase quality check that identifies incorrectly erased bits in the Flash sector and that indicates a verification error if weak bits can no more be corrected see Chapter 5 6 6 3 An erase operation is executed within max 5 s Data Flash 2 5 s but depending on sector size and on CPU frequency In Data Flash an automatic erase suspend function is implemente...

Page 448: ...s enabled in this case because the Flash module itself disables code and data accesses In case of start after reset from internal Flash Flash accesses are enabled but the debug interface is locked by the firmware in BootROM and the user himself has to control the debug interface In any case the Flash user can control by himself the access rights for instructions and data and for different masters ...

Page 449: ...et ROM functionality in UCB2 If any protection is configured and confirmed thus installed correctly this state is indicated in the Flash Status Register FSR Additionally protection summary bits are provided in FSR for every user indicating the installation of read protection only user 0 or and write protection and for indication of a temporarily disabled state user 0 and 1 The locked state of ever...

Page 450: ...only then the power down state is taken The wakeup from sleep ramps up the voltage generators before the Flash read mode is activated again Its duration is documented in the data sheet Additionally the PMU Flash module supports a dynamic power reduction mode where idle states are used to disable the wordline drivers If this mode is enabled the prefetch functionality is simplified ...

Page 451: ...tic prefetching the defined number of wait states in FCON register is disabled and the access is performed without wait state thus with 0 ns access time buffer hit In case of prefetch line hit the number of access cycles is reduced to 1 wait state if the prefetched read data line is already pending before the read buffer Table 5 1 Selection of Wait States in Relation to Operating Frequency for Fla...

Page 452: ...sh and to the Data Flash are not supported The accesses are serialized on LMB bus and thus also on the Flash array interface Therefore a burst transfer from PFlash cannot be interrupted by a DFlash cycle If a DFlash request is received during prefetching the PFlash the prefetch access is aborted and the DFlash access is immediately started Prefetched data or code is only inhibited and prefetching ...

Page 453: ...es and in segment 8H for cached accesses Thus the segment address bits are A31 A28 8H for all cached Flash accesses and A31 A28 AH for all non cached Flash accesses Note Data accesses to Overlay Memory shall only be performed in the non cached address space to bypass the cache line buffer in the DMI module necessary for data consistency after write Note Command sequence cycles to the Flash shall b...

Page 454: ...a Flash cached space DFlash bank 0 DFlash bank 1 128 Kbyte 64 KB 64 KB 8FE0 0000H 8FE1 0000H Data Access via LMB 2x64 bit into DMI cache no burst no prefetch Program Flash non cached 2 5 Mbyte AH A000 0000H Instr Access via LMB 4x64 bit into PMI Line Buffer with prefetch Data Access via LMB 1x64 bit DMI line buffer bypassed with prefetch Data Flash non cached DFlash bank 0 DFlash bank 1 128 Kbyte ...

Page 455: ... chapter Operation Hints and Guidelines on Page 5 86 In general the command mode remains active during the whole command execution also indicated by the busy bits in the status register Those command sequences which do not affect the Flash array e g the Enter Page Mode command or the Clear Status command are immediately executed and are therefore not visible through the busy status bit The command...

Page 456: ...U V1 47 UCPA User configuration page address SA Sector address base address of sector to be erased UCBA User configuration block address base address of the 1 Kbyte UC block UL User protection level the command user level is zero master user or one PW 32 bit password ...

Page 457: ...are shown as right bounded bytes in 32 bit words however their position on the 64 bit data bus is defined by address bit A2 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle Reset to Read Address Data 5554 xxF0 Enter Page Mode Address Data 5554 xx5y Load Page 3 Address Data 55F0 WD Write Page 4 5 Address Data 5554 xxAA AAA8 xx55 5554 xxA0 PA xxAA Write UC Page 5 Address Data 5554 xxAA AAA8 xx55 5554...

Page 458: ...d for load DW 64 bit operations and for load word 32 bit operations with word transfer on even half of 64 bit bus In case of word transfers for every second word the address has to be 55F4H because the word is transferred on the high half of the 64 bit data bus A2 1 In case of completely filled assembly buffer overrun data are lost and an error flag and interrupt is generated 4 The assembly buffer...

Page 459: ...generation would be disabled in case of single 32 bit transfers SQER error reporting in case of mixed transfers This sequential data write access to the assembly buffer belongs to and is only accepted in Page Mode The data width 64 bit or 32 bit is selected by the data source normally the DMI unit and it is indicated to the Flash by a qualifier to the data address For 64 bit transfers the address ...

Page 460: ... a sequence error is reported instead of execution The complete 256 byte Program Flash assembly buffer and the 32 ECC bytes or the 128 byte Data Flash assembly buffer and the 16 ECC bytes are programmed to Flash in one program operation autonomously controlled by the Flash array module The bits A21 to A8 of PA address of 4 cycle define the page address which is the location of the page within the ...

Page 461: ... all ones data and correct all ones ECC for example to create an invalidation stamp for indication of an invalid wordline During the program operation the quality of the programmed bits is autonomously verified by the Flash FSI Weak bits are re programmed A verification error re programming is not possible anymore is indicated with the VER bit in FSR see also Page 5 19 If write protection is insta...

Page 462: ...he last command cycle Sectors can be erased and re programmed as often as defined by the endurance value max 1000 for special handling of logical 16K sectors see Chapter 5 6 2 1 The timing of erase execution is autonomously controlled by the Flash array module The max erase time is five sec but its exact timing depends on the sector size and the CPU frequency The address bits A21 to A14 of SA addr...

Page 463: ...bove S7 Besides the different sector address definitions the command execution is analogous to the Erase Sector command including erase quality check The sector addresses see Page 5 40 have to be aligned therefore all low order address bits of SA are zero All command cycle addresses including the sector address SA have to be mapped into that space PFlash or DFlash range where the sector to be eras...

Page 464: ...read protection If protection is not disabled when the Erase UC Block command is received the command mode and thus the erase operation is not started and the protection error flag PROER is set in the FSR The UC block to be erased is addressed by UCBA UCB address in the last command cycle to the Program Flash The bits A21 to A10 of UCBA address of 6 cycle define the UC block address and thus the t...

Page 465: ...rotection is enabled The protection is resumed when The command Resume Read Write Protection is executed The next application reset including HW and SW reset is received Note This command sequence is also used to check the correctness of keywords before the protection is locked with the confirmation code in the User Configuration Block A wrong keyword is indicated by the FSR flag PROER Disable Rea...

Page 466: ...n of temporarily unlocked protected sectors and or read protection is resumed This single cycle command resumes all kinds of temporarily disabled protection installations as defined in the User Configuration Pages belonging to the UC blocks This command is released immediately after execution Clear Status The error flags in Flash status register are cleared Additionally the write status bits PROG ...

Page 467: ...y for the commands Write Page and Write User Configuration Page Sector Addresses Sector addresses SA are identical to the sector start addresses represented by lowest address within the sector which are defined by the address bits A21 A14 in the appropriate command cycles Depending on the sector size at least the address bits A13 A0 must be zero for sector addresses which have to be aligned The hi...

Page 468: ...and Sizes of Sectors in Program Flash Sector Phys Sector Sector Size Sector Addresses SA Sector Range Physical Addr hex A21 A19 A18 A17 A16 A14 A13 A00 S0 PS0 16 KB 0 0 0 0 0 0 0 0 0 00 0000 00 3FFF S1 16 KB 0 0 0 0 0 0 0 1 0 00 4000 00 7FFF S2 16 KB 0 0 0 0 0 0 1 0 0 00 8000 00 BFFF S3 16 KB 0 0 0 0 0 0 1 1 0 00 C000 00 FFFF S4 PS4 16 KB 0 0 0 0 0 1 0 0 0 01 0000 01 3FFF S5 16 KB 0 0 0 0 0 1 0 1 ...

Page 469: ... during the last command cycle of a Write Page command sequence The low order address bits A7 A0 Data Flash A6 A0 have to be zero thus the page address PA must be aligned As for sector addresses the high order address bits A31 A22 for Program Flash and A31 A16 for Data Flash are defined by the base address of the accessed Flash bank and depend on the Flash mapping see Table 5 3 for PMU0 The addres...

Page 470: ...the register width Besides word read write accesses also byte or half word read write accesses are supported All Flash register read and write accesses are single cycle operations Data Flash DPneven 128 Byte Base 0 b1 XXXX X X 0 0 x xx00 x xx7F DPnodd 128 Byte Base 0 b1 XXXX X X 1 0 x xx80 x xxFF User Configuration Block UCPneve n 256 Byte 0 0 0 X 0 0 00 0x00 00 0xFF UCPnodd 256 Byte 0 0 0 X 1 0 0...

Page 471: ...before End of Initialization or after ENDINIT with valid password access to WDT_CON0 Read accesses are always possible The following table shows the addresses the access modes and reset types for the Flash registers in PMU0 Table 5 9 Registers Address Spaces of Flash Registers Module Base Address End Address Note FLASH0 F800 1000H F800 23FFH See Table 5 11 Table 5 10 Address Map Symbols Symbol Des...

Page 472: ...62 FLASH0_ MARD Flash Margin Control Register DFlash F800 201CH U SV U SV Class3 Reset Page 5 63 FLASH0_ PROCON0 Flash Protection Configuration User 0 F800 2020H U SV BE Class3 Reset Page 5 69 FLASH0_ PROCON1 Flash Protection Configuration User 1 F800 2024H U SV BE Class3 Reset Page 5 71 FLASH0_ PROCON2 Flash Protection Configuration User 2 F800 2028H U SV BE Class3 Reset Page 5 73 Reserved F800 2...

Page 473: ...IS1 W PRO DIS0 0 W PRO IN2 W PRO IN1 W PRO IN0 0 R PRO DIS R PRO IN 0 PRO IN rh rh r rh r rh rh r rh rh rh r rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DF DB ER PF DB ER DF SB ER PF SB ER PRO ER SQ ER DF OP ER PF OP ER DF PAG E PF PAG E ERA SE PRO G D1 BUS Y D0 BUS Y FA BUS Y P BUS Y rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description PBUSY1 0 rh Program Flash Busy HW...

Page 474: ...ication of busy state of DFlash bank 1 because of active execution of program or erase operation DFlash1 busy state is also indicated during Flash recovery after reset and in power ramp up state or in sleep mode while in busy state the DFlash0 is not in read mode PROG3 4 4 rh Programming State HW controlled status flag 0B There is no program operation requested or in progress or just finished 1B P...

Page 475: ...Page Mode for PFlash cleared with Write Page command Note Concurrent page and read modes are allowed DFPAGE1 2 7 rh Data Flash in Page Mode HW controlled status flag 0B Data Flash not in page mode 1B Data Flash in page mode assembly buffer of DFlash 128 byte is in use being filled up Set with Enter Page Mode for DFlash cleared with Write Page command Note Concurrent page and read modes are allowed...

Page 476: ...ection Registered status bit must be cleared per command PFSBER1 2 3 12 rh PFlash Single Bit Error and Correction 0B No Single Bit Error detected during read access to PFlash 1B Single Bit Error detected and corrected Registered status bit must be cleared per command DFSBER1 2 3 13 rh DFlash Single Bit Error and Correction Function analogous to PFlash PFSBER PFDBER1 2 3 14 rh PFlash Double Bit Err...

Page 477: ...ed sectors is possible HW controlled status flag WPROIN0 21 rh Sector Write Protection Installed for User 0 0B No write protection installed for user 0 1B Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0 HW controlled status flag WPROIN1 22 rh Sector Write Protection Installed for User 1 0B No write protection installed for user 1 1B Sector...

Page 478: ...ser 1 are temporarily unlocked if not coincidently locked by user 0 or user 2 or via read protection HW controlled status flag SLM1 28 rh Flash Sleep Mode HW controlled status flag Indication of Flash sleep mode taken because of global or individual sleep request additionally indicates when the Flash is in shut down mode 0B Flash not in sleep mode 1B Flash is in sleep or shut down mode X 30 rh Res...

Page 479: ...us 4 Cleared with power on reset PORST 5 Cleared with command Resume Protection Note The xBUSY flags as well as the protection flags cannot be cleared with the Clear Status command or with the Reset to Read command These flags are controlled by HW Note The reset value above is indicated after correct execution of Flash rampup Additionally errors are possible after rampup see Chapter 5 6 6 4 0 17 2...

Page 480: ...sk bits Power reduction and shut down control FCON is a ENDINIT protected register It is defined as follows FCON Flash Configuration Register 1014H Reset value 0007 0A06H 1 1 After Flash rampup and execution of the startup SW in BootROM after firmware exit the initial value is 000X 0A06H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EOB M DF DB ERM PF DB ERM DF SB ERM PF SB ERM PRO ERM SQ ERM VO...

Page 481: ... for Error Correction of PFlash 0B No additional wait state for error correction 1B One additional wait state for error correction during read access to Program Flash If enabled this wait state is only used for the first transfer of a burst transfer Set this bit only when requested by Infineon WSDFLASH 11 8 rw Wait States for read access to DFlash This bitfield defines the number of wait states wh...

Page 482: ...s enabled 1B Externally requested Flash sleep is disabled The external signal input is connected with a global power down sleep request signal from SCU SLEEP 15 rw Flash SLEEP 0B Normal state or wake up 1B Flash sleep mode is requested Wake up from sleep is started with clearing of the SLEEP bit RPA 16 rh Read Protection Activated This bit monitors the status of the Flash internal read protection ...

Page 483: ...ly be cleared when RPA 0 This bit is automatically set with reset and is cleared during rampup if no RP installed and during startup BootROM SW in case of internal start out of Flash 0B Data read access to the Flash memory area is allowed 1B Data read access to the Flash memory area is not allowed This bit is not taken into account while RPA 0 DDFDMA 20 rw Disable Data Fetch from DMA Controller Th...

Page 484: ... not enabled 1B Flash interrupt because of Sequence Error is enabled PROERM 26 rw Protection Error Interrupt Mask 0B Interrupt not enabled 1B Flash interrupt because of Protection Error is enabled PFSBERM 27 rw PFlash Single Bit Error Interrupt Mask 0B No Single Bit Error interrupt enabled 1B Single Bit Error interrupt enabled for PFlash DFSBERM 28 rw DFlash Single Bit Error Interrupt Mask 0B No S...

Page 485: ...nfiguration Note After reset and execution of BootROM startup SW the read protection control bits are coded as follows DDF DCF RPA 110 No read protection installed DDF DCF RPA 001 Read protection installed start in internal Flash DDF DCF RPA 111 Read protection installed start not in internal Flash EOBM 31 rw End of Busy Interrupt Mask 0B Interrupt not enabled 1B EOB interrupt is enabled 0 7 5 19 ...

Page 486: ...ster 1008H Reset Value 0062 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number MOD_REV defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type This bit field is C0H It defines the module as a...

Page 487: ...e bit error if enabled in the FCON register An error interrupt is generated in case of any double bit error if enabled in the FCON register This interrupt shall only be used for margin check when trap is disabled A bus error trap is reported in case of a double bit error during access to Program Flash or Data Flash as soon as the disturbed instruction or data is transferred to the PMI or DMI unit ...

Page 488: ...rror trap The double bit error trap can be disabled for margin checks and also redirected to an error interrupt The different margin levels are enabled and selected with the Margin Control Registers MARP and MARD The high margin levels which can be selected are one low level margin coded with 0 and one high level margin coded with 1 Note Only one margin change high or low level PFlash or DFlash is...

Page 489: ... Standard default margin 01B High margin for 0 low level 10B Reserved 11B Reserved MARGIN1 3 2 rw PFLASH Margin Selection for High Level 00B Standard default margin 01B High margin for 1 high level 10B Reserved 11B Reserved TRAPDIS 15 rw PFLASH Double Bit Error Trap Disable 0B If a double bit error occurs in PFLASH a bus error trap is generated1 1B The double bit error trap is disabled Shall be us...

Page 490: ... Margin Selection for High Level 00B Standard default margin 01B High margin for 1 high level 10B Reserved 11B Reserved BNKSEL 4 rw Enable DFLASH Margin Control 0B The active read margin for both DFLASH banks is determined by MARGIN0 and MARGIN1 1B Both DFLASH banks are read with standard default margin independent of MARGIN0 and MARGIN1 TRAPDIS 15 rw DFLASH Double Bit Error Trap Disable 0B If a d...

Page 491: ...hus Flash read accesses by instructions fetched from other memory but internal Flash are initially blocked The read protection is characterized by the following definitions The read protection is installed if the read protection configuration is programmed thus the read protection is configured and confirmed in the User Configuration Block of user 0 UCB0 the installed read protection is indicated ...

Page 492: ...by user SW in Flash In this case all Flash data accesses are disabled but return to Program Flash instruction execution is possible because DCF is not set Before jumping to external memory or internal RAM bit DDF is set by the user DCF is also set by the user directly after jumping to internal or external RAM Now Flash data accesses and return to code fetch from Program Flash are disabled return i...

Page 493: ...tion The Disable Read Protection command sequence is a protected command which is only processed by the command state machine if the included two passwords are identical to the two keywords of user 0 The disabled state of read protection is controlled with the FCON bit RPA 0 and indicated in the Flash Status Register FSR with the RPRODIS bit see Chapter 5 6 3 7 As long as read protection is disabl...

Page 494: ...est person In case of OTP ROM protection the Flash test capability of FAR is very limited because FSI SFRs and FSI SRAM are no more accessible As read protection installation of write protection is performed with the Write User Configuration Page operation controlled by the user With this command the user defines and writes into the UCBx page 0 the write protection configuration bits for all secto...

Page 495: ...swords the complete protection configuration including the keywords of the specific user not user 2 is erased thus the sectors belonging to the user are totally unprotected until the user s UC pages are re programmed Only exception sectors protected by user 2 are locked for ever because the UCB2 can no more be erased after installation of write protection in UCB2 Sector specific write protection m...

Page 496: ...7L S14 S15L S12 S13L S10 S11L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description SnL n 0 9 n rh Sector n Locked for Write Protection by User 0 These bits indicate whether PFLASH sector n is write protected by user 0 or not 0B No write protection is configured for sector n 1B Write protection is configured for sector n S10 S11L 10 rh ...

Page 497: ...or Write Protection by User 0 This bit is only used if PFLASH has more than 1 5 Mbyte It indicates whether PFLASH sectors 14 15 together 512 KB are write protected by user 0 or not 0B No write protection is configured for sectors 14 15 1B Write protection is configured for sectors 14 15 S16 S17L 13 rh Sectors 16 and 17 Locked for Write Protection by User 0 This bit is only used if PFLASH has more ...

Page 498: ...e protection read protection and global write protection is configured by user 0 only for the PFLASH RPRO 15 rh Read Protection Configuration This bit indicates whether read protection is configured for PFLASH and DFLASH by user 0 0B No read protection configured 1B Read protection and global write protection is configured by user 0 master user 0 31 16 r Reserved always read as 0 PROCON1 Flash Pro...

Page 499: ... 0B No write protection is configured for sectors 10 11 1B Write protection is configured for sectors 10 11 S12 S13L 11 rh Sectors 12 and 13 Locked for Write Protection by User 1 This bit is only used if PFLASH has more than 1 Mbyte It indicates whether PFLASH sectors 12 13 together 512 KB are write protected by user 1 or not 0B No write protection is configured for sectors 12 13 1B Write protecti...

Page 500: ... Write protection is configured for sectors 16 17 SPREC 16 rh SPREC Soft Programming Recover 0B Program 1 data 1B Soft Recover See Page 5 93 0 31 17 15 14 r Reserved always read as 0 PROCON2 Flash Protection Configuration Register User 2 1028H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 S16 S17 ROM S14 S15 ROM S12 S13 ROM S10...

Page 501: ... 10 11 together 512 KB are read only sectors or not 0B No ROM functionality is configured for sectors 10 11 1B ROM functionality is configured for sectors 10 11 S12 S13ROM 11 rh Sectors 12 and 13 Locked Forever by User 2 This bit is only used if PFLASH has more than 1 MByte It indicates whether PFLASH sectors 12 13 together 512 KB are read only sectors or not 0B No ROM functionality is configured ...

Page 502: ... User 2 This bit is only used if PFLASH has more than 2 Mbyte It indicates whether PFLASH sectors 16 17 together 512 KB are read only sectors or not 0B No ROM functionality is configured for sectors 16 17 1B ROM functionality is configured for sectors 16 17 0 31 16 15 14 r Reserved always read as 0 Field Bits Type Description ...

Page 503: ... Copy of protection configuration bits Bytes 19 16 First 32 bit keyword of user 0 Bytes 23 20 Second 32 bit keyword of user 0 Bytes 27 24 Copy of first 32 bit keyword Bytes 31 28 Copy of second 32 bit keyword All other page bytes zero The User Configuration Page 1 is not used reserved for future all zero The User Configuration Page 2 bytes 255 0 includes the following information Bytes 3 0 32 bit ...

Page 504: ... after confirmation of its configuration because the UCB2 block can never be erased The confirmation code for user 0 and user 1 shall be programmed only after check of correct programming of keywords e g with the command Disable Read Protection The confirmation code is programmed in the 2 wordline to exclude any possibility of disturbing the keywords or the protection configuration while writing t...

Page 505: ...rogram or erase operation aborted Verify error program or erase operation not correctly finished Protection error Sequence error Single bit error corrected read data from PFlash or DFlash delivered Double bit error in Program Flash or Data Flash Note In case of an OPER or VER error the error interrupt is issued not before the busy state of the Flash is deactivated The source of interrupt is indica...

Page 506: ...trap event all other trap sources cannot be disabled within the PMU Note A double bit error trap during margin check can be disabled via MARP or MARD register and redirected to an interrupt request 5 6 6 3 Handling Errors During Operation The previous sections described shortly the functionality of error indicating bits in the flash status register FSR This section elaborates on this with more in ...

Page 507: ...itions or it is a permanent error due to a hardware defect This situation will practically not occur Attention these bits can also be set during startup see Chapter 5 6 6 4 New state The Flash operation is aborted the BUSY flag is cleared and read mode is entered Proposed handling by software The flag should be cleared with Clear Status The last operation can be determined from the PROG and ERASE ...

Page 508: ... active Write UC Page to protected UCB Attention a protection violation can even occur when a protection was not explicitly installed by the user This is the case when the Flash startup detects an error and starts the user software with read only Flash see Chapter 5 6 6 4 Trying to change the Flash memory will then cause a PROER New state Read mode is entered The protection violating command is no...

Page 509: ...r is programmed in which the erase was aborted In the EEPROM emulation the algorithm must ensure this e g by programming a marker after finishing successfully the erase VER after erase the erase operation can be repeated until VER disappears Repeating the erase more than 3 times consecutively for the same sector is not recommended After that it is better to ignore the VER program the data and chec...

Page 510: ...arison error is found the sector can usually not be erased because it contains active data in other pages The emulation algorithm can mark the affected page as invalid and program the data to a following page As always the number of consecutive repetitions should be limited e g to 3 as protection against violated operating conditions To keep the EEPROM emulation alive even when wordline oriented f...

Page 511: ...ng any flag clearing sequence as Clear Status or Reset to Read The following two levels of situations are separated Fatal level the user software is not started A WDT reset is performed Error level the user software is started but the Flash memory must not be programmed or erased Warning level the user software is started but a warning is issued Fatal Level WDT Reset These error conditions are eva...

Page 512: ...y of the other logical sectors the Flash tried to repair this state The aborted erase operation must be repeated See also Recovery From Aborted Logical Sector Erase ALSE on Page 5 93 Leftover OPER FSR bits set PFOPER or and DFOPER The OPER flags are only cleared by the command sequence Clear Status or with a power on reset Class 0 After any other reset a OPER flag can still be set when the user so...

Page 513: ...ess Write command sequence to Flash Check for correct command sequence by sampling the SQER and PROER bits in status register FSR or install a proper error interrupt reaction In case of an indicated fault condition clear the error flag with a Clear Status or a Reset to Read command and start a specific SW reaction for example a retry operation If no error In case of a Flash array operation check i...

Page 514: ...erally all buffers are invalidated by a reset After change of margin level a wait time of min 10 µsec is necessary for sense amp adjustment before read operations are executed with the modified margins After installation of OTP write protection for sectors with ROM functionality or after installation of tuning protection accesses to Flash SFRs are no more possible this greatly reduces the FAR anal...

Page 515: ...U V1 47 checkerboard pattern Always four sequential pages must then be programmed as follows Page 0 with all ones page 1 remains erased all zeros page 2 remains erased all zeros page 3 is programmed with all ones Identically the next four pages are treated and so on ...

Page 516: ...the user individually for the Flash if the FCON bit 15 SLEEP is set Additionally the sleep mode can be requested by a global SLEEP signal from a Power Management System This external sleep request signal is only accepted by Flash state machines when it is not disabled with the FCON bit ESLDIS The requested sleep mode is only taken if the Flash is in idle state and when all pending or active reques...

Page 517: ...TC1784 Program Memory Unit PMU User s Manual 5 90 V1 1 2011 05 PMU V1 47 Note The wake up time is documented in the data sheet This time may fully delay the interrupt response time in sleep mode ...

Page 518: ...al or physical sector can contain any data It can even be in a state that doesn t allow this range to be programmed When a page programming operation is aborted the page can still appear as erased but contain slightly programmed bits it can appear as being correctly programmed but the data has a lowered retention or the page contains garbage data It is also possible that the read data is instable ...

Page 519: ...d because of the 4 programming operations per wordline 3 Program the data to the Target Page 4 Perform strict check of the Target Page see below 5 Program 8 byte marker to Target Page 6 Perform strict check of the Target Page 7 In case of any error of the strict check go to the next wordline and program the saved data and the target data again following the same steps 8 Ensure that the algorithm d...

Page 520: ...lock UCB1 on Page 5 76 In both cases the algorithm checks first the sectors PS0 and PS4 for an over erased state When this is detected the bit FSR VER is set to inform the application see Chapter 5 6 6 4 After that the algorithm tries to repair this state The default algorithm is selected with SPREC 0 The over erased logical sector is searched When finding one this algorithm programs it shortly wi...

Page 521: ...not needed e g because an ABM boot mode is used then it can be switched off with the ALSEDIS bits in UCB1 see User Configuration Block UCB1 on Page 5 76 Each bit 0 7 of ALSEDIS corresponds to one logical sector If this bit is configured to 1 the logical sector is not repaired If bits 0 3 of ALSEDIS are set to FH then the physical sector PS0 is not checked for an over erased state during startup Th...

Page 522: ...rt of up to 512 Kbyte overlay calibration memory EMEM 1 Support of up to 2 MB overlay memory in external memory EBU space 2 Support of Online Data Acquisition into range of up to 32 KB and of its overlay Support of different overlay memory selections for every enabled overlay block Sizes of overlay blocks selectable depending on the overlay memory OVRAM from 16 byte to 2 Kbyte EMEM1 and external m...

Page 523: ...rlay blocks depend on the selected overlay memory Blocks in the internal OVRAM are smaller than overlay blocks in EMEM or external memory All enabled overlay blocks can be overlaid redirected together with only one register access Concurrently the data cache in the DMI may be flushed The operation of the address translation process is described in Figure 6 2 shown for redirection into the internal...

Page 524: ...ated enable and control bits A mask in the Overlay Mask Register OMASKx defining the size of the block the address bits to be checked for an address match and which bits are used from the redirected address base and which from the original data address The size of the overlay memory blocks can be 2n times the minimal block size 16 byte for internal memory overlay or 1 Kbyte for Emulation Memory ov...

Page 525: ...e determined by the bits set to 0 in the mask OMASK 6 2 Online Data Acquisition OLDA and its Overlay Calibration is additionally supported by an OLDA memory range of up to 32 Kbyte which is a virtual memory and physically only available if it is redirected as described above to the internal or external overlay memory or to the EMEM in Emulation Device If OLDA is enabled in PMU direct write accesse...

Page 526: ...y different users without violation of such control bit which shall remain unchanged Additionally byte protection is possible by support of byte write accesses to OCON 6 4 Target and Overlay Memories In the following the possible target and overlay memories are described and for the overlay memories also their block specific selection and the possible block sizes The Internal Overlay Memory OVRAM ...

Page 527: ...a program memory or OLDA overlay The External Memory is selected for overlay execution if the block related RABRx bits IEMS 1 and EXOMS 1 During address translation the upper 9 address bits are set to A0H1B non cached or to 80H1B cached space using the same segment address as the original data target address For redirection into the external EBU memory the same sizes of the overlay blocks are prov...

Page 528: ...umber will win and perform the address translation The dynamic address translation for redirection to the overlay memory is executed without performance penalty 6 7 Overlay Control Registers Figure 6 3 shows all the overlay control registers associated with control of the overlay memory blocks Overlay Control Registers Overview Figure 6 3 Overlay Control Registers The address space for the overlay...

Page 529: ...ddress are directly used as offset within the block remaining unchanged Additionally for general overlay control the register OCON is provided All overlay block and control registers are reset to their default values with the application reset A special debug reset is not considered Note All overlay block control registers have different definitions for overlay blocks in internal OVRAM RABRx IEMS ...

Page 530: ...5 4 3 2 1 0 TBASE 0 rw r Field Bits Type Description TBASE 27 4 rw Target Base This field holds the base address of the overlay memory block in the target memory Program Flash or OLDA memory or external memory TSEG 31 28 rw Target Segment reserved This bit field is reserved for future use to select a segment In TC1784 implementation any access to segments 8H or AH will be checked for a valid base ...

Page 531: ...5 4 3 2 1 0 TBASE 0 rw r Field Bits Type Description TBASE 27 10 rw Target Base This field holds the base address of the overlay memory block in the target memory Program Flash or OLDA memory or external memory TSEG 31 28 rw Target Segment reserved This bit field is reserved for future use to select a segment In TC1784 implementation any access to segments 8H or AH will be checked for a valid base...

Page 532: ...st block base address that is allowed is OBASEmax block size1 FIXVAL 27 16 r Fixed Value Base address of OVRAM within segment FE8H Base address All other values are reserved Returns FE8H if read should be written with FE8H RC0 RC1 28 29 r Reserved Control Bits Reserved for future control expansions Read returns 0 Must be written with 0 IEMS 30 rw Internal or Emulation External Memory Select IEMS s...

Page 533: ...lay function of overlay block x is enabled 0B Overlay function of block x is disabled 1B Overlay function of block x is enabled This bit can also be changed via its shadow bit in the OCON register 0 3 0 15 13 r Fixed Value Read as 0 should be written with 0 1 The block size is determined by the mask register OMASK Field Bits Type Description ...

Page 534: ...E 18 10 rw Overlay Block Base Address This bit field holds the base address of the overlay memory block in the Emulation Memory EMEM The largest block base address that is allowed is OBASEmax block size1 FIXVAL 27 20 r Fixed Value Base address of EMEM within segment FFH Base address All other values are reserved Returns FFH if read should be written with FFH RC0 28 r Reserved Control Bit Reserved ...

Page 535: ... EMEM is selected as overlay memory if not coincidently EXOMS is set Block sizes are 2n x 1 KB n 0 7 OVEN 31 rwh Overlay Enabled This bit controls whether or not the overlay function of overlay block x is enabled 0B Overlay function of block x is disabled 1B Overlay function of block x is enabled This bit can also be changed via its shadow bit in the OCON register 0 9 0 19 r Fixed Value Read as 0 ...

Page 536: ...w Overlay Block Base Address This bit field holds the base address of the overlay memory block in the external memory The largest block base address that is allowed is OBASEmax block size1 FIXVAL 27 23 r Fixed Value Base address of external memory within segment 00001BBase address All other values are reserved Returns 00001B if read should be written with 00001B RC0 28 r Reserved Control Bit Reser...

Page 537: ...Memory Select IEMS selects the type of the overlay memory and the size range of overlay blocks 0B Internal OVRAM is selected as overlay memory Block sizes are 2n Bytes n 4 11 1B Emulation Memory EMEM is selected as overlay memory if not coincidently EXOMS is set Block sizes are 2n x 1 KB n 0 7 OVEN 31 rwh Overlay Enabled This bit controls whether or not the overlay function of overlay block x is e...

Page 538: ...n and thus determine the block size corresponding final address bits are derived from the original data address One bits determine the corresponding address bits which are used for the address comparison corresponding final address bits are derived from RABRx register in case of address match All OMASK bits located right of the most significant mask bit which is set to zero are treated as zeros as...

Page 539: ...in EMEM 0000000B 128 Kbyte 1000000B 64 Kbyte 1100000B 32 Kbyte 1110000B 16 Kbyte 1111000B 8 Kbyte 1111100B 4 Kbyte 1111110B 2 Kbyte 1111111B 1 Kbyte Zero bits determine the corresponding address bits which are not used in the address comparison and thus determine the block size corresponding final address bits are derived from the original data address One bits determine the corresponding address ...

Page 540: ...onding address bits are participating in the address comparison Corresponding final address bits are taken from RABR 0 9 0 31 28 r Fixed 0 Values Corresponding address bits are not used in the address comparison Corresponding final address bits are taken from the original address Field Bits Type Description ...

Page 541: ...erlay Enable x 0B Overlay block x is disabled with next OVSTRT 1B Overlay block x is enabled with next OVSTRT For each of the 16 overlay blocks indicated by index x one enable disable bit is provided OVSTRT 16 w Overlay Start 0B No action 1B All 16 shadow overlay enable bits SHOVEN ar loaded into the related OVEN bits in RABRx registers in parallel Related to the SHOVEN bits state the overlay bloc...

Page 542: ...it may be used as handshake bit between a debug device via JTAG interface and Cerberus and the CPU POVCONF 25 w Protection Bit for OVCONF 0B Bit protection Bit OVCONF remains unchanged with register OCON write 1B OVCONF can be changed with actual write access to register OCON This bit enables OVCONF write during OCON write Return 0 if read 0 23 19 31 26 r Reserved Read write 0 1 Because the data c...

Page 543: ...ram Flash Bootstrap LoadingMode executes code out of the on chip Instruction Scratchpad Memory SPRAM PMI This code is downloaded beforehand via a selectable serial interface 7 1 Start up Mode Selection After any device start the currently valid start up configuration is indicated in bitfield HWCFG of register SCU_STSTAT Table 7 1 summarizes the defined start up modes The value in this bit field ca...

Page 544: ...rnal start mode is expected to be the configuration used in most cases this mode can be selected by pulling high just 2 pins 7 3 External Start As can be seen in Table 7 1 User Start directly from External memory is not supported as a startup option in TC1784 Nevertheless in TC1784 software execution from External Memory is still possible but it must be first prepared and invoked by another part o...

Page 545: ...as follows receive pin RxD at Pin 12 Port 3 P3 12 transmit pin TxD at Pin 13 Port 3 P3 13 After downloading in case the code the User Start Address STADD is set to the beginning of PMI Scratchpad RAM at D400 0000H 7 4 1 Common Procedures for all Bootloaders The first such a common procedure is to reconfigure the clock system in case the last reset is a Power on This reconfiguration switches from t...

Page 546: ... be executed This interface detection procedure is based on the following principles an ASC Bootloader Host sends one only start Byte and then waits for a response from the target system a CAN Bootloader Host sends a complete frame whereas no more than 5 consecutive bits can be sent having equal logical levels i e after two consecutive edges for a given time dT in any case another edge must follow...

Page 547: ... 2 byte baud rate detection pattern 5555H an 11 bit 2 byte identifier ACKID for the acknowledge frame a 16 bit data message count value DMSGC and an 11 bit 2 byte identifier DMSGID to be used by the data frame s The CAN baud rate is determined by analyzing the received baud rate detection pattern 5555H and the baud rate registers of the MultiCAN module are set accordingly The TC1784 is now ready t...

Page 548: ...r in check condition ASC or CAN The SSW flow in these modes is check the Headers refer to the description in Chapter 10 1 4 1 and react accordingly if the check is OK for one of the Headers set the User Start Address STADD to the respective value from this correct header STADABMx and continue if both the Header checks fail start a Bootloader ASC Generic corresponding to the startup configuration A...

Page 549: ...ormed by the SSW using the Memory Checker Module in TC1784 The complete check procedure for a Header consists of the following steps 1 check the ABM Header ID at offsets 04H 07H the correct values are given in Table 10 2 a if OK continue with 2 b if Not exit the check procedure for this Header with Error 2 calculate the CRC of the first 24 Bytes from the ABM Header process the fields STADABM CRCRa...

Page 550: ...e result with the CRCrange value offset 10H if OK continue with 3 b if Not exit the check procedure for this Header with Error b inverse the result value and compare with CRCrange offset 14H if Not exit the check procedure for this Header with Error if OK the check procedure PASSed for this Header According to the result returned from this check procedure the startup software continues either with...

Page 551: ...xecuted jump to itself As far as the Watchdog Timer is already enabled the endless loop is aborted by a WDT reset which triggers a new SSW execution If this new startup fails again the following error processing will lead to the same endless loop Respectively a second WDT reset will occur being already a locked reset which can be aborted only by a next power on sequence Table 7 3 Errors reported b...

Page 552: ...n SCU_TRAPDIS Watchdog Timer running in time out mode 7 7 2 RAMs Handling No RAM initialization is performed by the Startup Software in TC1784 The user should take care if ECC Control will be enabled for a RAM module first to assure a correct initial content of this memory 7 7 3 Influencing the next SSW execution By writing 1 to SYSCON SETLUDIS no protection the user software will prevent automati...

Page 553: ...M SPRAM2 1 16 Kbyte of Instruction Cache ICACHE2 1 Data Memory Interface DMI 128 Kbyte of Local Data RAM LDRAM3 1 4 Kbyte of Data Cache DCACHE3 PCP memory 32 Kbyte of PCP Code Memory CMEM1 16 Kbyte of PCP Data Memory PRAM1 Furthermore the TC1784 has two on chip buses System Peripheral Bus SPB Local Memory Bus LMB 1 Before enabeling error detection the memory has to be initialized by customer SW 2 ...

Page 554: ...LDRAM CRAM PRAM PFlash DFlash Notes for the Instruction Data Cache configurations where added OVRAM is moved from Segment 12 to Segment 8 and Segment 10 Emulation Device Memory was moved from xFF2 0000 xFF5FFF to xFF0 0000 xFF3 FFFF An PMI memory mirror image was added SPRAM configurable ICACHE to C000 Added map of the mirrored PMI memory image to segment E800 Removed Boot ROM Address Space in seg...

Page 555: ...r agents are PCP2 and DMA1 The LMB address map shows the system addresses from the point of view of the LMB master agents LMB master agents are PMI DMI and DMA1 The LFI is a bi directional bridge between LMB and SPB and therefore not mentioned here as LMB or SPB master in the Address Map The LFI includes an SPB to LMB address translation mechanism The SPB to LMB Bus Address Translation Table can b...

Page 556: ...ap write access LMBBE A bus access is terminated with a bus error on the LMB LMBBET A bus access is terminated with a bus error on the LMB and a DSE trap read access or DAE trap write access access A bus access is allowed and is executed ignore A bus access is ignored and is not executed No bus error is generated trap A DSE trap read access or DAE trap write access is generated 32 Only 32 bit word...

Page 557: ...segment allows non cached accesses to all PMU memories PFLASH DFLASH BROM TROM and OVRAM From the LMB point of view CPU PMI CPU DMI DMA including Cerberus and MLI this memory segment allows non cached accesses to all PMU memories PFLASH DFLASH BROM TROM and OVRAM From the DMA point of view Move Engine Cerberus and MLI accesses to this segment are processed by the DMA LMB master interface on the LM...

Page 558: ...face on the LMB Bus Segment 14 From the SPB point of view PCP DMA including Cerberus and MLI this memory segment allows accesses the DMI Local Data RAM LDRAM and the PMI scratch pad RAM SPRAM All accesses to this segment will be translated by the LFI into Segment 12 and Segment 13 accesses The detailed SPB to LMB Bus Address Translation is described in the Chapter Local Memory to FPI Bus Interface...

Page 559: ...byte SPBBE SPBBE 8 8000 0000H 8027 FFFFH 2 5 Mbyte Program Flash PFLASH access access1 8028 0000H 803F FFFFH 1 5 Mbyte Reserved LMBBE SPBBE access2 8040 0000H 807F FFFFH 4 Mbyte Reserved LMBBE SPBBE LMBBE 8040 0000H 807F FFFFH 4 Mbyte Reserved LMBBE SPBBE LMBBE 8080 0000H 8FDF FFFFH 246 Mbyte External EBU Space access access 8FE0 0000H 8FE0 FFFFH 64 Kbyte Data Flash DFLASH Bank 0 access access1 8F...

Page 560: ...28 0000H A07F FFFFH 5 5 Mbyte Reserved LMBBE SPBBE LMBBE A080 0000H AFDF FFFFH 246 Mbyte External EBU Space access access AFE0 0000H AFE0 FFFFH 64 Kbyte Data Flash DFLASH Bank 0 access access1 AFE1 0000H AFE1 FFFFH 64 Kbyte Data Flash DFLASH Bank 1 access access1 AFE2 0000H AFE6 FFFFH Reserved LMBBE SPBBE LMBBE AFE7 0000H AFE7 7FFFH 32 Kbyte Online Data Acquisition OLDA LMBBE SPBBE access3 LMBBE S...

Page 561: ...access C000 6000H C000 7FFFH 8 Kbyte access4 access4 C000 8000H C000 8FFFH 4 Kbyte access5 access5 C000 9000H C000 97FFH 2 Kbyte access6 access6 C000 9800H C000 9FFFH 2 Kbyte access7 access7 C000 A000H CFFF FFFFH 256 Mbyte Reserved LMBBE SPBBE LMBBE 13 D000 0000H D001 EFFFH 124 Kbyte DMI Local Data RAM LDRAM access access D001 F000H D001 F7FFH 2 Kbyte access8 access8 D001 F800H D001 FFFFH 2 Kbyte ...

Page 562: ...BBE D800 0000H DEFF FFFFH 112 Mbyte Ext Peripheral EBU access access DF00 0000H DFFF FFFFH 16 Mbyte Reserved LMBBE SPBBE LMBBE 14 E000 0000H E7FF FFFFH 128 MB Ext Peripheral EBU access access E800 0000H E83F FFFFH 4 MB Reserved LMBBE LMBBE E840 0000H E841 CFFFH 124 Kbyte DMI Local Data RAM LDRAM access access E841 D000H E841 D7FFH 2 Kbyte access8 access8 E841 D800H E841 DFFFH 2 Kbyte access9 acces...

Page 563: ... for details 3 Online Data Acquisition address space can be disabled enabled via PMU control register bit PMU_OVRCON OLDAEN CPU access to OLDA address space via segment 8 cached results in LMBBET independent of the PMU_OVRCON OLDAEN bit setting 4 Not available when Instruction Cache is configured for 16 Kbyte 5 Not available when Instruction Cache is configured for 8 Kbyte or 16Kbytes 6 Not availa...

Page 564: ...em Timer STM F000 0200H F000 02FFH 256 byte access access Reserved F000 0300H F000 03FFH SPBBE SPBBE On Chip Debug Support Cerberus F000 0400H F000 04FFH 256 byte access access System Control Unit SCU and Watchdog Timer WDT F000 0500H F000 06FFH 2 256 byte access access Reserved F000 0700H F000 07FFH SPBBE SPBBE MicroSecond Bus Controller 0 MSC0 F000 0800H F000 08FFH 256 byte access access Reserve...

Page 565: ... F000 15FFH 256 byte access access Port 10 F000 1600H F000 16FFH 256 byte access access Reserved F000 1700H F000 17FFH SPBBE SPBBE General Purpose Timer Array GPTA0 F000 1800H F000 1FFFH 8 256 byte access access Reserved F000 2000H F000 27FFH SPBBE SPBBE Local Timer Cell Array LTCA2 F000 2800H F000 2FFFH 8 256 byte access access Reserved F000 3000H F000 31FFH SPBBE SPBBE Reserved F000 3200H F000 3...

Page 566: ...ol Controller E Ray F001 0000H F001 7FFFH 32 Kbyte access access Reserved F001 8000H F003 FFFFH SPBBE SPBBE PCP Reserved F004 0000H F004 3EFFH SPBBE SPBBE PCP Registers F004 3F00H F004 3FFFH 256 byte access access Reserved F004 4000H F004 FFFFH SPBBE SPBBE PCP Data Memory PRAM F005 0000H F005 3FFFH 16 Kbyte nE 32 nE 32 Reserved F005 4000H F005 FFFFH SPBBE SPBBE PCP Code Memory CMEM F006 0000H F006...

Page 567: ...alog to Digital Converter 0 ADC0 F010 1000H F010 13FFH 4 256 byte access access Analog to Digital Converter 1 ADC1 F010 1400H F010 17FFH 4 256 byte access access Reserved F010 1800H F010 9FFFH SPBBE SPBBE Reserved F010 A000H F010 BFFFH SPBBE SPBBE Micro Link Interface 0 MLI0 F010 C000H F010 C0FFH 256 byte access access Reserved F010 C100H F010 C1FFH SPBBE SPBBE Memory Checker MCHK F010 C200H F010 ...

Page 568: ...2FFH SPBBE SPBBE Reserved F032 0300H F032 0FFFH SPBBE SPBBE Reserved F032 1000H F032 19FFH SPBBE SPBBE Reserved F032 1A00H F032 2FFFH SPBBE SPBBE Reserved F032 3000H F032 4FFFH SPBBE SPBBE Reserved F032 5000H F7E0 FEFFH SPBBE SPBBE CPU CPU Slave Interface Registers CPS F7E0 FF00H F7E0 FFFFH 256 byte access access CPU Core SFRs GPRs F7E1 0000H F7E1 FFFFH 64 Kbyte access access Reserved F7E2 0000H F...

Page 569: ... SPBBE LMBBE Reserved F801 0200H F87F F9FFH LMBBE SPBBE LMBBE Reserved F87F FA00H F87F FAFFH LMBBE SPBBE LMBBE Overlay Control Unit OVC F87F FB00H F87F FBFFH 256 byte access access CPU DMI Registers F87F FC00H F87F FCFFH 256 byte access access PMI Registers F87F FD00H F87F FDFFH 256 byte access access Local Memory Bus Control Unit LBCU F87F FE00H F87F FEFFH 256 byte access access LFI Bridge F87F F...

Page 570: ... Mbyte Reserved LMBBE access2 8040 0000H 807F FFFFH 4 Mbyte Reserved LMBBE LMBBE 8080 0000H 8FDF FFFFH 246 Mbyte External EBU Space access access 8FE0 0000H 8FE0 FFFFH 64 Kbyte Data Flash DFLASH Bank 0 access access1 8FE1 0000H 8FE1 FFFFH 64 Kbyte Data Flash DFLASH Bank 1 access access1 8FE2 0000H 8FE6 FFFFH Reserved LMBBET LMBBET 8FE7 0000H 8FE7 7FFFH 32 Kbyte Online Data Acquisition OLDA LMBBET ...

Page 571: ...H Bank 0 access access1 AFE1 0000H AFE1 FFFFH 64 Kbyte Data Flash DFLASH Bank 1 access access1 AFE2 0000H AFE6 FFFFH Reserved LMBBET LMBBET AFE7 0000H AFE7 7FFFH 32 Kbyte Online Data Acquisition OLDA LMBBET access3 LMBBET AFE7 8000H AFE7 FFFFH 32 Kbyte Reserved LMBBET LMBBET AFE8 0000H AFE8 1FFFH 8 Kbyte Overlay memory OVRAM access access AFE8 2000H AFEF FFFFH Reserved LMBBET LMBBET AFF0 0000H AFF...

Page 572: ...ccess5 access5 C000 9000H C000 97FFH 2 Kbyte access6 access6 C000 9800H C000 9FFFH 2 Kbyte access7 access7 C000 A000H CFFF FFFFH 256 Mbyte Reserved LMBBET LMBBET 13 D000 0000H D001 EFFFH 124 Kbyte DMI Local Data RAM LDRAM access access D001 F000H D001 F7FFH 2 Kbyte access8 access8 D001 F800H D001 FFFFH 2 Kbyte access9 access23 D001 B000H D3FF FFFFH 64 Mbyte Reserved LMBBET LMBBET Table 8 4 LMB Add...

Page 573: ...DFFF FFFFH 16 Mbyte Reserved LMBBET LMBBET 14 E000 0000H E7FF FFFFH 128 Mbyte Ext Peripheral EBU access access E800 0000H EFFF FFFFH 128 Mbyte Reserved LMBBET LMBBET 15 F000 0000H F7FF FFFFH 128 Mbyte Address map is identical to FPI Bus segment 15 address map see Table 8 3 Reserved areas give an bus error SPBBET SPBBE F800 0000H F800 03FFH 1 Kbyte External Bus Unit EBU access access F800 0400H F80...

Page 574: ...d sequences 2 Write is handled by PMU Flash command sequence see PMU chapter for details 3 Online Data Acquisition address space can be disabled enabled via PMU control register bit PMU_OVRCON OLDAEN CPU access to OLDA address space via segment 8 cached results in LMBBET independent of the PMU_OVRCON OLDAEN bit setting 4 Not available when Instruction Cache is configured for 16 Kbyte 5 Not availab...

Page 575: ...to the different memories in the TC1784 Table 8 5 Possible Memory Accesses Memory Bit Byte Half word Word Double word rmw r w r w r w r w PMI1 1 The module also supports LMB 2 Word and 4 Word Block read and write accesses SPRAM DMI1 LDRAM PMU ROM PFLASH DFLASH OVRAM1 PCP2 2 The module also supports FPI 4 Word and 8 Word Block read and write accesses CMEM PRAM ...

Page 576: ...to LDRAM Please note that the LDRAM is also used by Boot routine and can be used by the CPU for system tasks the Boot routine copies some devices informations during the startup into the LDRAM see chapter BootROM Content LDRAM can be used as context save area for details see chapter CPU Subsystem ...

Page 577: ...1 Basic Port Operation Figure 9 1 shows a general block diagram of a TC1784 GPIO port line Figure 9 1 General Structure of a Port Pin pin ALT1 Pn_OUT Pn_IN Pn_OMR Pn_IOCR ALT2 1 1 pull devices 2 4 2 Access to port registers via the FPI Bus Alternate Data signals or other control lines from Peripherals input stage output stage pad 4 ALT3 1 HW_OUT 1 HW_DIR 2 msb af_Standard _EBCport_structure_L90 vs...

Page 578: ...l SDIR Single DIR the pin is controlled by its own dedicated single HW_DIR signal grouping indicates if the respective pin is controlled by hardware Table 9 1 Port x Input Output Functions Port Pin I O Select Connected Signal s From to Module Px y Input Signal s module s Output GPIO Signal module ALT1 Signal module ALT2 Signal module ALT3 Signal module HW_DIR HW_Out Signal module group En Table 9 ...

Page 579: ...ode the level of the pin can be read by software via Pn_IN or a peripheral can use the pin level as an input In output mode the output driver is activated and drives the value supplied through the multiplexer to the port pin Switching between input and output mode is accomplished through the Pn_IOCR register which enables or disables the output driver If a peripheral unit uses a GPIO port line as ...

Page 580: ...software supported arbitration schemes can be implemented in this way using the open drain configuration and an external wired And circuitry Collisions on the external communication lines can be detected when a high level 1 is output but a low level 0 is seen when reading the pin value via the input register Pn_IN All GPIO lines of the TC1784 that are used by the GPTA module have an emergency stop...

Page 581: ...umber other than zero then some control bits remain unused These bits behave as standard read write bits but do not have any function The registers of not implemented groups of bits starting on the position 0 are implemented but do not have any function The not implemented bits appear in the boundary scan chain although they do not have an external connection Port Register Overview Figure 9 2 Port...

Page 582: ...utput Register 00H Page 9 16 Pn_OMR Port n Output Modification Register 04H Page 9 17 Pn_IOCR0 Port n Input Output Control Register 0 10H Page 9 8 Pn_IOCR4 Port n Input Output Control Register 4 14H Page 9 9 Pn_IOCR8 Port n Input Output Control Register 8 18H Page 9 9 Pn_IOCR12 Port n Input Output Control Register 12 1CH Page 9 11 Pn_IN Port n Input Register 24H Page 9 20 Pn_PDR Port n Pad Driver ...

Page 583: ...nual 9 7 V1 1 2011 05 Ports V1 1 Register Access Rights and Reset Class Table 9 5 Registers Access Rights and Reset Classes Register Short Name Access Rights Reset Class Read Write Pn_OUT U SV U SV Class 3 Pn_OMR Pn_IOCR0 Pn_IOCR4 Pn_IOCR8 Pn_IOCR12 Pn_IN Pn_PDR SV E Pn_ESR ...

Page 584: ...n 3 0 port lines Register Pn_IOCR4 controls the Pn 7 4 port lines Register Pn_IOCR8 controls the Pn 11 8 port lines Register Pn_IOCR12 controls the Pn 15 12 port lines The diagrams below show the register layouts of the port input output control registers with the PCx bit fields One PCx bit field controls exactly one port line Pn x Pn_IOCR0 n 0 10 Port n Input Output Control Register 0 F000 0C10H ...

Page 585: ...ue 2020 2020H Pn_IOCR4 n 7 10 Port n Input Output Control Register 4 F000 0C14H n 100H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC7 0 PC6 0 PC5 0 PC4 0 rw r rw r rw r rw r Field Bits Type Description PC4 PC5 PC6 PC7 7 4 15 12 23 20 31 28 rw Port Control for Port n Pin x This bit field defines the Port n line x functionality according to the coding table see Table 9 6 0 3 0...

Page 586: ...put Control Register 8 18H Reset Value 2020 2020H Pn_IOCR8 n 7 10 Port n Input Output Control Register 8 F000 0C18H n 100H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC11 0 PC10 0 PC9 0 PC8 0 rw r rw r rw r rw r Field Bits Type Description PC8 PC9 PC10 PC11 7 4 15 12 23 20 31 28 rw Port Control for Port n Pin x This bit field defines the Port n line x functionality according...

Page 587: ...ster 12 F000 0C1CH n 100H Reset Value 2020 2020H P3_IOCR12 Port 3 Input Output Control Register 12 1CH Reset Value 2020 2020H P5_IOCR12 Port 5 Input Output Control Register 12 1CH Reset Value 2020 2020H Pn_IOCR12 n 7 8 Port n Input Output Control Register 12 F000 0C1CH n 100H Reset Value 2020 2020H P10_IOCR12 Port 10 Input Output Control Register 12 1CH Reset Value 2020 2020H 31 28 27 24 23 20 19 ...

Page 588: ...Output Function 0X00B Input No input pull device connected 0X01B Input pull down device connected 0X10B Input pull up device connected1 1 This is the default pull device setting after reset 0X11B No input pull device connected 1000B Output Push pull General purpose Output 1001B Alternate output function 1 1010B Alternate output function 2 1011B Alternate output function 3 1100B Open drain General ...

Page 589: ...lasses of pads Class A1 pins low speed 3 3 V LVTTL outputs Class A2 pins high speed 3 3 V LVTTL outputs e g for serial outputs Depending on the assigned pad class the 3 bit wide pad driver mode selection bit fields PDx in the pad driver mode registers Pn_PDR make it possible to select the port line functionality as shown in Table 9 7 Note that the pad driver mode registers are specific for each po...

Page 590: ...eak driver A2 0 0 0 Strong driver sharp edge selected 0 0 1 Strong driver medium edge selected 0 1 0 Strong driver soft edge selected 0 1 1 Strong sharp minus 1 0 0 Medium driver selected 1 0 1 1 1 0 Strong medium minus 1 1 1 Weak driver selected Table 9 8 Possible Driver Strength Combinations in a Mixed Pad Group A1 and A2 PDx 2 PDx 1 PDx 0 A2 Driver Strength A1 Driver Strength 0 0 0 Strong sharp...

Page 591: ... 20 19 18 17 16 0 PD7 0 PD6 0 PD5 0 PD4 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD3 0 PD2 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for Px 3 0 Class A1 or A2 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for Px 7 4 Class A1 or A2 pads coding see Page 9 14 PD2 10 8 rw Pad Driver Mode for Px 11 8 Class A1 or A2 pads coding see P...

Page 592: ...e 16 bit wide ports The Pn_OUT registers of the other ports have a reduced number of Px bits see Pn_OUT register descriptions in the corresponding port sections Pn_OUT n 0 10 Port n Output Register F000 0C00H n 100H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 rwh rwh rwh rwh r...

Page 593: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 PR 15 PR 14 PR 13 PR 12 PR 11 PR 10 PR 9 PR 8 PR 7 PR 6 PR 5 PR 4 PR 3 PR 2 PR 1 PR 0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS 15 PS 14 PS 13 PS 12 PS 11 PS 10 PS 9 PS 8 PS 7 PS 6 PS 5 PS 4 PS 3 PS 2 PS 1 PS 0 w w w w w w w w w w w w w w w w Field Bits Type Description PSx x 0 15 x w Port n Set Bit x Setting this bit will se...

Page 594: ... Purpose I O Ports and Peripheral I O Lines Ports User s Manual 9 18 V1 1 2011 05 Ports V1 1 1 0 Bit Pn_OUT Px is reset 1 1 Bit Pn_OUT Px is toggled Table 9 9 Function of the Bits PRx and PSx cont d PRx PSx Function ...

Page 595: ...s in register Pn_IOCR is discarded Because very few GPIO lines do not have a GPTA outputs mapped to them these GPIO lines too have the emergency stop logic implemented making in addition the architecture uniform Pn_ESR n 0 10 Port n Emergency Stop Register F000 0C50H n 100H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN 15 EN 14 ...

Page 596: ...ed as input or output Note The Pn_IN registers of the ports with less then 16 pins have less than 16 Px bits see Pn_IN register descriptions in the corresponding port sections 0 31 16 r Reserved Read as 0 should be written with 0 Pn_IN n 0 10 Port n Input Register F000 0C24H n 100H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 ...

Page 597: ...e I O control selection functions of each Port 0 line Table 9 10 Port 0 Functions Port Pin I O Pin Functionality Associated Reg I O Line Port I O Control Select Reg Bit Field Value P0 0 I General purpose input P0_IN P0 P0_IOCR0 PC0 0XXXB GPTA input IN0 SCU input HWCFG0 LTCA2 input IN0 O General purpose output P0_OUT P0 1X00B GPTA output OUT0 1X01B GPTA output OUT56 1X10B LTCA2 output OUT0 1X11B P0...

Page 598: ...e input P0_IN P3 P0_IOCR0 PC3 0XXXB GPTA input IN3 SCU input HWCFG3 LTCA2 input IN3 O General purpose output P0_OUT P3 1X00B GPTA output OUT3 1X01B GPTA output OUT59 1X10B LTCA2 output OUT3 1X11B P0 4 I General purpose input P0_IN P4 P0_IOCR4 PC4 0XXXB GPTA input IN4 SCU input HWCFG4 LTCA2 input IN4 O General purpose output P0_OUT P4 1X00B GPTA output OUT4 1X01B GPTA output OUT60 1X10B LTCA2 outpu...

Page 599: ...6 P0_IOCR4 PC6 0XXXB GPTA input IN6 SCU input HWCFG6 SCU input REQ2 LTCA2 input IN6 O General purpose output P0_OUT P6 1X00B GPTA output OUT6 1X01B GPTA output OUT62 1X10B LTCA2 output OUT6 1X11B P0 7 I General purpose input P0_IN P7 P0_IOCR4 PC7 0XXXB GPTA input IN7 SCU input HWCFG7 SCU input REQ3 LTCA2 input IN7 O General purpose output P0_OUT P7 1X00B GPTA output OUT7 1X01B GPTA output OUT63 1X...

Page 600: ...DB0 O General purpose output P0_OUT P9 1X00B GPTA output OUT9 1X01B GPTA output OUT65 1X10B LTCA2 output OUT9 1X11B P0 10 I General purpose input P0_IN P10 P0_IOCR8 PC10 0XXXB GPTA input IN10 O General purpose output P0_OUT P10 1X00B GPTA output OUT10 1X01B ERAY output TXDA0 1X10B LTCA2 output OUT10 1X11B P0 11 I General purpose input P0_IN P11 P0_IOCR8 PC11 0XXXB GPTA input IN11 O General purpose...

Page 601: ... 1X01B ERAY output TXENB 1X10B LTCA2 output OUT13 1X11B P0 14 I General purpose input P0_IN P14 P0_IOCR12 PC14 0XXXB GPTA input IN14 SCU input REQ4 O General purpose output P0_OUT P14 1X00B GPTA output OUT14 1X01B MSC0 Data output Positive C FCLP0C 1X10B LTCA2 output OUT14 1X11B P0 15 I General purpose input P0_IN P15 P0_IOCR12 PC15 0XXXB GPTA input IN15 SCU input REQ5 O General purpose output P0_...

Page 602: ...Register 04H Page 9 17 P0_IOCR0 Port 0 Input Output Control Register 0 10H Page 9 8 P0_IOCR4 Port 0 Input Output Control Register 4 14H Page 9 9 P0_IOCR8 Port 0 Input Output Control Register 8 18H Page 9 10 P0_IOCR12 Port 0 Input Output Control Register 12 1CH Page 9 11 P0_IN Port 0 Input Register 24H Page 9 20 P0_PDR Port 0 Pad Driver Mode Register 40H Page 9 271 1 This register is listed here in...

Page 603: ...40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 PD2 r r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PDERAYB 0 PDERAYA 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P0 7 0 except P0 3 Class A1 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P0 10 8 Class A1 pads coding see Page 9 14 PDERAYA 10 8 rw Pad Driver...

Page 604: ...s Manual 9 28 V1 1 2011 05 Ports V1 1 9 4 Port 1 This section describes the Port 1 functionality in detail 9 4 1 Port 1 Configuration Port 1 is a 16 bit bi directional general purpose I O port that can be alternatively used for the GPTA I O lines SSC1 and ADC0 interfaces ...

Page 605: ...IN P0 P1_IOCR0 PC0 0XXXB GPTA input IN16 OCDS input BRKIN O General purpose output P1_OUT P0 1X00B GPTA output OUT16 1X01B GPTA output OUT72 1X10B LTCA2 output OUT16 1X11B DIR8 OCDS EN8 BRKOUT HW_Out P1 1 I General purpose input P1_IN P1 P1_IOCR0 PC1 0XXXB GPTA input IN17 O General purpose output P1_OUT P1 1X00B GPTA output OUT17 1X01B GPTA output OUT73 1X10B LTCA2 output OUT17 1X11B P1 2 I Genera...

Page 606: ...ose output P1_OUT P4 1X00B GPTA output OUT20 1X01B GPTA output OUT76 1X10B LTCA2 output OUT20 1X11B P1 5 I General purpose input P1_IN P5 P1_IOCR4 PC5 0XXXB GPTA input IN21 LTCA2 input IN21 O General purpose output P1_OUT P5 1X00B GPTA output OUT21 1X01B GPTA output OUT77 1X10B LTCA2 output OUT21 1X11B P1 6 I General purpose input P1_IN P6 P1_IOCR4 PC6 0XXXB GPTA input IN22 LTCA2 IN22 O General pu...

Page 607: ...XXB GPTA input IN24 GPTA input IN48 SSC1input Slave Mode MTSR1B O General purpose output P1_OUT P8 1X00B GPTA output OUT24 1X01B GPTA output OUT48 1X10B SSC1 output Master Mode MTSR1B 1X11B P1 9 I General purpose input P1_IN P9 P1_IOCR8 PC9 0XXXB GPTA input IN25 GPTA input IN49 SSC1input Master Mode MRST1B O General purpose output P1_OUT P9 1X00B GPTA output OUT25 1X01B GPTA output OUT49 1X10B SSC...

Page 608: ...B O General purpose output P1_OUT P11 1X00B GPTA output OUT27 1X01B GPTA output OUT51 1X10B SSC1 output SCLK1B 1X11B P1 12 I General purpose input P1_IN P12 P1_IOCR12 PC12 0XXXB LTCA2 input IN16 O General purpose output P1_OUT P12 1X00B ADC01 AD0EMUX0 1X01B ADC0 AD0EMUX0 1X10B LTCA2 output OUT16 1X11B P1 13 I General purpose input P1_IN P13 P1_IOCR12 PC13 0XXXB LTCA2 input IN17 O General purpose o...

Page 609: ...X2 1X10B LTCA2 output OUT18 1X11B P1 15 I General purpose input P1_IN P15 P1_IOCR12 PC15 0XXXB OCDS BRKIN O General purpose output P1_OUT P15 1X00B Reserved 1X01B Reserved 1X10B Reserved 1X11B DIR8 OCDS EN8 BRKOUT HW_Out 1 The ALT1 and ALT2 for this pin are connected together There are no dependencies Either one can be chosen Table 9 12 Port 1 Functions cont d Port Pin I O Pin Functionality Associ...

Page 610: ...ddress Description see P1_OUT Port 1 Output Register 00H Page 9 341 1 This register is listed here in the Port 1 section because they differ from the general port register description given in Section 9 2 P1_OMR Port 1 Output Modification Register 04H Page 9 341 P1_IOCR0 Port 1 Input Output Control Register 0 10H Page 9 8 P1_IOCR4 Port 1 Input Output Control Register 4 14H Page 9 9 P1_IOCR8 Port 1...

Page 611: ...re assigned to A1 and A2 pad classes P1_PDR Port 1 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDBRKOUT0 0 PDSSC1B r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD2 0 PDEMUX 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P1 3 1 Class A1 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for ...

Page 612: ...Port 1 Emergency Stop Register The basic P1_ESR register functionality is described on Page 9 19 At Port 1 the port lines P1 14 0 are connected to GPTA I O lines Nevertheless all port lines have the emergency stop feature 0 3 7 11 15 19 31 23 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 613: ...ort Pin I O Pin Functionality Associated Reg I O Line Port I O Control Select Reg Bit Field Value P2 0 I General purpose input P2_IN P0 P2_IOCR0 PC2 0XXXB GPTA input IN32 O General purpose output P2_OUT P0 1X00B GPTA output OUT32 1X01B MLI0 output TCLK0 1X10B LTCA2 output OUT28 1X11B P2 1 I General purpose input P2_IN P1 P2_IOCR0 PC3 0XXXB GPTA input IN33 MLI0 input TREADY0A O General purpose outp...

Page 614: ...UT P4 1X00B GPTA output OUT36 1X01B GPTA output OUT36 1X10B LTCA2 output OUT31 1X11B P2 5 I General purpose input P2_IN P5 P2_IOCR4 PC5 0XXXB GPTA input IN37 O General purpose output P2_OUT P5 1X00B GPTA output OUT37 1X01B MLI0 output RREADY0A 1X10B LTCA2 output OUT110 1X11B P2 6 I General purpose input P2_IN P6 P2_IOCR4 PC6 0XXXB GPTA input IN38 MLI0 input RVALID0A O General purpose output P2_OUT...

Page 615: ...OUT P8 1X00B SSC0 output SLSO04 1X01B SSC1 input SLSO14 1X10B MSC0 output EN00 1X11B P2 9 I General purpose input P2_IN P9 P2_IOCR8 PC9 0XXXB O General purpose output P2_OUT P9 1X00B SSC0 output SLSO05 1X01B SSC1 output SLSO15 1X10B MSC0 output EN01 1X11B P2 10 I General purpose input P2_IN P10 P2_IOCR8 PC10 0XXXB SSC1 input MRST1A LTCA2 input IN10 O General purpose output P2_OUT P10 1X00B SSC1 ou...

Page 616: ...urpose input P2_IN P12 P2_IOCR1 2 PC12 0XXXB SSC1 input MTSR1A LTCA2 input IN12 O General purpose output P2_OUT P12 1X00B SSC1 output MTSR1A 1X01B LTCA2 output OUT2 1X10B MSC0 output SOP0B 1X11B P2 13 I General purpose input P2_IN P13 P2_IOCR1 2 PC13 0XXXB SSC1 input SLSI1 MSC0 input SDI0 LTCA2 input IN13 O General purpose output P2_OUT P13 1X00B LTCA2 output OUT3 1X01B Reserved 1X10B Reserved 1X1...

Page 617: ...s P2_OUT P 15 14 9 5 3 3 Port 2 Input Register The basic P2_IN register functionality is described on Page 9 20 However port lines P2 14 and P2 15 are not available Therefore bits P14 and P15 in register P2_IN are always read as 0 Table 9 15 Port 2 Registers Register Short Name Register Long Name Offset Address Description see P2_OUT Port 2 Output Register 00H below1 1 These registers are listed a...

Page 618: ...s all port lines have the emergency stop feature P2_PDR Port 2 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDSSC1 0 PDMSC0 0 PDMLI0 r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P2 4 and P2 7 6 Class A2 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mod...

Page 619: ...s User s Manual 9 43 V1 1 2011 05 Ports V1 1 9 6 Port 3 This section describes the Port 3 functionality in detail 9 6 1 Port 3 Configuration Port 3 is a 16 bit bi directional general purpose I O port which can be alternatively used for ASC0 1 SSC0 1 and CAN lines ...

Page 620: ... 0XXXB ASC0 input RXD0A Async Sync Mode O General purpose output P3_OUT P0 1X00B ASC0 output Synchronous Mode 1 RXD0A 1X01B ASC0 output Synchronous Mode 1 RXD0A 1X10B GPTA0 output OUT84 1X11B P3 1 I General purpose input P3_IN P1 P3_IOCR0 PC1 0XXXB O General purpose output P3_OUT P1 1X00B ASC0 output1 TXD0A 1X01B ASC0 output1 TXD0A 1X10B GPTA0 output OUT85 1X11B P3 2 I General purpose input P3_IN ...

Page 621: ...neral purpose output P3_OUT P4 1X00B SSC0 output Master Mode 1 MTSR0 1X01B SSC0 output Master Mode 1 MTSR0 1X10B GPTA0 output OUT88 1X11B P3 5 I General purpose input P3_IN P5 P3_IOCR4 PC5 0XXXB O General purpose output P3_OUT P5 1X00B SSC0 output SLSO00 1X01B SSC1 output SLSO10 1X10B SSC1 output SLSOANDO0 1X11B P3 6 I General purpose input P3_IN P6 P3_IOCR4 PC6 0XXXB O General purpose output P3_O...

Page 622: ...01B ASC1 output TXD1 1X10B GPTA0 output OUT90 1X11B P3 9 I General purpose input P3_IN P9 P3_IOCR8 PC9 0XXXB ASC1 input Asynchronous Mode Synchronous Mode RXD1A O General purpose output P3_OUT P9 1X00B ASC1 output Synchronous Mode 1 RXD1A 1X01B ASC1 output Synchronous Mode 1 RXD1A 1X10B GPTA0 output OUT91 1X11B P3 10 I General purpose input P3_IN P10 P3_IOCR8 PC10 0XXXB SCU input REQ0 O General pu...

Page 623: ...ve input 0 RXDCAN0 ASC0 input Asynchronous Mode Synchronous Mode RXD0B O General purpose output P3_OUT P12 1X00B ASC0 output Synchronous Mode 1 RXD0B 1X01B ASC0 output Synchronous Mode 1 RXD0B 1X10B GPTA0 output OUT94 1X11B P3 13 I General purpose input P3_IN P13 P3_IOCR12 PC13 0XXXB O General purpose output P3_OUT P13 1X00B CAN node 0 output TXDCAN0 1X01B ASC0 output Synchronous Mode TXD0 1X10B G...

Page 624: ...Synchronous Mode 1 RXD1B 1X01B ASC1 output Synchronous Mode 1 RXD1B 1X10B GPTA0 output OUT96 1X11B P3 15 I General purpose input P3_IN P15 P3_IOCR12 PC15 0XXXB O General purpose output P3_OUT P15 1X00B CAN node 1output TXDCAN1 1X01B ASC1 output Synchronous Mode TXD1 1X10B GPTA0 output OUT97 1X11B 1 The ALT1 and ALT2 for this pin are connected together There are no dependencies Either one can be ch...

Page 625: ... Register 04H Page 9 17 P3_IOCR0 Port 3 Input Output Control Register 0 10H Page 9 8 P3_IOCR4 Port 3 Input Output Control Register 4 14H Page 9 9 P3_IOCR8 Port 3 Input Output Control Register 8 18H Page 9 10 P3_IOCR12 Port 3 Input Output Control Register 12 1CH Page 9 11 P3_IN Port 3 Input Register 24H Page 9 20 P3_PDR Port 3 Pad Driver Mode Register 40H Page 9 501 1 This register is listed here i...

Page 626: ...PDASC0 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P3 11 10 Class A1 pads coding see Page 9 14 PDASC0 18 16 rw Pad Driver Mode for P3 1 0 Class A1 pads coding see Page 9 14 PDSSC0 22 20 rw Pad Driver Mode for P3 7 2 Class A1 and A2 pads coding see Page 9 14 PDASC1 26 24 rw Pad Driver Mode for P3 8 Class ...

Page 627: ...nual 9 51 V1 1 2011 05 Ports V1 1 9 6 3 2 Port 3 Emergency Stop Register The basic P3_ESR register functionality is described on Page 9 19 At Port 3 the port lines P3 4 0 and P3 15 7 are connected to GPTA I O lines Nevertheless all port lines have the emergency stop feature ...

Page 628: ...e Table 9 18 Port 4 Functions Port Pin I O Pin Functionality Associated Reg I O Line Port I O Control Select 1 Reg Bit Field Value P4 0 I General purpose input P4_IN P0 P4_IOCR0 PC0 0XXXB GPTA input IN28 GPTA input IN52 CAN node 2 receive input RXDCAN2 O General purpose output P4_OUT P0 1X00B GPTA output OUT28 1X01B GPTA output OUT52 1X10B Reserved1 1X11B P4 1 I General purpose input P4_IN P1 P4_I...

Page 629: ...t are assigned to this reserved alternate output control selection should not be used Otherwise unpredictable output port line behavior may occur Table 9 19 Port 4 Registers Register Short Name Register Long Name Offset Address Description see P4_OUT Port 4 Output Register 00H Page 9 541 1 This register is listed here in the Port 4 section because they differ from the general port register descrip...

Page 630: ... Modification Register The basic P4_OMR register functionality is described on Page 9 17 However port line P4 15 4 are not available Therefore the P4_OMR bits PS 15 4 and PR 15 4 have no direct effect on port lines but only on register bits P4_OUT P 15 4 9 7 3 3 Port 4 Input Output Control Register x x 4 8 and 12 Port lines P4 15 4 are not available Therefore the PC bit fields PC 15 4 in registers...

Page 631: ...e groups P4_PDR Port 4 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDEXTCLK0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PDEXTCLK1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P4 1 0 Class A1 pads coding see Page 9 14 PDEXTCLK1 6 4 rw Pad Driver Mode for P4 2 Class A2 pad coding see Page 9 14 PDEXTCLK0 18 16 r...

Page 632: ...Lines Ports User s Manual 9 56 V1 1 2011 05 Ports V1 1 9 8 Port 5 This section describes the Port 5 functionality in detail 9 8 1 Port 5 Configuration Port 5 is a 16 bit bi directional general purpose I O port used for the GPTA I O or the MLI0 interface ...

Page 633: ...P0 P5_IOCR0 PC0 0XXXB GPTA input IN40 LTCA2 input IN26 O General purpose output P5_OUT P0 1X00B GPTA output OUT40 1X01B LTCA2 output OUT8 1X10B SSC2 output SLSO20 1X11B P5 1 I General purpose input P5_IN P1 P5_IOCR0 PC1 0XXXB GPTA input IN41 LTCA2 input IN27 O General purpose output P5_OUT P1 1X00B GPTA output OUT41 1X01B LTCA2 output OUT9 1X10B SSC2 output SLSO21 1X11B P5 2 I General purpose inpu...

Page 634: ...IOCR4 PC4 0XXXB GPTA input IN44 LTCA2 input IN29 SSC2 input SLSI2A O General purpose output P5_OUT P4 1X00B GPTA output OUT44 1X01B LTCA2 output OUT12 1X10B SSC2 output SLSO24 1X11B P5 5 I General purpose input P5_IN P5 P5_IOCR4 PC5 0XXXB GPTA input IN45 LTCA2 input IN30 SSC2 input MRST2A O General purpose output P5_OUT P5 1X00B GPTA output OUT45 1X01B LTCA2 output OUT13 1X10B SSC2 output MRST2 1X...

Page 635: ...CLK2A O General purpose output P5_OUT P7 1X00B GPTA output OUT47 1X01B LTCA2 output OUT15 1X10B SSC2 output SCLK2 1X11B P5 8 I General purpose input P5_IN P8 P5_IOCR4 PC8 0XXXB MLI0 input RDATA0B O General purpose output P5_OUT P8 1X00B Reserved 1X01B ERAY output TXDA1 1X10B LTCA2 output OUT89 1X11B P5 9 I General purpose input P5_IN P9 P5_IOCR4 PC9 0XXXB MLI0 input RVALID0B O General purpose outp...

Page 636: ...5 12 I General purpose input P5_IN P12 P5_IOCR4 PC12 0XXXB O General purpose output P5_OUT P12 1X00B MLI0 output TDATA0 1X01B SSC0 output SLSO7 1X10B LTCA2 output OUT93 1X11B P5 13 I General purpose input P5_IN P13 P5_IOCR4 PC13 0XXXB O General purpose output P5_OUT P13 1X00B MLI0 output TVALID0B 1X01B SSC1 output SLSO16 1X10B Reserved 1X11B P5 14 I General purpose input P5_IN P14 P5_IOCR4 PC14 0X...

Page 637: ...hort Name Register Long Name Offset Address Description see P5_OUT Port 5 Output Register 00H Page 9 16 P5_OMR Port 5 Output Modification Register 04H Page 9 17 P5_IOCR0 Port 5 Input Output Control Register 0 10H Page 9 8 P5_IOCR4 Port 5 Input Output Control Register 4 14H Page 9 9 P5_IOCR8 Port 5 Input Output Control Register 8 18H Page 9 10 P5_IOCR12 Port 5 Input Output Control Register 12 1CH P...

Page 638: ... PDMLI0 r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ERAYB 0 ERAYA 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P5 3 0 Class A1 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P5 7 4 Class A1 pads coding see Page 9 14 ERAYA 10 8 rw Pad Driver Mode for P5 8 P5 10 Class A2 pads coding see Page 9 14 ERAYB 14 12 rw Pad Driver Mode for P5 9 P5...

Page 639: ...IOCR PCx bit field of each pin of an LVDS pair must be programed as output that is 1xxxB Figure 9 3 Port 6 Pad Connections Note Applicable in TC1784 A step only the following constraint applies to an LVDS pair used in CMOS mode only one pin of a pair should be used as output the other should be used as input or both pins should be used as inputs Using both pins as outputs is not recommended becaus...

Page 640: ...able 9 22 Port 6 Registers Register Short Name Register Long Name Address Offset Description see P6_OUT Port 6 Output Register 00H Page 9 16 P6_OMR Port 6 Output Modification Register 04H Page 9 17 P6_IOCR00 Port 6 Input Output Control Register 0 10H Page 9 8 P6_IN Port 6 Input Register 24H Page 9 20 P6_PDR Port 6 Output Control Register 40H Page 9 66 P6_ESR Port 5 Emergency Stop Register 50H Page...

Page 641: ...input IN14 O General purpose output P6_OUT P0 1X00B MSC0 output FCLN0 1X01B GPTA0 output OUT80 1X10B LTCA2 output OUT4 1X11B P6 1 I General purpose input P6_IN P1 P6_IOCR0 PC1 0XXXB LTCA2 input IN15 O General purpose output P6_OUT P1 1X00B MSC0 output FCLP0A 1X01B GPTA0 output OUT81 1X10B LTCA2 output OUT5 1X11B P6 2 I General purpose input P6_IN P2 P6_IOCR0 PC2 0XXXB LTCA2 input IN24 O General pu...

Page 642: ...7 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P6 1 0 The msb of PD0 switches between CMOS and LVDS pads Default CMOS input 0XXB CMOS Input or Output depending on the IOCR setting 1XXB LVDS Output pull up pull down must be switched off via IOCR PD1 6 4 rw Pad Driver Mode for P6 3 2 The msb of PD0 switches between CMOS...

Page 643: ...ame Address Offset Description see P7_OUT Port 7 Output Register 00H Page 9 16 P7_OMR Port 7 Output Modification Register 04H Page 9 17 P7_IOCR00 Port 7 Input Output Control Register 0 10H Page 9 8 P7_IOCR04 Port 7 Input Output Control Register 1 14H Page 9 9 P7_IOCR08 Port 7 Input Output Control Register 2 18H Page 9 10 P7_IOCR12 Port 7 Input Output Control Register 3 1CH Page 9 11 P7_IN Port 7 I...

Page 644: ...it Field Value P7 0 I General purpose input P7_IN P0 P7_IOCR0 PC0 0XXXB EBU input AD0 O General purpose output P7_OUT P0 1X00B GPTA0 output OUT32 1X01B Reserved 1X10B Reserved 1X11B DIR1 EBU EN AD0 HW_Out P7 1 I General purpose input P7_IN P1 P7_IOCR0 PC1 0XXXB EBU input AD1 O General purpose output P7_OUT P1 1X00B GPTA0 output OUT33 1X01B Reserved 1X10B Reserved 1X11B DIR1 EBU EN AD1 HW_Out P7 2 ...

Page 645: ... P4 1X00B GPTA0 output OUT36 1X01B Reserved 1X10B Reserved 1X11B DIR1 EBU EN AD4 HW_Out P7 5 I General purpose input P7_IN P5 P7_IOCR4 PC5 0XXXB EBU input AD5 O General purpose output P7_OUT P5 1X00B GPTA0 output OUT37 1X01B Reserved 1X10B Reserved 1X11B DIR1 EBU EN AD5 HW_Out P7 6 I General purpose input P7_IN P6 P7_IOCR4 PC6 0XXXB EBU input AD6 O General purpose output P7_OUT P6 1X00B GPTA0 outp...

Page 646: ... 1X00B GPTA0 output OUT40 1X01B Reserved 1X10B Reserved 1X11B DIR2 EBU EN AD8 HW_Out P7 9 I General purpose input P7_IN P9 P7_IOCR8 PC9 0XXXB EBU input AD9 O General purpose output P7_OUT P9 1X00B GPTA0 output OUT41 1X01B Reserved 1X10B Reserved 1X11B DIR2 EBU EN AD9 HW_Out P7 10 I General purpose input P7_IN P10 P7_IOCR8 PC10 0XXXB EBU input AD10 O General purpose output P7_OUT P10 1X00B GPTA0 ou...

Page 647: ...2 1X00B GPTA0 output OUT44 1X01B Reserved 1X10B Reserved 1X11B DIR2 EBU EN AD12 HW_Out P7 13 I General purpose input P7_IN P13 P7_IOCR12 PC13 0XXXB EBU input AD13 O General purpose output P7_OUT P13 1X00B GPTA0 output OUT45 1X01B Reserved 1X10B Reserved 1X11B DIR2 EBU EN AD13 HW_Out P7 14 I General purpose input P7_IN P14 P7_IOCR12 PC14 0XXXB EBU input AD14 O General purpose output P7_OUT P14 1X00...

Page 648: ...eral purpose input P7_IN P15 P7_IOCR12 PC15 0XXXB EBU input AD15 O General purpose output P7_OUT P15 1X00B GPTA0 output OUT47 1X01B Reserved 1X10B Reserved 1X11B DIR2 EBU EN AD15 HW_Out Table 9 25 Port 7 Functions cont d Port Pin I O Pin Functionality Associated Reg I O Line Port I O Control Select Reg Bit Field Value ...

Page 649: ... Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD3 0 PD2 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P7 3 0 Class A2 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P7 7 4 Class A2 pads coding see Page 9 14 PD2 10 8 rw Pad Driver Mode for P7 11 8 Class A2 pads coding see Pag...

Page 650: ...ame Address Offset Description see P8_OUT Port 8 Output Register 00H Page 9 16 P8_OMR Port 8 Output Modification Register 04H Page 9 17 P8_IOCR00 Port 8 Input Output Control Register 0 10H Page 9 8 P8_IOCR04 Port 8 Input Output Control Register 1 14H Page 9 9 P8_IOCR08 Port 8 Input Output Control Register 2 18H Page 9 10 P8_IOCR12 Port 8 Input Output Control Register 3 1CH Page 9 11 P8_IN Port 8 I...

Page 651: ...Reserved 1X01B GPTA0 output OUT48 1X10B LTCA2 output OUT95 1X11B DIR3 EBU EN3 A16 HW_Out P8 1 I General purpose input P8_IN P1 P8_IOCR0 PC1 0XXXB O General purpose output P8_OUT P1 1X00B Reserved 1X01B GPTA0 output OUT49 1X10B LTCA2 output OUT96 1X11B DIR3 EBU EN3 A17 HW_Out P8 2 I General purpose input P8_IN P2 P8_IOCR0 PC2 0XXXB O General purpose output P8_OUT P2 1X00B Reserved 1X01B GPTA0 outpu...

Page 652: ...erved 1X01B GPTA0 output OUT53 1X10B LTCA2 output OUT100 1X11B DIR4 EBU SEN CS0 HW_Out P8 6 I General purpose input P8_IN P6 P8_IOCR4 PC6 0XXXB O General purpose output P8_OUT P6 1X00B Reserved 1X01B GPTA0 output OUT54 1X10B LTCA2 output OUT101 1X11B DIR4 EBU SEN CS1 HW_Out P8 7 I General purpose input P8_IN P8 P8_IOCR4 PC7 0XXXB O General purpose output P8_OUT P8 1X00B Reserved 1X01B GPTA0 output...

Page 653: ...ed 1X01B GPTA0 output OUT57 1X10B LTCA2 output OUT104 1X11B DIR5 EBU EN5 BC0 HW_Out P8 10 I General purpose input P8_IN P10 P8_IOCR8 PC10 0XXXB O General purpose output P8_OUT P10 1X00B Reserved 1X01B GPTA0 output OUT58 1X10B LTCA2 output OUT105 1X11B DIR5 EBU EN5 BC1 HW_Out P8 11 I General purpose input P8_IN P11 P8_IOCR8 PC11 0XXXB O General purpose output P8_OUT P11 1X00B Reserved 1X01B GPTA0 o...

Page 654: ... I General purpose input P8_IN P13 P8_IOCR12 PC13 0XXXB O General purpose output P8_OUT P13 1X00B Reserved 1X01B GPTA0 output OUT61 1X10B LTCA2 output OUT108 1X11B DIR5 EBU EN5 ADV HW_Out P8 14 I General purpose input P8_IN P14 P8_IOCR12 PC14 0XXXB EBU EN5 WAIT 0XXXB O General purpose output P8_OUT P14 1X00B Reserved 1X01B GPTA0 output OUT62 1X10B LTCA2 output OUT109 1X11B Table 9 27 Port 8 Functi...

Page 655: ...0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD3 0 PD2 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P8 3 0 Class A2 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P8 7 4 Class A2 pads coding see Page 9 14 PD2 10 8 rw Pad Driver Mode for P8 13 8 Class A2 pads coding see P...

Page 656: ... Register Long Name Address Offset Description see P9_OUT Port 9 Output Register 00H Page 9 16 P9_OMR Port 9 Output Modification Register 04H Page 9 17 P9_IOCR00 Port 9 Input Output Control Register 0 10H Page 9 8 P9_IOCR04 Port 9 Input Output Control Register 4 14H Page 9 9 P9_IOCR08 Port 9 Input Output Control Register 8 18H Page 9 10 P9_IN Port 9 Input Register 24H Page 9 20 P9_PDR Port 9 Outpu...

Page 657: ...rved1 1X01B GPTA0 output OUT80 1X10B LTCA2 output OUT80 1X11B P9 1 I General purpose input P9_IN P1 P9_IOCR0 PC1 0XXXB O General purpose output P9_OUT P1 1X00B CAN2 output TXDCAN2 1X01B GPTA0 output OUT81 1X10B LTCA2 output OUT81 1X11B P9 2 I General purpose input P9_IN P2 P9_IOCR0 PC2 0XXXB O General purpose output P9_OUT P2 1X00B Reserved1 1X01B GPTA0 output OUT82 1X10B LTCA2 output OUT82 1X11B ...

Page 658: ...3 1X00B Reserved1 1X01B GPTA0 output OUT86 1X10B LTCA2 output OUT86 1X11B P9 7 I General purpose input P9_IN P3 P9_IOCR4 PC3 0XXXB O General purpose output P9_OUT P3 1X00B Reserved1 1X01B GPTA0 output OUT87 1X10B LTCA2 output OUT87 1X11B 1 The port I O control values P9_IOCRx Py that are assigned to this reserved alternate output control selection should not be used Otherwise unpredictable output ...

Page 659: ...r 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDCAN r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P9 0 2 3 Class A1 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P9 7 4 Class A1 pads coding see Page 9 14 PDCAN 18 16 rw Pad Driver Mode for P9 1 Class A2 pad cod...

Page 660: ...ress Offset Description see P10_OUT Port 10 Output Register 00H Page 9 16 P10_OMR Port 10 Output Modification Register 04H Page 9 17 P10_IOCR00 Port 10 Input Output Control Register 0 10H Page 9 8 P10_IOCR04 Port 10 Input Output Control Register 1 14H Page 9 9 P10_IOCR08 Port 10 Input Output Control Register 2 18H Page 9 10 P10_IOCR12 Port 10 Input Output Control Register 3 1CH Page 9 11 P10_IN Po...

Page 661: ...pose input P10_IN P0 P10_IOCR0 PC0 0XXXB SSC2 input Slave Mode MRST2B O General purpose output P10_OUT P0 1X00B SSC2 output Master Mode MRST2 1X01B MCDS event output 0 EVTO0 1X10B Reserved 1X11B P10 1 I General purpose input P10_IN P1 P10_IOCR0 PC1 0XXXB SSC2 input Master Mode MTSR2B O General purpose output P10_OUT P1 1X00B SSC2 output Slave Mode MTSR2 1X01B MCDS event output 1 EVTO1 1X10B Reserv...

Page 662: ...served 1X11B P10 5 I General purpose input P10_IN P5 P10_IOCR4 PC5 0XXXB O General purpose output P10_OUT P5 1X00B SSC2 output SLSO22 1X01B Reserved 1X10B Reserved 1X11B P10 6 I General purpose input P10_IN P6 P10_IOCR4 PC6 0XXXB O General purpose output P10_OUT P6 1X00B SSC2 output SLSO23 1X01B SSC2 output SLSOAND03 1X10B Reserved 1X11B P10 7 I General purpose input P10_IN P7 P10_IOCR4 PC7 0XXXB ...

Page 663: ... 1X11B P10 10 I General purpose input P10_IN P10 P10_IOCR8 PC10 0XXXB O General purpose output P10_OUT P10 1X00B Reserved 1X01B Reserved 1X10B Reserved 1X11B P10 11 I General purpose input P10_IN P11 P10_IOCR8 PC11 0XXXB O General purpose output P10_OUT P11 1X00B Reserved 1X01B Reserved 1X10B Reserved 1X11B P10 12 I General purpose input P10_IN P12 P10_IOCR1 2 PC12 0XXXB O General purpose output P...

Page 664: ...Ports V1 1 P10 13 I General purpose input P10_IN P13 P10_IOCR1 2 PC13 0XXXB O General purpose output P10_OUT P13 1X00B Reserved 1X01B Reserved 1X10B Reserved 1X11B Table 9 31 Port 10 Functions cont d Port Pin I O Pin Functionality Associated Reg I O Line Port I O Control Select Reg Bit Field Value ...

Page 665: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD3 0 PD2 0 PD1 0 PD0 r rw r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P10 3 0 Class A1 pads coding see Page 9 14 PD1 6 4 rw Pad Driver Mode for P10 7 4 Class A1 pads coding see Page 9 14 PD2 10 8 rw Pad Driver Mode for P10 11 8 Class A1 pads coding see Page 9 14 PD3 14 12 rw Pa...

Page 666: ...l therefore list enhancements that may not apply to the PCP version included in TC1784 Table 21 PCP Feature Enhancement History List Version Enhancement TC1775 First released version of PCP TC1766 TC1796 Optimised Context switching Support for nested interrupts Enhanced instruction set Enhanced instruction execution speed Enhanced interrupt queueing TC1767 TC1797 Enhanced PCP core to support highe...

Page 667: ...outines to data capture and data transfer operations Easing the implementation of multitasking operating systems The PCP has an architecture that efficiently supports DMA type transactions to and from arbitrary devices and memory addresses within the TC1784 and also has reasonable stand alone computational capabilities 10 2 1 High Integrity Operation The PCP can be used in High Integrity Systems t...

Page 668: ... Code Memory CMEM Parameter Memory PRAM PCP Interrupt Control Unit PICU PCP Service Request Nodes PSRN System bus interface to the Flexible Peripheral Interface FPI Bus Figure 16 PCP Block Diagram MCB06135 PCP Processor Core PCP Service Req Nodes PSRNs PCP Interrupt Control Unit PICU Parameter Memory PRAM Code Memory CMEM FPI Interface PCP Interrupt Arbitration Bus CPU Interrupt Arbitration Bus FP...

Page 669: ...ext service request The PCP Processor Core is capable of suspending execution of a Channel Program on receipt of a service request with a higher priority than the channel currently being executed The Core will automatically resume processing of the original Channel Program once the higher priority request or requests has been processed A channel that has been suspended in this way is termed as Sus...

Page 670: ...gardless of a failure in another part of the system or the PCP itself This means that it is necessary to protect the content of the CMEM from such failures CMEM content can only be modified via the FPI Protection of CMEM therefore consists of prevention of unwanted FPI writes to CMEM The normal model of PCP operation is that the program code i e CMEM is loaded at system initialization and remains ...

Page 671: ... and other resources through the FPI Bus interface The PCP can become an FPI Bus slave so that other FPI Bus master may access CMEM and PRAM and the control and status registers in the PCP The CMEM and PRAM blocks are visible to FPI Bus masters as a block of memory on the FPI Bus If an FPI Bus master accesses CMEM or PRAM memory concurrently with the PCP the external FPI Bus master is given preced...

Page 672: ...l Processor PCP User s Manual 10 7 V1 1 2011 05 PCP V2 09 program when it is suspended in favor of a higher priority Service Request Please refer to Section 10 6 3 for more detailed information on the operation of these nodes ...

Page 673: ... environment outside of the scope of the PCP 10 4 1 General Purpose Register Set of the PCP The program accessible register file of the PCP is composed of eight 32 bit General Purpose Registers GPRs These registers are all accessible by PCP programs directly as part of the PCP instruction set Source and destination registers must be specified in most instructions These registers are referenced to ...

Page 674: ...om outside the PCP 10 4 1 1 Register R0 R0 is used as an implicit operand destination for some instructions These are detailed in the individual instruction descriptions 10 4 1 2 Registers R1 R2 and R3 R1 R2 and R3 are general use registers It is recommended that by convention R2 should be used as a return address register when call and return program structures are used 10 4 1 3 Registers R4 and ...

Page 675: ...vel at which the channel shall run at its next invocation before the EXIT is executed The fields for R6 are shown below PCP Register R6 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CPPN SRPN rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOS GEN GEN CNT1 rw rw rw rw Field Bits Type Description CPPN 31 24 rw General use PCP Priority Number Posted to PICU SRPN 23 16 rw General...

Page 676: ...gs to 0 As a result the value left in R7 after the MOV is complete will be 0000FF04H i e C 1 Z 0 N 0 It is recommended that only SET and CLR instructions should be used to explicitly modify flags in R7 The Data Pointer R7 DPTR is the means of accessing PRAM variables programmatically It points to a 64 word PRAM segment that may be addressed by instructions that can use the PRAM for source or desti...

Page 677: ... rw rw Field Bits Type Description RES 31 16 r Reserved read as 0 should be written with 0 DPTR 15 8 rw Data Pointer Segment Address for PRAM accesses RES 7 rw Reserved should always be written with 0 CEN 6 rw Channel Enable Control Bit IEN 5 rw Interrupt Enable 0B Channel is not interruptible 1B Channel can be suspended in favor of a higher priority service request CNZ 4 rw Outer Loop Counter 1 Z...

Page 678: ...tically copied to a defined area in the PRAM Context Save If the same channel program is re activated the contents of the registers are restored by copying the values from the same defined PRAM area into the appropriate registers Context Restore The defined area in the PRAM for the context save and restore operations is called the CSA Each channel program has its own individual predefined region i...

Page 679: ...ntext Model is used for all channels Once a context model has been selected during PCP configuration and the PCP has been started the PCP must continue to use that Context Model Attempting to change the Context Model in use during PCP operation will lead to invalid context restore operations which will in turn lead to invalid PCP operation In the case of Small and Minimum Context Models the unsave...

Page 680: ... 17 PCP Context Models MCA06136 R0 R1 R2 R3 R4 R5 R6 R7 Stored Context in PRAM R0 R1 R2 R3 R4 R5 R6 R7 PCP Register Set Restore Save 8 Words Full Context R0 R1 R2 R3 R4 R5 R6 R7 R4 R5 R6 R7 Small Context Restore Save 4 Words R0 R1 R2 R3 R4 R5 R6 R7 R6 R7 Minimum Context Restore Save 2 Words ...

Page 681: ...he TriCore Architecture the bottom region context region 0 of the CSA is never used for an actual context The total size of the CSA depends on the Context Model and the number of service request numbers used in a given system Each priority number used in a service request node which can activate interrupts to the PCP must be represented through a dedicated context region in the PRAM The highest ad...

Page 682: ...he memory space required for this data For best utilization of PRAM it is advisable to have the CSA grow upwards as a contiguous area without any holes meaning that all SRPNs in the range 1 max are actually used to place interrupt requests on the PCP Unused regions within the CSA that is the unused region at the base of the CSA and any context regions associated with unused channels cannot be used...

Page 683: ...CR1 CR0 00H 08H 10H SRPN 2 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 n1 8H SRPN n1 Context n1 31 0 SRPN 1 00H 04H 0CH CR7 CR6 CR5 CR4 CR7 CR6 CR5 CR4 08H Context 2 SRPN 2 Context 3 SRPN 3 Context n2 SRPN n2 Small Context 31 0 Minimum Context 31 0 00H 2 Words Not Used SRPN 1 Context 1 CR7 CR6 02H 04H SRPN 2 Context 2 CR7 CR6 06H Context 3 08H SRPN 3 n3 2H Context n3 SRPN n3 PRAM Memory PRAM Memory Note All a...

Page 684: ...errupts see Page 146 The criteria for choosing the Context Model are listed in the following Size of PRAM implemented in a given derivative Amount of channels SRPNs that need to be used in a system Amount of PRAM used for general variables and global s Amount of context register content which need to be saved and restored quickly by most of the most important channels While registers R0 through R5...

Page 685: ...er half of R7 is loaded from CR7 15 0 The operating priority of the channel is taken from CR6 31 24 and all of R6 is loaded from CR6 Figure 19 Context Restore Channel Start in Channel Resume Mode PC MCA06138 31 16 0 CPPN 0 ARB CTL PIPN 0 IE 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS Stored Content CR7 in PRAM CDPTR 31 16 0 0 FLAGS CDPTR PCP Register R7...

Page 686: ...7 is loaded from CR7 15 0 The upper half of CR6 is discarded The operating priority of the channel is taken from CR6 31 24 and all of R6 is loaded from CR6 Figure 20 Context Restore Channel Start in Channel Restart Mode 2 SRPN PC MCA06139 31 16 0 CPPN PCP Interrupt Control Reg PCP_ICR 0 ARB CTL PIPN 0 IE 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS Store...

Page 687: ...e Request Node that was used to store the Suspended Interrupt Request see Page 91 Figure 21 Context Restore Suspended Channel Restart PC MCA06140 31 16 0 CPPN PCP Interrupt Control Reg PCP_ICR 0 ARB CTL PIPN 0 IE 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS Stored Content CR7 in PRAM CDPTR 31 16 0 0 FLAGS DPTR PCP Register R7 16 0 PCP Program Counter Sto...

Page 688: ...t when Channel Resume Mode has been selected The value written to CR7 is created by concatenating the 16 bit PC value with the lower 16 bits of R7 CR6 is written with the value taken from R6 Figure 22 Context Save Channel Exit in Channel Resume Mode PC MCA06141 When the context save is due to execution of an EXIT instruction with EP 0 the PC is loaded with the appropriate channel entry table addre...

Page 689: ... This is the same as for Channel Resume mode except that the PC value is discarded and the appropriate Channel Entry Table address is written to CR7 31 16 Figure 23 Context Save Channel Exit in Channel Restart Mode 2 SRPN MCA06142 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 Stored Content CR6 in PRAM 31 16 0 CPC CFLAGS Stored Content CR7 in PRAM CDPTR 31 16 0 0 FLAGS CDPT...

Page 690: ... SRPN and the operating priority CPPN with which the channel was operating prior to being suspended This operation in conjunction with the suspended channel restore operation shown in Figure 21 allows the temporary suspension of a channel in favor of a higher priority channel Figure 24 Context Save Channel Suspend PC SRPN 1 1 MCA06143 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS Stored Co...

Page 691: ...witching strategy consisting of optimization of both context load and store During a context load in which the channel that is starting is also the last channel that the PCP was running then the PCP GPRs already contain the values appropriate to the channel In this case there is no need to reload the context i e the PCP can immediately continue operation at the appropriate point in the code withou...

Page 692: ... same address in the interrupt entry table each time the channel is requested Channel Resume Mode allows the PCP to begin execution at the PC address restored as part of the channel program context This mode allows code to be contiguous and start at any arbitrary address It also allows for the implementation of interrupt driven state machines and even the sharing of code across multiple programs w...

Page 693: ...sume Mode is globally selected by configuring each EXIT instruction to determine the channel start address to be used on the next invocation of a channel see Page 110 When the EP 0 setting is used the PC value saved in the channel s context saved in CPC is the address of the appropriate location in the channel entry table This forces the channel to start at the appropriate location in the interrup...

Page 694: ... each offset by two Code Memory CMEM Instruction 1 2 Half words Not Used Instruction 2 MCA06144 00H 02H SRPN 1 Channel 1 04H Instruction 2 Instruction 1 Channel 2 SRPN 2 SRPN 3 06H Instruction 2 Instruction 1 Channel 3 SRPN n1 n1 2H Instruction 1 Instruction 2 Channel 1 Channel 1 Main Code Channel 3 Main Code Channel n1 Main Code Channel 2 Main Code Channel Restart Mode 16 0 Channel Entry Table Ch...

Page 695: ...nterrupts and executing channel programs 10 5 2 Channel Invocation and Context Restore Operation A channel program is started when one or other of the following conditions occurs The current round of PCP interrupt arbitration results in a winning interrupt number SRPN and the PCP is currently quiescent has exited the previous channel and stored the context for that channel The current round of PCP...

Page 696: ...hat the PC value should be set to the appropriate channel entry point if PCP_CS RCB 1 10 5 3 Channel Exit and Context Save Operation The context of a channel program must be saved when it terminates Three events can cause the termination of a channel program Execution of the EXIT instruction normal termination Occurrence of an error Execution of the DEBUG instruction channel termination is optiona...

Page 697: ...ial care needs to be taken to optimize the number of clock cycles required to perform a Context Save During a Context Save the PCP Processor Core needs only to save those registers that have been written since the last Context Restore was performed Note Particular attention must be paid to the values of R6 and R7 prior to execution of the EXIT instruction When posting an interrupt request the user...

Page 698: ...ble to restore the channel program to operation The minimum required to restart the channel program is to set the context value of CR7 CEN 1 10 5 3 3 Debug Exit If the DEBUG instruction is programmed to stop the channel program execution SDB 1 has been specified the PCP performs an exit sequence that is very similar to the error exit sequence with the exception that no interrupt request to the CPU...

Page 699: ...have some special characteristics which are described in the following sections Figure 26 shows an overview of the PCP interrupt scheme Figure 26 PCP Interrupt Block Diagram MCA06145 Winning SRPN Priority Interrupt Type PCP Core Queue Full Nesting Available CPPN SRPN TOS PCP_SRC4 Select PCP_SRC2 PCP_SRC3 PCP_SRC9 PCP_SRC10 PCP_SRC11 PCP_SRC0 PCP_SRC1 PCP Service Request Nodes PICU Suspended Interr...

Page 700: ...he request with the highest priority It then places the priority number of this winning service request into the PIPN field of register PCP_ICR and generates a service request to the PCP kernel If the PCP kernel is currently busy processing a channel program the new request is left pending until the current channel program has finished When the PCP kernel is ready to accept a new service request i...

Page 701: ... to 1 meaning these service requests are always enabled Note The number of interrupt buses is device dependent Programming a PCP_SRCx register x 4 to 8 with a TOS value representing a non available interrupt bus 10B or 11B in the TC1784 will disable Service Request Node x The actual service request flag and the service request priority number of the PCP_SRCx registers are updated by the PCP when i...

Page 702: ...XIT instruction 10 6 4 2 Service Request on Suspension of Interrupt An implicit PCP service request is issued when the PCP suspends execution of the ongoing channel program in favor of a service request with a higher priority Such a service request is always issued to the PCP s own interrupt bus and is stored in one of the three extended Service Request Nodes PCP_SCR9 PCP_SRC10 PCP_SRC11 Along wit...

Page 703: ...ter PCP_ES 10 6 4 4 Queue Full Operation Queuing the implicit service requests typically allows the PCP to continue with the next service request without stalling The depth of the queue and the number of channel programs using them determines the stall rate Depending on the selected service provider via R6 TOS in case of an EXIT interrupt or always to the CPU in case of an error interrupt the requ...

Page 704: ...n otherwise appropriate use of the interrupt priority scheme It is recommended that the system be designed such that in most cases high priority numbers can be assigned to these self interrupts so that they can win normal arbitration rounds avoiding the situation where the PCP queue becomes full Note If the CPU queue is full the PCP can continue to operate until it needs to post another service re...

Page 705: ...ction 10 7 2 Protection of PRAM is provided to allow running of system critical tasks on the PCP Protection means that such tasks can be made immune from failures outside of the PCP or indeed from software failures in non critical tasks running on the PCP itself PRAM protection is based around the concept of Protected and Unprotected Channel Programs A Protected channel program is one that is runn...

Page 706: ...address range defined by PCP_PPROT FBASE is issued with an error response and the PRAM content remains unmodified The address range can be select such that an Open Window of PRAM based at the top of PRAM remains available for incoming FPI write accesses The Open Window is provided as PRAM is often used for implementation of a mail box to allow communication between the PCP and other on chip cores ...

Page 707: ... place and the PCP will exit the channel with an IOP Illegal Operation error Note FPI PRAM write accesses to PRAM are unaffected by this protection 10 8 FPI Interface The PCP operates both as an FPI Master and an FPI Slave 10 8 1 Operation as an FPI Master The PCP generates FPI read and write transactions in response to execution of PCP FPI instructions The PCP can generate Byte Half word and Word...

Page 708: ...rol Status Registers PRAM and CMEM will generate an FPI bus error All PCP locations can be read in either User or Supervisor Modes All writes must be performed in Supervisor Mode Attempting to write to any PCP location in User Mode will generate an FPI error Some Control and Status Registers are ENDINIT protected There are some additional user selectable FPI write protection options to support Hig...

Page 709: ...y PRAM location including any location in the CSA This means that a channel program may be inadvertently programmed to corrupt the context save region or PRAM storage belonging to another channel causing invalid operation of the corrupted channel when it next executes Generation of an interrupt request to the PCP with a priority number that would cause loading of a context from outside the CSA wil...

Page 710: ...xpected software sequence As each channel executes the PCP maintains an internal count of the number of instructions that have been read from CMEM since the channel started If the watchdog function is enabled by programming PCP_CS CWE 1 and the internal instruction fetch counter reaches the threshold programmed by the user programmed via PCP_CS CWT a PCP Error is generated The threshold setting PC...

Page 711: ...n the normal data access path to the memory The additional storage bits are not easily accessible via the existing data paths causing significant problems where SIST based testing of the memories is required In order to address this problem the PCP includes improved SIST support allowing all PCP memory arrays to be accessedto allow the test and debug of the fault tolerant memory systems The mappin...

Page 712: ...ray Mapping error detection enabled No mapping of the bits is performed and normal operation is possible Note Unlike TriCore the PCP has no hidden memory arrays i e all PCP memories reside permanently in the system address map As a result for the PCP this mode is identical to Normal Operation This mode is retained for compatibility with TriCore SIST 10 11 Memory Integrity Error Detection The PCP i...

Page 713: ... modes of the PCP in the TC1784 10 12 1 DMA Primitives Table 18 describes the two DMA instructions of the PCP Table 24 DMA Transfer Instructions DMA Transfer BCOPY Move block of data value from FPI Bus source address location to FPI Bus destination address location Optionally increment or decrement source and destination pointer registers Optionally repeat instruction until counter CNT1 reaches 0 ...

Page 714: ...s address register content immediate offset LD P Load value from PRAM address location into register PRAM address DPTR register offset LD PI Load value from PRAM address location into register PRAM address DPTR immediate offset LDL IL Load 16 bit immediate value into lower bits 15 0 of register LDL IU Load 16 bit immediate value into upper bits 31 16 of register Store ST F Store register value to ...

Page 715: ...egister conditionally ADD I Add immediate value to register ADD F Add content of FPI Bus address location to register byte half word or word ADD PI Add content of PRAM address location to register Subtract SUB Subtract register from register conditionally SUB I Subtract immediate value from register SUB F Subtract content of FPI Bus address location from register byte half word or word SUB PI Subt...

Page 716: ...ord OR PI Content of PRAM address location OR register MSET PI Set specified bits within a PRAM location Logical Exclusive Or XOR Register XOR register conditionally XOR F Content of FPI Bus address location XOR register byte half word or word XOR PI Content of PRAM address location XOR register Logical Not NOT Invert register 1 s complement conditionally Shift SHL Shift left register SHR Shift ri...

Page 717: ...ister position given by content of a register INB I Insert carry flag into register position given by immediate value Check Bit CHKB Set carry flag depending on value of specified register bit Table 29 Flow Control Instructions Jump JC Jump conditionally to PC short immediate offset address JC A Jump conditionally to immediate absolute address JC I Jump conditionally to PC register offset address ...

Page 718: ... in the instruction is added to the immediate 5 bit offset value encoded in the instruction This address must be properly aligned for the type of data access byte half word or word If it is not aligned the results are undefined Effective Target Address 31 0 R a offset5 where a is the number of the register and offset5 is a 5 bit immediate offset value Instructions using this addressing mode are in...

Page 719: ...ressing Single bits can be addressed in the PCP GPRs or in FPI Bus address locations A 5 bit value indicates the location of a bit in the register specified in the instruction This bit location is either given through an immediate value in the instruction or through the lower five bits of a second register indirect addressing Effective Bit Position 31 0 imm5 Effective Bit Position 31 0 R a 5 0 The...

Page 720: ... I For absolute addressing the actual address in CMEM where program flow is to resume is either an immediate value imm16 in the CMEM location immediately following the jump instruction or it is contained in the lower 16 bits of a register If the value is greater than the PC size implemented an error condition has occurred Effective JUMP Address 15 0 imm16 Effective JUMP Address 15 0 R a Instructio...

Page 721: ...d Additionally see below for High Integrity applications the entire Register content can be ENDINIT protected see below 10 13 1 1 PCP Control Register Protection To allow the PCP to handle system critical tasks it is necessary to ensure that the PCP can operate properly regardless of a failure in another part of the system or the PCP itself This means that it is necessary to protect the Control an...

Page 722: ...The FPI Bus address of a word location pointed to by the Data Pointer R7_DPTR is calculated by the following formula Effective FPI Bus address 31 0 PRAM Base Address DPTR 6 10 13 3 Access to the CMEM from the FPI Bus FPI Bus accesses to the CMEM must always be performed with word accesses byte or half word accesses will result in a bus error When using a channel entry table the FPI Bus address of ...

Page 723: ...Processor PCP User s Manual 10 58 V1 1 2011 05 PCP V2 09 The FPI Bus address of an instruction pointed to by the PCP program counter PC is calculated by the following formula Effective FPI Bus address 31 0 CMEM Base Address PC 1 ...

Page 724: ...alue of the RTA instruction field If RTA 0 the PCP disables further invocations of the current channel through clearing bit R7 CEN and then performs a context save The execution of this channel is stopped at the point of the DEBUG instruction If the DAC instruction field 0 the PCP will continue to operate accepting service requests for other channels as they arise Since the stopped channel was dis...

Page 725: ...o 1 Note The DEBUG instruction must be only used in DEBUG mode otherwise it will generate an IOP error Note If PCP_CS RCB 0 Channel Resume Mode then the channel program will begin executing at whichever PC is restored from the context location CR7 PC If PCP_CS RCB 1 Channel Restart Mode then the channel program is forced to always start at its channel entry table location no matter what the restor...

Page 726: ... the current state of the PCP to the external FPI Bus master Accessing of Control Registers The control registers are accessible by any master via the FPI Bus The control registers must be configured at initialization and then left unaltered This is typically done by the CPU The only setting that can be dynamically modified is the PCP_CS EN bit All other bits must only be modified when PCP_CS EN 0...

Page 727: ...tarts at its base address as shown in Table 39 The address offsets of the PCP registers are described in Table 31 MCA06150 PCP_RPROT PCP_CPROT PCP_PPROT PCP_CLC PCP_CS PCP_SRC0 Control Registers Interrupt Registers PCP_SRC1 PCP_SRC2 PCP_ES PCP_ICR PCP_SRC3 PCP_ITR PCP_ICON PCP_SSR PCP_SRC4 PCP_SRC5 PCP_SRC6 PCP_SRC7 PCP_SRC8 PCP_SRC9 PCP_SRC10 PCP_SRC11 PCP_SMACON PCP_MIECON PCP_MIESTATP PCP_MIEST...

Page 728: ... Interrupt Threshold Control Register 24H U SV 32 SV 32 FPI Reset Page 74 PCP_ICON Interrupt Configuration Register 28H U SV 32 SV 322 FPI Reset Page 75 PCP_SSR Stall Status Register 2CH U SV 32 SV 322 FPI Reset Page 77 PCP_SMACON SIST Mode Access Control Register 40H U SV 32 SV 32 FPI Reset Page 79 PCP_RPROT Register Protection Register 70H U SV 32 SV E 32 FPI Reset Page 80 PCP_CPROT CMEM Protect...

Page 729: ...ol Register 3 F0H U SV 32 SV 322 FPI Reset Page 89 PCP_SRC2 Service Request Control Register 2 F4H U SV 32 SV 322 FPI Reset Page 89 PCP_SRC1 Service Request Control Register 1 F8H U SV 32 SV 322 FPI Reset Page 87 PCP_SRC0 Service Request Control Register 0 FCH U SV 32 SV 322 FPI Reset Page 87 1 The absolute register address is calculated as follows Module Base Address Offset Address shown in this ...

Page 730: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 RES r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCG DIS RES rw r Field Bits Type Description RES 31 16 r Reserved Read as 0 should be written with 0 PCGDIS 15 rw Clock Gating Disable Bit Allows clock gating to be disabled 0B PCP Internal Clock stops when PCP is idle default after reset 1B PCP Internal Clock always runs RES 14 0 r Reserved Read as 0 should be wr...

Page 731: ...ation Register 08H Reset Value 0020 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MODNUM r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID32BIT REVNUM r r Field Bits Type Description MODNUM 31 16 r PCP Identification Number value 0020H ID32BIT 15 8 r 32 bit Module Identification Number Marker value C0H REVNUM 7 0 r PCP Revision Number Implementation specific ...

Page 732: ... rw Error Service Request Number SRPN for interrupt to CPU on an error condition 00H No interrupt request posted default 01H Post an SRPN interrupt to CPU on an error condition 10H Post an SRPN interrupt to CPU on an error condition CWT 23 17 rw Channel Watchdog Threshold 0D Reserved 1D Threshold 16 instructions 127D From 1D up to 127D n the threshold 16 n instructions CWE 16 rw Channel Watchdog E...

Page 733: ...SRPN is greater than MCN an error condition has occurred For example setting PPS to n 3 will give a CSA containing 7 context save regions As channel 0 cannot be used and MCN 6 channels 1 to 6 are allowed PPE 8 rw PRAM Partitioning Enable 0B PRAM is not partitioned 1B PRAM is partitioned Note When partitioned the PRAM is divided into two areas CSA and remainder A PCP error will be generated on an i...

Page 734: ... global control bit and applies to all channels RES 3 r Reserved Read as 0 should be written with 0 RS 2 rh PCP Run Stop Status Flag 0B PCP is stopped or idle default 1B PCP is currently running RES 1 r Reserved Read as 0 should be written with 0 EN 0 rw PCP Enable 0B PCP is disabled for operation default 1B PCP is enabled for operation Note This bit does not enable disable clocks for power saving...

Page 735: ...ddress within the CSA or receipt of an interrupt request that would have caused a context restore from outside the CSA CWD 6 rh Channel Watchdog Triggered Set if the last error debug event was an error generated by a channel program attempting to execute more instructions than allowed by PCP_CS CWT ME 5 rh Memory Error This bit is set if a PCP internal memory error has occurred See Table 10 22 Imp...

Page 736: ...The only way to clear this register is to reset the PCP 10 17 5 PCP Interrupt Control Register PCP_ICR This register controls the operation of the PCP Interrupt Control Unit PICU DCR 2 rh Disabled Channel Request Flag Set if the last error debug event was an error generated by receipt of an interrupt request with an SRPN that attempted to start a disabled PCP channel otherwise clear IOP 1 rh Inval...

Page 737: ...1B One clock per arbitration cycle PARBCYC 25 24 rw Number of Arbitration Cycles Control This bit field controls the number of arbitration cycles used to determine the request with the highest priority It follows the same coding scheme as described for the CPU interrupt arbitration 00B Four arbitration cycles default 01B Three arbitration cycles 10B Two arbitration cycles 11B One arbitration cycle...

Page 738: ...10 73 V1 1 2011 05 PCP V2 09 IE 8 rh Reserved CPPN 7 0 rh Current PCP Priority Number This field indicates the current priority level of the PCP and is automatically updated by hardware on entry into an interrupt service routine Field Bits Type Description ...

Page 739: ...sued to the interrupt queue associated with interrupt bus 0 i e when the number of active port 0 interrupt requests stored in all SRCx registers reaches this value then an interrupt is posted to port 0 with the priority programmed into the ITP field When ITL is programmed to 0 or is the number of SRCx registers that can contain port 0 interrupt requests the threshold warning mechanism is disabled ...

Page 740: ...ts the status of interrupt bus 3 Interrupt bus 3 is always disabled not implemented in the TC1784 IP2E 10 r PCP Interrupt Bus 2 Enable This bit reflects the status of interrupt bus 2 Interrupt bus 2 is always disabled not implemented in the TC1784 IP1E 9 r PCP Interrupt Bus 1 Enable This bit reflects the status of interrupt bus 1 PCP interrupt arbitration bus Interrupt bus 1 is always enabled IP0E...

Page 741: ...ld reflects the TOS associated with interrupt bus 1 PCP interrupt arbitration bus The PCP should use this value in R6 TOS when it wishes to raise an interrupt request to itself the PCP is always connected to interrupt bus 1 P0T 1 0 r PCP Interrupt Bus 0 TOS Mapping This field reflects the TOS associated with interrupt bus 0 CPU interrupt arbitration bus The PCP should use this value in R6 TOS when...

Page 742: ...Number This field shows the channel number of the channel that was executing when the last or present stall condition occurred This field can only be cleared by a reset ST 15 rh PCP Stalled Status This bit shows the stalled status of the PCP 0B PCP is not stalled 1B PCP is stalled RES 14 10 r Reserved Read as 0 STOS 9 8 rh PCP Stalled Type of Service This field shows the Type Of Service to which a...

Page 743: ...78 V1 1 2011 05 PCP V2 09 SSRN 7 0 rh PCP Stalled Service Request Number This field shows the Service Request Number that was being posted when the last or present stall condition occurred This field can only be cleared by a reset Field Bits Type Description ...

Page 744: ...0 9 8 7 6 5 4 3 2 1 0 RES CMEM PRAM r rw rw Field Bits Type Description RES 31 4 r Reserved returns 0 if read should be written with 0 CMEM 3 2 rw CMEM SIST mode access control 00B Normal Operation No Mapping 01B Data Array Mapping no error detection correction 10B Check Array Mapping no error detection correction 11B Data Array Mapping error detection correction enabled PRAM 1 0 rw PRAM SIST mode...

Page 745: ... Register 70H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN RES rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES r Field Bits Type Description EN 31 rw Register Protection Enable 0B Registers are not protected and can be written at any time 1B Registers are protected and can only be written when ENDINT is 0 RES 30 0 r Reserved returns 0 if read should be written with 0 ...

Page 746: ...This register is ENDINIT protected PCP_CPROT CMEM Protection Register 74H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN RES rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES r Field Bits Type Description EN 31 rw Register Protection Enable 0B CMEM is not protected and can be written at any time 1B CMEM is protected and can not be written RES 30 0 r Reserved returns 0 if re...

Page 747: ...0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN ENI RES PCA T PTHRES rw rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSIZE FBASE rw rw Field Bits Type Description EN 31 rw PRAM Protection Enable for FPI Writes 0B PRAM is not protected and can be written via FPI at any time 1B All PRAM outside the Open Window is protected and can not be written via FPI PRAM inside the Open Window remai...

Page 748: ...bled the entire Context Region will be protected against PCP PRAM write instructions regardless of the Protection settings or whether the channel is Protected or not RES 29 25 r Reserved Returns 0 if read Should be written with 0 PCAT 24 rw Protected Channels Above Threshold When ENI above is 0 this bit has no effect When ENI is 1 this bit defines whether the Channel number defined in the PTHRES r...

Page 749: ...Window the entire PRAM subject to PRAM Partitioning can be written by the use of PRAM write instructions by any Channel 1D 256 Bytes i e the lowest 64 words of PRAM are protected against PRAM write instructions executed by non protected Channels 255D 255 256 Bytes Note Use of an eight bit field allows for the maximum PRAM size currently supported by the architecture 64Kbytes Where a PCP is impleme...

Page 750: ...via the FPI bus the lowest 64 words of PRAM are protected against FPI Writes 254D Base of PRAM 254 256 Bytes 255D The entire PRAM is protected against FPI writes Note Use of an eight bit field allows for the maximum PRAM size currently supported by the architecture 64Kbytes Where a PCP is implemented with a smaller PRAM setting an Open Window base above the actual top of PRAM will result in the en...

Page 751: ...ption EN 31 rw FPI Protection Enable 0B The addresses of outgoing FPI writes are not checked 1B During execution of an instruction that generates an FPI write a check is performed to ensure that the target address is within the programmed allowed address range If the address is not to an allowed address then an FPI write is not issued and the PCP exits the current Channel with an IOP error EX 30 r...

Page 752: ...indow size Bit 23 maps to bit 31 of the FPI byte address The appropriate number of subsequent bits defines the aligned address according to the window size e g when using a 1Kbyte window the lower 2 bits of this field are treated as zero regardless of their actual value in order to obtain the base address of the window PCP_SRCm m 0 1 PCP Service Request Control Register m FCH m 4H Reset Value 0000...

Page 753: ...ways read as 1 enabled TOS 11 10 r PCP Node m Type of Service State Always read as 00B This means TOS is associated with interrupt bus 0 CPU interrupt arbitration bus RES 9 8 r Reserved Read as 0 SRPN 7 0 rh PCP Node m Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 CPU interrupt arbitration bus Default after res...

Page 754: ... r r r rh Field Bits Type Description RES 31 14 r Reserved Read as 0 SRR 13 rh PCP Node m Service Request Flag 0B No service requested default 1B Valid active service requested SRE 12 r PCP Node m Service Request Enable Always read as 1 enabled TOS 11 10 r PCP Node m Type of Service State Always read as 01B This means TOS is associated with interrupt bus 1 PCP interrupt arbitration bus RES 9 8 r R...

Page 755: ... 7 6 5 4 3 2 1 0 RES SRR SRE 1 TOS RES SRPN r rh r rw r rh Field Bits Type Description RES 31 14 r Reserved Read as 0 Should be written with 0 SRR 13 rh PCP Node m Service Request Flag 0B No service requested default 1B Valid active service requested SRE 12 r PCP Node m Service Request Enable Always read as 1 enabled TOS 11 10 rw PCP Node m Type of Service State Control TOS value depends on the in...

Page 756: ...s 00H PCP_SRCm m 9 11 PCP Service Request Control Register m FCH m 4H Reset Value 0000 1400H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RES RRQ RES SRCN r rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES SRR SRE 1 TOS 01B RES SRPN r rh r r r rh Field Bits Type Description RES 31 29 r Reserved Read as 0 RRQ 28 rh PCP Node m Channel Restart Request Set when this service request register n cont...

Page 757: ...d SRE 12 r PCP Node m Service Request Enable Always read as 1 enabled TOS 11 10 r PCP Node m Type of Service State Always read as 01B This means TOS is associated with interrupt bus 1 PCP interrupt arbitration bus RES 9 8 r Reserved Read as 0 SRPN 7 0 rh PCP Node m Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 ...

Page 758: ... of flags Additionally many instructions including arithmetic and many flow control instructions are conditionally executed The descriptions of the PCP instructions are based on the following conventions Shift left or right respectively Indirect access based on contents of brackets de reference immNN Immediate value encoded into an instruction with width NN offsetNN Address offset immediate value ...

Page 759: ...ion of the Flags held in R7 See Table 33 Table 33 Condition Codes Description CONDCA B Test Flag Bits Code Mnemonic Unconditional A B 0H cc_UC Zero Equal A B Z 1 1H cc_Z Not Zero Not Equal A B Z 0 2H cc_NZ Overflow A B v 1 3H cc_V Carry Unsigned Less Than Check Bit True A B C 1 4H cc_C cc_ULT Unsigned Greater Than A B C OR Z 0 5H cc_UGT Signed Less Than A B N XOR V 1 6H cc_SLT Signed Greater Than ...

Page 760: ...e Figure 10 2 on Page 99 For COPY operation see Figure 10 1 on Page 98 Perform the number of transfers specified by CNT0 then proceed to next instruction Perform the number of transfers specified by CNT0 then decrement CNT1 and proceed to next instruction Perform the number of transfers specified by CNT0 then decrement CNT1 Repeat until CNT1 0 then proceed to next instruction Reserved CNT0 CNT0 00...

Page 761: ...o channel program Start EP 0 assumes that a Channel Entry Table exists in the base of CMEM Failure to provide such a table will cause improper operation Set the PC to the address contained in NextPC next instruction address INT INT 0 INT 1 Interrupt Control No Interrupt INT 1 AND cc_B True means Issue Interrupt RTA RTA 0 RTA 1 Action on Debug Exit Stop channel program from accepting new service re...

Page 762: ...it Reserved SRC SRC 00B SRC 01B SRC 10B 11B Source Address Pointer Control No Change SRC Post Increment by Size SRC Post Decrement by Size SRC Reserved ST ST 0 ST 1 Stop Channel Continue channel execution leave channel program enabled Stop Channel Execution perform actions according to RTA setting see above Table 34 Instruction Field Definitions cont d Symbol Syntax Description ...

Page 763: ...ounter Operation for COPY Instruction Figure 10 1 shows the flow of a COPY instruction Figure 10 1 Counter Operation for COPY Instruction MCA06147 DATA Transfer COPY Instruction t_count 0 Next Instruction t_count CNT0 t_count t_count 1 CNC CNT1 CNT1 1 CNT1 CNT1 1 CNT1 0 no yes 00 10 01 yes no ...

Page 764: ... 3 Counter Operation for BCOPY Instruction Figure 10 2 shows the flow of a BCOPY instruction Figure 10 2 Counter Operation for BCOPY Instruction MCA06148 DATA Transfer Block size determined by CNT0 field BCOPY Instruction Next Instruction CNC CNT1 CNT1 1 CNT1 CNT1 1 CNT1 0 00 10 01 yes no ...

Page 765: ...e instructions within the sequence DSTEP must use the same register for dividend and the same register for divisor as used in the preceding DINIT instruction The first instruction of any multiply sequence must be the MINIT initialization instruction Any additional instructions other than DINIT or DSTEP may also be used within the sequence as long as they do not modify any of the registers used for...

Page 766: ... false no operation is performed Operation if CONDCA True then R b R b R a else NOP Flags N Z V C ADD I Syntax ADD I Ra imm6 Description Add the zero extended immediate value imm6 to the contents of register Ra place the result in Ra Operation R a R a zero_ext imm6 Flags N Z V C ADD F Syntax ADD F Rb Ra Size Description Add the contents of the address location specified by the contents of register...

Page 767: ...b AND R a else NOP Flags N Z AND F Syntax AND F Rb Ra Size Description Perform a bit wise logical AND of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b AND zero_ext FPI R a Flags N Z AND PI Syntax AND PI Ra offset6 Description Perform a bit wise logical AND of the contents of the PRAM location s...

Page 768: ... to FPI Bus destination location Source location is pointed to by the contents of register R4 destination location is pointed to by the contents of register R5 Options see also Table 34 at Page 95 Source pointer SRC Increment decrement or unchanged Destination pointer SRC Increment decrement or unchanged Counter control CNC see Table 34 Block size value CNT0 see Table 34 Operation temp zero_ext FP...

Page 769: ... is equal to the specified test value S C then set the carry flag R7 C else clear the carry flag Operation if R a imm5 S C then R7_C 1 else R7_C 0 Flags C CLR Syntax CLR Ra imm5 Description Clear bit imm5 of register Ra to 0 Operation R a imm5 0 Flags None CLR F Syntax CLR F Ra imm5 Size Description Clear bit imm5 of the address location specified through the contents of register Ra to 0 This inst...

Page 770: ...ng to the result of the subtraction discard the subtraction result Operation R7_FLAGS Flags R a zero_ext imm6 Flags N Z V C COMP F Syntax COMP F Rb Ra Size Description Subtract the contents of the address location specified by the contents of register Ra from the contents of register Rb set the flags in register R7 according to the result of the subtraction discard the subtraction result Operation...

Page 771: ... by the contents of register R5 Options see also Table 34 on Page 95 Source pointer SRC Increment decrement or unchanged Destination pointer SRC Increment decrement or unchanged Counter control CNC see Table 34 Counter 0 reload value CNT0 see Table 34 Data transfer width SIZE byte half word word pointers are incremented decremented based upon SIZE Operation temp zero_ext FPI R 4 value loaded and e...

Page 772: ...xit DEBUG Syntax DEBUG EDA DAC RTA SDB cc_B Description Conditionally cause a debug event if condition CONDCB is true Optionally stop channel execution SDB 1 and or generate an external debug event EDA 1 Operation if CONDCB True then if EDA 1 then activate BRK_OUT pin if SDB 1 then if RTA 0 then R7_CEN 0 disable further channel invocation else PC PC 1 endif save_context idle endif if DAC 1 PCP_CS ...

Page 773: ...bes the DINIT instruction of the PCP DINIT Syntax DINIT R0 Rb Ra Description Initialize Divide logic ready for divide sequence Rb Ra and Clear R0 If value of Ra is 0 then set V to flag divide by 0 error otherwise clear V If value of Rb is 0 and value of Ra is not 0 then set Z to flag a zero result otherwise clear Z Operation R0 0 Flags Z V ...

Page 774: ...ules specified on Page 100 are followed then the above description and operation are correct Failure to adhere to these rules will yield undefined results DSTEP Syntax DSTEP R0 Rb Ra Description Perform 1 step eight bits of an unsigned 32 by 32 bit divide Rb Ra Shift R0 left by 8 bits copy the most significant byte of Rb into LS byte of R0 Shift Rb left by 8 bits and add R0 divided by Ra Load R0 w...

Page 775: ...t the channel code entry point in Channel Resume Mode to either the address of the next instruction EP 1 or to the start address of the channel EP 0 The EXIT instruction is finished with a context save operation The EP option is only in effect when Channel Resume operation is globally selected through PCP_CS RCB 0 If PCP_CS RCB 1 Channel restart mode is selected for all channels and the EP field o...

Page 776: ... is true then insert the carry flag R7 C into register Rb at the bit position specified through bits 4 0 of register Ra If CONDCA is false no operation is performed Operation if CONDCA True then R b R a 4 0 R7_C else NOP Flags None INB I Syntax INB I Ra imm5 Description Insert the carry flag R7 C into register Ra at the bit position specified through the immediate value imm5 Operation R a imm5 R7_...

Page 777: ... address16 into the PC and jump to that address If CONDCB is false no operation is performed Operation if CONDCB True then PC address16 else NOP Flags None JC I Syntax JC I Ra cc_B Description If CONDCB is true then add the value specified by Ra 15 0 to the contents of the PC and jump to that address Value Ra 15 0 is treated as a signed 16 bit number If CONDCB is false no operation is performed Op...

Page 778: ...ffset10 Flags None LD F Syntax LD F Rb Ra Size Description Load the zero extended contents of the address location specified by the contents of register Ra into register Rb Operation R b zero_ext FPI R a Flags N Z LD I Syntax LD I Ra imm6 Description Load the zero extended value specified by imm6 into register Ra Operation R a zero_ext imm6 Flags N Z LD IF Syntax LD IF Ra offset5 Size Description ...

Page 779: ...six bits and the zero extended 6 bit value Ra 5 0 into register Rb If condition CONDCA is false no operation is performed Operation if CONDCA True then R b PRAM DPTR 6 zero_ext R a 5 0 else NOP Flags N Z LD PI Syntax LD PI Ra offset6 Description Load the contents of the PRAM location specified by the addition of contents of the PRAM Data Pointer shifted left by six bits and the zero extended 6 bit...

Page 780: ... register Ra bits 15 0 Bits 31 16 of register Ra are unaffected Value imm16 is treated as an unsigned 16 bit number Operation R a 15 0 imm16 Flags N Z LDL IU Syntax LDL IU Ra imm16 Description Load the immediate value imm16 into the upper bits of register Ra bits 31 16 Bits 15 0 of register Ra are unaffected Operation R a 31 16 imm16 Flags N Z MINIT Syntax MINIT R0 Rb Ra Description Initialize Mul...

Page 781: ...ve Register to Register This section describes the MOV instruction of the PCP MOV Syntax MOV Rb Ra cc_A Description If condition CONDCA is true then move the contents of register Ra into register Rb If CONDCA is false no operation is performed Operation if CONDCA True then R b R a else NOP Flags N Z ...

Page 782: ...Shift R0 left by 8 bits Add Ra multiplied by the least significant 8 bits of Rb to R0 If value of R0 is zero then set Z to signal zero result else clear Z Operation Rb Rb 8 Rb 24 R0 R0 8 Rb 0xff Ra Flags Z MSTEP64 Syntax MSTEP64 R0 Rb Ra Description Perform an unsigned multiply step using eight bits of data taken from Rb keeping 40 bits of a potential 64 bit result Add Ra multiplied by the least s...

Page 783: ...DCA is true then move the 2 s complement of the contents of register Ra into register Rb If CONDCA is false no operation is performed Operation if CONDCA True then R b R a else NOP Flags N Z V C NOP Syntax NOP Description No operation The NOP instruction puts the PCP in low power operation Operation no operation Flags None NOT Syntax NOT Rb Ra cc_A Description If condition CONDCA is true then move...

Page 784: ... OR R a else NOP Flags N Z OR F Syntax OR F Rb Ra Size Description Perform a bit wise logical OR of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b OR zero_ext FPI R a Flags N Z OR PI Syntax OR PI Ra offset6 Description Perform a bit wise logical OR of the contents of the PRAM location specified ...

Page 785: ...nts of the PRAM location specified by the addition of contents of the PRAM Data Pointer shifted left by six bits and the zero extended 6 bit value offset Write the result back to the PRAM location Operation R a R a AND PRAM DPTR 6 offset6 PRAM DPTR 6 offset6 R a Flags N Z MSET Syntax MSET PI Ra offset6 Description Perform an OR of the contents of the specified register with the contents of the PRA...

Page 786: ...is true then find the bit position of the most significant 1 in register Ra and put the number into register Rb The bit location 31 0 is encoded as a 5 bit number stored in Rb 4 0 If the contents of Ra is zero bit Rb 5 is set while all other bits in Rb are cleared If CONDCA is false no operation is performed Operation if CONDCA False then NOP else if R a 0 then R b 0x20 else R b bit_pos most_signi...

Page 787: ...ified through the 5 bit value imm5 The values defined for imm5 are 1 2 4 and 8 The carry flag R7 C is set to the last bit shifted out of bit 31 of register Ra Operation tmp R a R a R a imm5 imm5 1 2 4 8 R7_C last bit shifted out of R a tmp tmp 32 imm5 R a tmp OR R a Flags N Z RR Syntax RR Ra imm5 Description Rotate the contents of register Ra to the right by the number of bit positions specified t...

Page 788: ... bit imm5 of the address location specified through the contents of register Ra to 1 This instruction is executed using a locked read modify write FPI Bus transaction Operation FPI R a imm5 1 Flags None SHL Syntax SHL Ra imm5 Description Shift the contents of register Ra to the left by the number of bit positions specified through the 5 bit value imm5 The values allowed for imm5 are 1 2 4 and 8 Th...

Page 789: ...tion describes the SHR instruction of the PCP SHR Syntax SHR Ra imm5 Description Shift the contents of register Ra to the right by the number of bit positions specified through the 5 bit value imm5 The values allowed for imm5 are 1 2 4 and 8 Zeros are shifted in from left Operation R a R a imm5 imm5 1 2 4 8 Flags N Z ...

Page 790: ...e Size is byte or half word the data is stored with the internal LSB bit 0 properly aligned to the correct FPI Bus byte or half word lane Operation FPI R a zero_ext imm5 R 0 Flags None ST P Syntax ST P Rb Ra cc_A Description If condition CONDCA is true then store the contents of Rb to the PRAM address location specified by the addition of the contents of the PRAM Data Pointer shifted left by six b...

Page 791: ...nded immediate value imm6 from the contents of register Ra place the result in Ra Operation R a R a zero_ext imm6 Flags N Z V C SUB F Syntax SUB F Rb Ra Size Description Subtract the zero extended contents of the address location specified by the contents of register Ra from the contents of register Rb place the result in Rb Operation R b R b zero_ext FPI R a Flags N Z V C SUB PI Syntax SUB PI Ra ...

Page 792: ... bit 0 properly aligned to the correct FPI byte or half word lane The exchange is done via a locked FPI bus transfer Operation temp R b R b zero_ext FPI R a FPI R a temp Flags N Z XCH PI Syntax XCH PI Ra offset6 Description Exchange contents of R a and PRAM DPTR 6 offset6 Note The exchange is un interruptible and locks out external accesses it will not be interrupted by any external FPI bus master...

Page 793: ... b XOR R a else NOP Flags N Z XOR F Syntax XOR F Rb Ra Size Description Perform a bit wise logical Exclusive OR of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b XOR zero_ext FPI R a Flags N Z XOR PI Syntax XOR PI Ra offset6 Description Perform a bit wise logical Exclusive OR of the contents of ...

Page 794: ...instruction is shown with the flags that it updates Table 35 Flag Updates Instruction CN1Z V C N Z ADD yes yes yes yes AND yes yes BCOPY yes1 CHKB yes CLR COMP yes yes yes yes COPY yes1 DEBUG DINIT yes yes DSTEP yes EXIT yes1 INB JC JL LD yes2 yes LDL yes yes MCLR yes yes MSET yes yes MOV yes yes NEG yes yes yes yes NOP NOT yes yes OR yes yes PRI yes3 yes RR yes yes RL yes yes yes SET ...

Page 795: ...an execution time is stated for an FPI instruction this is always a minimum value A number of FPI instructions must wait for the completion of an FPI transaction or transactions When running in 2 1 mode each FPI clock cycle consists of two core clock frequencies Where this applies the cycle count is shown with an FPI superscript designation e g 3FPI In addition there may be an additional single co...

Page 796: ...in for FPI read 3 OR F 8 min 5 int 3FPI min for FPI read 3 ST F 5 min 2 int 3FPI min for FPI write 3 SUB F 8 min 5 int 3FPI min for FPI read 3 XCH F 8 min 4 int 4FPI min for FPI read and write 3 XOR F 8 min 5 int 3FPI min for FPI read 3 PRAM Access ADD PI 2 AND PI 2 COMP PI 2 LD PI 2 MCLR PI 6 MSET PI 6 OR PI 2 ST PI 4 SUB PI 2 XCH PI 5 XOR PI 2 Arithmetic Conditional ADD 1 AND 1 COMP 1 INB 1 Tabl...

Page 797: ...B I 1 LD I 1 LDL IL 1 LDL IU 1 RL 1 RR 1 SET 1 SHL 1 SHR 1 SUB I 1 FPI Immediate Access CLR F 8 min 4 int 4FPI min for locked FPI RMW Read Modify Write 4 LD IF 8 min 5 int 3FPI min for FPI read 3 SET F 8 min 4 int 4FPI min for locked FPI RMW Read Modify Write 4 ST IF 5 min 2 int 3FPI min for FPI write 5 Table 36 Instruction Timing cont d Instruction Number of Clock Cycles Comments Notes ...

Page 798: ...rite with 0 wait cycles 1 cycle bus arbitration and assuming 1 1 clocking mode 5 Cycles 2 internal 3 minimum for FPI write with 0 wait cycles 1 cycle for bus arbitration and assuming 1 1 clocking mode Time starts after any previous ST F instruction has completed 6 32 32 bit divide requires instruction DINIT JC 4 DSTEP 1 4 2 4 10 45 cycles 8 32 bit divide requires instruction RR DINIT JC DSTEP 1 1 ...

Page 799: ...oop counter Perform the number type of transfers appropriate to the instruction then decrement CNT1 Repeat until CNT1 0 then proceed to next instruction If R 7 IEN True interrupts enabled the instruction may be interrupted at the end of each iteration of the outer loop 11 N A error CNT0 Internal Loop Counter Block Size Control Internal Loop Counter for COPY 000 Perform a sequence of 8 read write t...

Page 800: ...Issue interrupt 0 No 1 Yes if CONDCB True RTA Return to This Address 0 The channel is disabled R7 CEN 0 and the PC value stored in the context is NextPC 1 The channel remains enabled and the PC value stored in the context is NextPC 1 SDB Stop on Debug 0 Continue running if Debug Event Triggered 1 Stop PCP Channel if Debug Event Triggered Set Clr Set Clear 0 Check for Clear 0 1 Check for Set 1 SIZE...

Page 801: ... fmt Ins tr DST SRC CNC CNT0 Size NOP 0 0 COPY 0 1 ST INT EP EC CONDC B EXIT 1 0 Condition for Interrupt fmt Ins tr DST SRC CNC CNT0 BCOPY 1 1 1 FPI Instruction R b R a Size ADD F 0 SUB F 1 COMP F 2 error 3 error 4 AND F 5 error 6 OR F 7 XOR F 8 LD F 9 ST F A XCH F B error C error D error E error F 2 PRAM Instruction R a Offset 6 bit ADD PI 0 SUB PI 1 COMP PI 2 ...

Page 802: ...PI 5 MSET PI 6 OR PI 7 XOR PI 8 LD PI 9 ST PI A XCH PI B error C error D error E error F 3 Arithmetic Instruction R b R a CONDC A ADD 0 SUB 1 COMP 2 NEG 3 NOT 4 AND 5 error 6 OR 7 XOR 8 LD P 9 ST P A error B MOV C INB D PRI E error F Table 38 Instruction Encoding cont d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 803: ...LDL IU 8 following imm16 instruction LDL IL 9 following imm16 instruction SET A CLR B LD I C INB I D CHKB E S C error F 5 FPI Immediate Instruction Siz e1 R a Siz e0 Immediate 5 bit error 0 error 1 error 2 SET F 3 CLR F 4 LD IF 5 ST IF 6 error 7 6 Complex Maths op2 Instruction R b R a Reserved DINIT 0 DSTEP 1 Table 38 Instruction Encoding cont d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 804: ... error B error C error D error E error F 7 JUMP op2 Instr Offset 10 bit JL 0 0 0 op2 Instr CONDC B Offset 6 bit JC 0 0 1 JC A 0 1 0 Absolute Destination in next 16 bits error 0 1 1 op2 Instr CONDCB R a JC I 1 0 0 JC IA 1 0 1 error 1 1 0 op2 Instr CONDCB DA C RT A ED A SD B DEBUG 1 1 1 Table 38 Instruction Encoding cont d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 805: ...el program is forced to always start at its Channel Entry Table location regardless of the PC value stored in the CSA If PCP_CS RCB 0 then the channel program will simply begin executing at whatever PC value is restored in the context R7 PC It is important to be aware of the implications of these two approaches on how CMEM should be configured and what the initial value of the PC should be in the ...

Page 806: ... channel start address ST IF base 0x8 SIZE 32 output note from R0 JC CH16 cc_UC loop back before exit Note that when the channel program is originally configured by the programmer the PC field in the R7 context of this channel program should also be set to the address of the START label Similarly an interrupt driven state machine can be created by exiting with the next PC value pointing to the sta...

Page 807: ...ded in the context must be handled explicitly by channel programs since these are not saved and restored with the context of the interrupted channel program Channel programs may still use all registers reliably Channel programs can be so designed that they either ignore the values in unsaved registers or use those registers to store constants that no channel program changes Hence they never need t...

Page 808: ...rogram continue operation in the background It will also always be superseded by any higher priority tasks The third approach uses a channel program to dispatch other non interrupt driven channel programs in an arbitrary order determined by the channel program dispatcher In this way multiple tasks could be continuously operated without over using the PCP service request queue This approach would b...

Page 809: ...destination if R3 4 JL case_5 destination if R3 5 10 20 7 Simple DMA Operation A simple interrupt driven DMA requires at least the Small Context Model to operate properly Its operation is consists of three stages The device interrupts the PCP to indicate it can receive or provide data The PCP moves the amount of data it is programmed to move The PCP eventually finishes and interrupts the CPU to no...

Page 810: ...the COPY instruction except that it uses the FPI Burst mode to perform the transfers rather than performing individual reads writes As for the COPY instruction the FPI Bus is locked between the burst read and burst write to ensure that a valid set of data is transferred The BCOPY instruction allows support of all burst sizes supported by FPI Burst Mode except a burst size of 1 i e 2 4 or 8 words T...

Page 811: ...ly The programmer of the PCP may lock PCP_CS by setting PCP_CS EIE 1 When the global ENDINIT bit is set the PCP_CS register will no longer be writable and attempting to do so will cause an FPI Bus error An error condition will result in an interrupt being sent to the local FPI Bus master The targeted interrupt service routine must be capable of dealing with the cause as recorded in PCP_ES and if r...

Page 812: ...l 0 would normally be unused That is PRAM Base PRAM Base 1 channel In addition for Small Context the least significant 4 32 bit entries are unused and for Minimum Context the least significant 2 32 bit entries are un used These unused entries should not be used by channel programs If EP 0 is used or if PCP_CS RCB 1 a Channel Entry Table must be provided at the base of CMEM If there is a plan to us...

Page 813: ...nded Service Request Nodes PCP_SRC9 PCP_SRC10 and PCP_SCR11 that allow storage of suspended channel interrupt requests This allows interrupt nesting to a depth of four This limit on the nesting depth carries the danger that a high priority service request will not be serviced because the PCP s interrupt nesting depth has been exceeded It is recommended that a four level grouping scheme should be a...

Page 814: ...If the restrictions on the use of the DSTEP instruction specified on Page 100 are adhered to the above condition will always be met and this description of the instruction is correct Failure to adhere to these conditions will lead to invalid results which are outside the scope of this document During execution of a divide sequence Rb is used both to compile the final divide result and to hold the ...

Page 815: ...2 Initialize ready for the divide JC HANDLE_DIVIDE_BY_ZERO cc_V V flag was set so jump to divide by zero error handler DSTEP R4 R2 DSTEP instruction 1 8 8 bit divide After this sequence R4 holds the result R0 the remainder and R2 is unchanged Note that the above example is specified as being a 8 32 bit divide rather than an 8 8 bit divide see comments above 10 21 5 Implementing Multiply Algorithms...

Page 816: ...ing a 32 bit result R3 32 bit R2 16 bit RR R2 8 Perform two 8 bit rotations RR instructions to get original least significant 16 bits into most significant 16 bits RR R2 8 MINIT R2 R3 Initialize ready for multiply MSTEP32 R2 R3 Perform two MSTEP32 instructions 16 bit multiply MSTEP32 R2 R3 After this sequence R0 holds the result R2 is left unchanged right rotated by two RR instructions then left r...

Page 817: ...upervisor mode 10 22 2 BCOPY Instruction In the TC1784 the BCOPY instruction can be used to perform burst transfers 2 4 or 8 words with DMI memories Local data RAM and the PCP memories Other internal and external memories can be accessed using a burst size of 2 words only CNT0 10B Table 39 PCP General Block Address Map PCP Address Map Address Range Access Mode Size Read Write Reserved F004 0000H F...

Page 818: ...ed if at least one of these TC1784 reset sources becomes active Watchdog Timer Reset Software Reset Hardware Reset Power on Reset Each of these reset sources forces a hardware reset of the functional blocks within the PCP module The effect of hard reset within the PCP is to Halt any operating channel Reset all control registers to their reset values Reset the PCP Processor Core to its default stat...

Page 819: ...er DMA_ADRCR1 0x The DMA channels are supporting now transactions with data moves 32 KB with wrap around after 32 KB bit fields CHCR TREL and CHSR TCOUNT are extended to 10 bit See Page 11 86 Page 11 86 and Page 11 90 Page 11 90 See also DMA_ADRCR CBLS CBLD Page 11 93 Page 11 93 As a central module of the AudoFuture system on chip architecture the DMA is now directly connected to the LMB with an o...

Page 820: ...DMA request wiring matrix was re defined Page 11 102 Adapted the DMA access protection assignment to the AudoFuture address map Page 11 112 The address protection sub ranges are mapped to OVRAM PCP PRAM LDRAM and SPRAM In general the DMA control registers where adapted to the new structure one FPI master interface and one LMB master interface instead of two FPI master interfaces A figure with the ...

Page 821: ...ipheral interface provides a connection to the Cerberus module Micro Link Interface module and other DMA related devices Memory Checker module in the TC1784 Clock control address decoding DMA request wiring and DMA interrupt service request control are implementation specific and are managed outside the DMA controller kernel The index m in the following block diagram refers to the DMA Sub Block nu...

Page 822: ...nnel after a predefined number of DMA transfers Continuous Mode DMA channel remains enabled after a predefined number of DMA transfers DMA transaction can be repeated Programmable address modification Two shadow register modes with w o automatic reset and direct write access Full 32 bit addressing capability of each DMA channel 4 Gbyte address range Data block move 32 Kbyte per DMA transaction Cir...

Page 823: ...ata destination Data is temporarily stored in the DMA controller The data widths of read move and write move are always identical 8 bit 16 bit or 32 bit Data assembly or disassembly is not supported Figure 11 2 DMA Definition of Terms DMA Transfer A DMA transfer can be composed of 1 2 4 8 or 16 DMA moves DMA Transaction A DMA transaction is composed of several at least one DMA transfers The Transf...

Page 824: ...e functionality Typically the parallel occurrence of DMA requests and interrupts requests for DMA channels is possible Therefore the interrupt control unit and the DMA controller can react independently to interrupt and DMA requests that have been generated by one source Figure 11 3 DMA Principle The DMA controller mainly consists of two DMA Sub Blocksand a Bus Switch Once configured the DMA Sub B...

Page 825: ...nt of data has been transferred a new DMA transaction should be initiated to deliver further ASC data into another memory buffer While the destination address register is updated during a running DMA transaction with the actual destination address a shadow mechanism allows programming of a new destination address without disturbing the content of the destination address register In this case the n...

Page 826: ...H if the shadow register write enable bit is set to 0 ADRCRmn SHWEN 0 In this case ADRCRmn SHWEN 0 the software can check by reading the shadow address register whether or not the shadow transfer has already taken place Only one address register can be shadowed while a transaction is running because the shadow register can only be assigned either to the source or to the destination address registe...

Page 827: ...saction No reload of address or counter will be done if TCOUNT is not equal to 0 The reprogramming of channel specific values except for the selected address shadow register should be avoided while a DMA channel is active MCA06152 Write new source address to address of SADRmn no New transaction started ADRCRmn SHCT 01B yes no Content of SHADR0n is transferred into SADRmn If ADRCRmn SHWEN 0 then SH...

Page 828: ...ion Transfer count tc2 and source address sa2 Source address sa2 is buffered in SADRmn and transferred to SADRmn when the new DMA transaction is started at 2 At this time transfer count tc2 is also transferred to CHSRmn TCOUNT Pls note that the shadow address register is only reset by hardware to 0000 0000H as shown in this example if the write enable bit is set to 0 ADRCRmn SHWEN 0 MCT06153 tc1 t...

Page 829: ... positive edge detector as the DMA channels requires single pulse requests Hardware requests are enabled disabled by status bit TRSR HTREmn HTREmn can be set reset by software or by hardware in Single Mode at the end of a DMA transaction A software request can be generated by setting bit STREQ SCHmn MCA06154c TRSR Transfer Request To Channel Arbiter HTREmn STREQ SCHmn TRSR CHmn Set Reset CHCRmn RR...

Page 830: ...equest signals typically generated by on chip peripheral units In hardware controlled Single Mode a DMA channel mn becomes disabled by hardware after the last DMA transfer of its DMA transaction In hardware controlled Continuous Mode a DMA channel mn remains enabled after the last DMA transfer of its DMA transaction In hardware and software controlled mode a DMA request signal can be configured to...

Page 831: ... operations CHCRmn RROAT 0 STREQ SCHmn 1 repeated for each DMA transfer When CHCRmn RROAT 0 TRSR CHmn becomes reset after each DMA transfer of the DMA transaction and a new software request writing STREQ SCHmn 1 must be generated for starting the next DMA transfer Figure 11 7 Software Controlled Mode Operation m 0 1 TR0 TR1 TRn tc 1 tc initial transfer count TR0 TR1 0 tc 1 0 tc tc 1 MCT06155 TR0 T...

Page 832: ...R HTREmn 1 Whenever the hardware request CHmn_REQ becomes active the value of CHCRmn TREL is loaded into CHSRmn TCOUNT and the DMA transaction is started by executing its first DMA transfer After each DMA transfer TCOUNT becomes decremented and next source and destination addresses are calculated When TCOUNT reaches the 0 DMA channel 0n becomes disabled and status flags TRSR CHmn and TRSR HTREmn a...

Page 833: ...tored in the channel register set of DMA channel mn is started each time when CHSRmn TCOUNT 0 at the end of the DMA transaction No software re enable for a hardware request at CHmn_REQ is required MCT06156 tc initial transfer count tc initial transfer count CHCRmn RROAT 1 CHCRmn RROAT 0 TR0 TR1 TRn tc 1 TR0 TR1 0 tc tc 1 0 1 tc TR0 tc 1 tc TR1 TRn 1 TRn 0 0 2 1 tc TR0 TRSR HTREmn CHmn_REQ INT trig...

Page 834: ...e 11 9 Transaction Start by Software Continuation by Hardware m 0 1 11 2 4 4 Error Conditions The bus error flag ERRSR FPIER indicates an FPI Bus error SPB that occurred during a source move read or write of a DMA module transaction The bus error flag ERRSR LMBER indicates an LMB Bus error that occurred during a source move read or write of a DMA module transaction The source error flags ERRSR MEm...

Page 835: ...CHRST CHmn is set to 1 Bits TRSR HTREmn TRSR CHmn ERRSR TRLmn INTSR ICHmn INTSR IPMmn WRPSR WRPDmn WRPSR WRPSmn CHSRmn LXO and bit field CHSRmn TCOUNT are reset Source and destination address register will be set to the wrap boundary SHADRmn will be cleared All automatic functions are stopped for channel mn A user program must execute the following steps for resetting a DMA channel 1 If hardware r...

Page 836: ...nation addresses are calculated independently of each other The following address calculation parameters can be selected The address offset which is a multiple of the selected data width The offset direction addition subtraction or none unchanged address Control bits in address control register ADRCRmn determine how the addresses are incremented decremented Further the data width as defined in CHC...

Page 837: ...tion memory with decrementing destination addresses offset of 08H In Figure 11 12 16 bit half words are transferred from a source memory with an incrementing source address offset of 02H to a destination memory with incrementing destination addresses offset of 04H MCA06159 ADRCRmn Parameters SMF 011B INCS 1 Source Memory Destination Memory D1 D0 31 0 15 16 DMA Moves 00H D1 31 0 15 16 04H 08H 0CH 1...

Page 838: ...izes of the circular buffers can be 2CBLS or 2 CBLD bytes 1 2 4 8 16 up to 32k bytes When source or destination addresses are updated incremented or decremented after a DMA move all upper bits 31 CBLS of source address and 31 CBLD of destination address are frozen and remain unchanged even if a wrap around from the lower address bits CBLS 0 or CBLD 0 occurred This address freezing mechanism always...

Page 839: ...wo different DMA channels with identical channel priority become active at the same time the DMA channel with the lowest channel number n is serviced first The Move Engine handles the execution of a DMA transfer that has been detected by the Channel Arbiter to be the next one The Move Engine requests the required buses and loads or stores data according to the parameters of a DMA transfer It is ab...

Page 840: ...e interface which provides the access to the DMA and the peripherals connected to the DMA Peripheral Interface MLI Cerberus and Memory Checker modules The LMB Bus interface of the DMA is a master interface The DMA module the DMA Sub Blocks as well as the MLI the Memory Checker and the Cerberus module working frequencies are identical to the FPI Bus frequency The working frequency of the LMB master...

Page 841: ...the DMA Bus Switch Move Engine MLI Cerberus for the same resource FPI Bus Interface LMB Bus Interface DMA Peripheral Interface Move Engine The arbitration is done for each Bus Switch request The general overview of the Bus Switch Priorities is given in Table 11 1 Additional detailed information about the Move Engine priorities for concurrent on the Bus Switch is described in Table 11 2 In case of ...

Page 842: ...The detailed Bus Switch priorities for the two Engines with concurrent reads or concurrent writes are listed in Table 11 2 DMA Move Engine Read The detailed Bus Switch priorities for the two Engines with concurrent reads or concurrent writes are listed in Table 11 2 MLI0 access Lowest Cerberus to On Chip Bus Low Priority selection by software in Cerberus Table 11 2 DMA Bus Switch Priorities of DMA...

Page 843: ...ter The complete list of LMB master priorities can be found in the Local Memory Bus Controller Unit Chapter 11 2 8 DMA Module On Chip Bus Access Rights RMW support All accesses triggered by the DMA Move Engines the MLI module or the Cerberus module are always done in SV mode The DMA module does not support read modify write instructions to the peripherals connected to the DMA Peripheral Interface ...

Page 844: ...e dedicated LMB requests medium low high priority See Table 11 3 2 A single move engine supports only one transaction at a time Due to the fact that the move engines do generate read write sequences it is unlikely that the DMA module generates permanent pipelined high priority requests DMA LMB Master Read Buffer The DMA LMB master interface includes a 64bit buffer for read accesses to cached addre...

Page 845: ...unctionality from the FPI Bus to the DMA Peripheral Interface from the DMA Peripheral Interface to the FPI Bus and LMB Bus FPI Bus LMB Bus The DMA module does not forward transaction from the FPI Bus to the LMB Bus The DMA module does not support include bridge functionality between FPI Bus and LMB Bus FPI Bus DMA Peripheral Interface MLI Memory Check Cerberus The DMA module forwards transactions ...

Page 846: ...trol unit is able to generate a Soft suspend Mode request SUSREQ for the DMA controller When this soft suspend request becomes active the state of a DMA channel becomes frozen regarding hardware changes to ensure that the state of the DMA channels can be analyzed by reading the register contents Pending read or write transfers in the DMA module On Chip Bus Master Interfaces LMB Master Interface FP...

Page 847: ...gether to the BREAK output signal A transaction lost break condition occurs in DMA Sub Block m whenever at least one of its eight transaction lost interrupts becomes active and when enable bit OCDSR BRL0 is set The transaction lost interrupts do not generate a break condition if OCDSR BRL0 0 Transaction interrupt control is described in Section 11 2 12 2 The second break condition of DMA Sub Block...

Page 848: ...MA User s Manual 11 30 V1 1 2011 05 DMA V3 03 Figure 11 16 DMA Break Event Generation m 0 1 TRSR CH01 BREAK BCHS0 OCDSR TRSR CH07 Edge Detection BTCR0 OCDSR BRL0 OCDSR Enabled Transaction Lost Interrupts 00 07 DMA Sub Block m MCA06164 3 2 1 1 ...

Page 849: ... associated channel interrupt It can always be activated after a DMA transfer or when CHSRmn TCOUNT matches with the value of bit field CHSRmn IRDV after it has been decremented after a DMA transfer The pattern detection interrupts that are combined with the channel interrupts one common Interrupt Node Pointer CHICRmn INTP are activated when the pattern detection interrupt of DMA channel mn become...

Page 850: ...errupt pointer CHICRmn INTP defines which of the interrupt outputs SR 15 0 will be activated on a pattern detection interrupt or the channel interrupt pointer CHICRmn INTP determines which of the interrupt outputs SR 15 0 1 will be activated on a pattern detection or channel interrupt Figure 11 17 Channel Interrupts m 0 1 1 In the TC1784 SR 7 0 are connected to interrupt nodes SR 8 15 are used for...

Page 851: ...t interrupt that can be directed to one of the interrupt outputs SR 15 0 1 by setting the transaction lost interrupt pointer EER TRLINP with a corresponding value A transaction request lost condition of DMA channel mn is indicated by status flag ERRSR TRLmn which can be reset by setting bit CLRE CTLmn or CHRSTR CHmn The transaction lost interrupt for DMA channel mn is enabled when bit EER ETRLmn i...

Page 852: ...tware when setting bit CLRE CME0SER The source error interrupt of Move Engine 0 is enabled when bit EER EME0SER is set Separate reset status and enable bits are available in the Move Engines for source error condition as well as for destination error condition The Move Engine s interrupts can be directed to one of the interrupt outputs SR 15 0 1 by setting the Move Engine interrupt pointer EER ME0...

Page 853: ...wo status conditions At which On Chip Bus interface a Move Engine 0 error occurred FPI or LMB For which DMA channel a Move Engine 0 read or write move error was reported LECME0 These error status bits and bit fields are required by error handler software to detect in detail at which On Chip Bus interface and DMA channel the Move Engine error has been generated ERRSR FPIER or ERRSR LMBER is reset w...

Page 854: ...it CHICRmn WRPSE is set The wrap destination buffer interrupt is enabled when bit CHICRmn WRPDE is set The two interrupts for wrap source buffer and wrap destination buffer are OR ed together to one common wrap buffer interrupt of DMA channel mn that can be directed to one of the interrupt outputs SR 15 0 1 by setting the wrap buffer interrupt pointer CHICRmn WRPP with a corresponding value Note t...

Page 855: ...1 condenses the 8 1 1 8 18 interrupt sources to the sixteen interrupt outputs Each internal interrupt source can be directed to one of the sixteen interrupt outputs SR 15 0 1 by using a 4 bit Interrupt Node Pointer This also allows the connection of more than one interrupt source to one interrupt output SRx Each interrupt output SR 15 0 1 can also be activated by writing a 1 to the corresponding b...

Page 856: ...atch is always stored in a bit LXO of the channel status register of the DMA channel mn that is currently executing the DMA move Therefore the pattern match result LXO of the previous read move can also be combined together with the pattern match result of the actual read move ME0R is overwritten with each read move MCA06169 INTP CHICRmn MEm DMA Channel Interrupts 8 Pattern Det Interrupts 8 TRLINP...

Page 857: ...Another control bit CHCRmn PATSEL selects among the different operating modes for a specific value of CHDW Depending on CHCRmn PATSEL and on the positive result of the comparison two actions follow if CHCRmn PATSEL 00 no action will be taken when a pattern match is detected so the wrap interrupt can be used The activation of the interrupt corresponding to the current active channel mn using the In...

Page 858: ...t from register ME0R is compared to the corresponding pattern bit stored in register ME0PR If both bits are equal and a pattern mask bit stored in another part of register ME0PR is 0 the compare matched condition becomes active When the pattern mask bit is set to 1 the compare matched condition is always active set for the related bit When the compare matched conditions for each bit within a COMP ...

Page 859: ...g from a serial peripheral unit with 8 bit data width e g recognition of carriage return line feed characters A mask operation of each compared bit is possible Figure 11 23 Pattern Detection for 8 bit Data Width CHCRmn CHDW 00B m 0 Table 11 4 Pattern Detection for 8 bit Data Width CHCRmn PATSEL Pattern Detection Operating Modes 00B Pattern detection disabled 01B Pattern compare of RD00 to PAT00 ma...

Page 860: ...remented the low byte RD00 of the current and the high byte RD01 of the previous 16 bit read move are compared If it is not known on which byte boundary even or odd address the 16 bit pattern to be detected is located the combined mode should be used This mode is the most flexible Table 11 5 Pattern Detection for 16 bit Data Width CHCRmn PATSEL ADRCRmn INCS Pattern Detection Operating Modes 00B Pa...

Page 861: ...bit data searches Figure 11 24 Pattern Detection for 16 bit Data Width CHCRmn CHDW 01B m 0 1 2 MCA06172 0 PAT03 PAT02 PAT01 PAT00 31 PATSEL CHCRmn Pattern Detected LXO CHSRmn ME0PR COMP RD03 RD02 RD01 RD00 31 15 0 16 ME0R COMP COMP 1 This signal is clocked into LXO after each read move 1 INCS ADRCRmn 1 15 16 23 7 8 24 7 8 23 24 1 Mask Mask Mask 10 11 01 00 0 0 1 0 ...

Page 862: ...half word only or the complete 32 bit word with a pattern stored in the ME0PR register A mask operation is not possible Figure 11 25 Pattern Detection for 32 bit Data Width CHCRmn CHDW 10B m 0 1 Table 11 6 Pattern Detection for 32 bit Data Width CHCRmn PATSEL Pattern Detection Operating Modes 00B Pattern detection disabled 01B Unmasked pattern compare of RD0 1 0 to PAT0 1 0 10B Unmasked pattern co...

Page 863: ...dress range extension makes it possible to define a sub range within the corresponding address range where an access will be executed by the corresponding Move Engine if the address range is not disabled by the corresponding AENx bit An access to the address range outside the defined sub range will not be executed by the corresponding Move Engine The parameters for the sub ranges are stored in the...

Page 864: ...CE 2 0 selects one out of the eight sub ranges SLICE 4 3 is don t care 27 128 sub ranges are basically available with SIZEn 000B SLICEn 4 0 selects one out of the lowest 32 sub ranges The upper 3 x 32 96 sub ranges are not selectable fixed address bits a 1 and a 2 Note The definition of the fixed address ranges x and the assignment of each sub range to one of the fixed address ranges is product sp...

Page 865: ...dress a 6 0 31 a 5 a 7 0 0 5 Variable Address a 8 0 Fixed Address Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Variable Address 1 This bit is defined by SLICE 0 2 These 2 bits are defined by SLICE 1 0 3 These 3 bits are defined by SLICE 2 0 4 These 4 bits are defined by SLICE 3 0 5 These 5 bits are defined by SLICE 4 0 Fixed Address Range Pr...

Page 866: ...ndicate the related DMA Sub Block and one index to indicate the related DMA channel Index m refers to the DMA Sub Block number m 0 1 and Index n or x refers to the channel number n 0 7 or x 0 7 within the DMA Sub Block DMA Registers Overview Figure 11 27 DMA Kernel Registers Table 11 7 Registers Address Space DMA Module Module Base Address End Address Note DMA F000 3C00H F000 3EFFH mov_eng_reg_its...

Page 867: ...er 014H U SV BE 3 Page 11 61 DMA_STR EQ DMA Software Transaction Request Register 018H U SV SV 3 Page 11 63 DMA_HTR EQ DMA Hardware Transaction Request Register 01CH U SV SV 3 Page 11 64 DMA_EER DMA Enable Error Register 020H U SV SV 3 Page 11 66 DMA_ERR SR DMA Error Status Register 024H U SV BE 3 Page 11 69 DMA_CLR E DMA Clear Error Register 028H U SV SV 3 Page 11 72 DMA_GIN TR DMA Global Interru...

Page 868: ...nge Register 050H U SV SV E 3 Page 11 84 DMA_INTS R DMA Interrupt Status Register 054H U SV BE 3 Page 11 74 DMA_INTC R DMA Interrupt Clear Register 058H U SV SV 3 Page 11 78 DMA_WRP SR DMA Wrap Status Register 05CH U SV BE 3 Page 11 76 Reserved 060H BE BE DMA_OCD SR DMA OCDS Register 064H U SV SV E 1 Page 11 55 DMA_SUS PMR DMA Suspend Mode Register 068H U SV SV E 1 Page 11 57 Reserved 06CH 07CH BE...

Page 869: ... 20 H m x 10 0H 08CH U SV SV 3 Page 11 93 DMA_SAD Rmn DMA Channel mn Source Address Register n 0 7 m 0 1 n x 20 H m x 10 0H 090H U SV SV 3 Page 11 98 DMA_DAD Rmn DMA Channel mn Destination Address Register n 0 7 m 0 1 n x 20 H m x 10 0H 094H U SV SV 3 Page 11 99 DMA_SHA DRmn DMA Channel mn Shadow Address Register n 0 7 m 0 1 n x 20 H m x 10 0H 098H U SV BE SV 2 3 Page 11 100 Reserved n 0 7 m 0 1 n...

Page 870: ...DMA_ SRC5 DMA Service Request Control Register 5 2E8H U SV SV 3 Page 11 123 DMA_ SRC4 DMA Service Request Control Register 4 2ECH U SV SV 3 Page 11 123 DMA_ SRC3 DMA Service Request Control Register 3 2F0H U SV SV 3 Page 11 123 DMA_ SRC2 DMA Service Request Control Register 2 2F4H U SV SV 3 Page 11 123 DMA_ SRC1 DMA Service Request Control Register 1 2F8H U SV SV 3 Page 11 123 DMA_ SRC0 DMA Servic...

Page 871: ...the following register description are virtual registers and do not contain flip flops They are always read as 0 2 Write access mode to DMA_SHADRmn is controlled by the register bit DMA_ADRCRmn SHWEN DMA_ADRCRmn SHWEN 0 Access Mode Write for DMA_SHADRmn is BE DMA_ADRCRmn SHWEN 1 Access Mode Write for DMA_SHADRmn is SV ...

Page 872: ...28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type The bit field is set to C0H which defines the module as a 32 bit module MOD_NUMBER 3...

Page 873: ...request bit TRSR CH0n that leads to a break condition in DMA Sub Block 0 00B No break condition is generated 01B A break condition is generated when TRSR CH0n changes from 0 to 1 10B A break condition is generated when TRSR CH0n changes from 1 to 0 11B A break condition is generated when TRSR CH0n changes its state BCHS0 4 2 rw Break Channel Select In Sub Block 0 This bit field determines the DMA ...

Page 874: ...nges from 0 to 1 10B A break condition is generated when TRSR CH1n changes from 1 to 0 11B A break condition is generated when TRSR CH1n changes its state BCHS1 12 10 rw Break Channel Select In Sub Block 1 This bit field determines the DMA channel n of DMA Sub Block 1 whose transaction request bit TRSR CH1n is observed for signal transitions as defined by BTRC1 000B DMA channel 10 selected 001B DM...

Page 875: ...11 10 9 8 7 6 5 4 3 2 1 0 SUS EN 17 SUS EN 16 SUS EN 15 SUS EN 14 SUS EN 13 SUS EN 12 SUS EN 11 SUS EN 10 SUS EN 07 SUS EN 06 SUS EN 05 SUS EN 04 SUS EN 03 SUS EN 02 SUS EN 01 SUS EN 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description SUSEN0n n 0 7 n rw Suspend Enable for DMA Channel 1n This bit enables the soft suspend capability individually for each DMA channel 0n 0B ...

Page 876: ...ctive a DMA transaction of DMA channel 1n is stopped after the current DMA transfer has been finished Soft suspend Mode can be terminated when SUSENmn is written with 0 SUSAC0n n 0 7 16 n rh Suspend Active for DMA Channel 0n This status bit indicates whether DMA channel 0n is in Soft suspend Mode or not 0B DMA channel 0n is not in Soft suspend Mode or internal actions are not yet finished after th...

Page 877: ...28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI DMA 15 SI DMA 14 SI DMA 13 SI DMA 12 SI DMA 11 SI DMA 10 SI DMA 9 SI DMA 8 SI DMA 7 SI DMA 6 SI DMA 5 SI DMA 4 SI DMA 3 SI DMA 2 SI DMA 1 SI DMA 0 w w w w w w w w w w w w w w w w Field Bits Type Description SIDMAx x 0 15 x w Set DMA Interrupt Output Line x 0B No action 1B DMA interrupt output line SRx will be activ...

Page 878: ... 7 n rwh Channel 0n Reset These bits force the DMA channel 0n to stop its current DMA transaction Once set by software this bit will be automatically cleared when the channel has been reset Writing a 0 to CH0n has no effect 0B No action write or the requested channel reset has been reset read 1B DMA channel 0n is stopped More details see Page 11 17 CH1n n 0 7 8 n rwh Channel 1n Reset These bits fo...

Page 879: ... CH 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description CH0n n 0 7 n rh Transaction Request State of DMA Channel 0n 0B No DMA request is pending for channel 0n 1B A DMA request is pending for channel 0n CH1n n 0 7 8 n rh Transaction Request State of DMA Channel 1n 0B No DMA request is pending for channel 1n 1B A DMA request is pending for channel 1n HTRE0n n 0 7 16 n rh ...

Page 880: ...n is disabled An input DMA request will not trigger the channel 1n 1B Hardware transaction request for DMA Channel 1n is enabled The transfers of a DMA transaction are controlled by the corresponding channel request line of the DMA requesting source HTRE1n is set to 0 when CHSR1n TCOUNT is decremented and CHSR1n TCOUNT 0 HTRE1n can be enabled and disabled with HTREQ ECH1n or HTREQ DCH1n Field Bits...

Page 881: ... 1 0 SCH 17 SCH 16 SCH 15 SCH 14 SCH 13 SCH 12 SCH 11 SCH 10 SCH 07 SCH 06 SCH 05 SCH 04 SCH 03 SCH 02 SCH 01 SCH 00 w w w w w w w w w w w w w w w w Field Bits Type Description SCH0n n 0 7 n w Set Transaction Request for DMA Channel 0n 0B No action 1B A transaction for DMA channel 0n is requested When setting SCH0n TRSR CH0n becomes set to indicate that a DMA request is pending for DMA channel 0n ...

Page 882: ...0 ECH 17 ECH 16 ECH 15 ECH 14 ECH 13 ECH 12 ECH 11 ECH 10 ECH 07 ECH 06 ECH 05 ECH 04 ECH 03 ECH 02 ECH 01 ECH 00 w w w w w w w w w w w w w w w w Field Bits Type Description ECH0n n 0 7 n w Enable Hardware Transfer Request for DMA Channel 0n see table below ECH1n n 0 7 8 n w Enable Hardware Transfer Request for DMA Channel 1n see table below DCH0n n 0 7 16 n w Disable Hardware Transfer Request for...

Page 883: ...11 05 DMA V3 03 X 1 X Reset X X 1 Reset 1 In Single Mode only In Continuous Mode the end of a transaction has no impact Table 11 9 Conditions to Set Reset the Bits TRSR HTREmn cont d HTREQ ECHmn HTREQ DCHmn Transaction Finishes1 for Channel mn Modification of TRSR HTREmn ...

Page 884: ...scription ETRL0n n 0 7 n rw Enable Transaction Request Lost for DMA Channel 0n This bit enables the generation of an interrupt when the set condition for ERRSR TRL0n is detected 0B The interrupt generation for a request lost event for channel 0n is disabled 1B The interrupt generation for a request lost event for channel 0n is enabled ETRL1n n 0 7 8 n rw Enable Transaction Request Lost for DMA Cha...

Page 885: ...is enabled EME1DER 19 rw Enable Move Engine 0 Destination Error This bit enables the generation of a Move Engine 0 destination error interrupt 0B Move Engine 1 destination error interrupt is disabled 1B Move Engine 1 destination error interrupt is enabled ME0INP 23 20 rw Move Engine 0 Error Interrupt Node Pointer ME0INP determines the number n n 0 15 of the service request output SRn that becomes ...

Page 886: ...Engine 1 interrupt Note In the TC1784 SR 7 0 are connected to interrupt nodes SR 15 8 are used as DMA channel request inputs Page 11 102 TRLINP 31 28 rw Transaction Lost Interrupt Node Pointer TRLINP determines the number n n 0 15 of the service request output SRn that becomes active on a transaction lost interrupt 0000B SR0 selected for transaction lost interrupt 0001B SR1 selected for transactio...

Page 887: ...17 TRL 16 TRL 15 TRL 14 TRL 13 TRL 12 TRL 11 TRL 10 TRL 07 TRL 06 TRL 05 TRL 04 TRL 03 TRL 02 TRL 01 TRL 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description TRL0n n 0 7 n rh Transaction Transfer Request Lost of DMA Channel 0n 0B 0 No request lost event has been detected for channel 0n 1B 1 A new DMA request was detected while TRSR CH0n 1 request lost event This bit is re...

Page 888: ...nation error has occurred ME1SER 18 rh Move Engine 1 Source Error This bit is set whenever a Move Engine 1 error occurred during a source read move of a DMA transfer or a request could not been serviced due to the access protection 0B No Move Engine 1 source error has occurred 1B A Move Engine 1 source error has occurred ME1DER 19 rh Move Engine 1 Destination Error This bit is set whenever a Move ...

Page 889: ...hip Bus error occurred due to Cerberus LECME0 26 24 rh Last Error Channel Move Engine 0 This bit field indicates the channel number of the last channel of Move Engine 0 leading to an On Chip Bus error that has occurred MLI0 27 rh MLI0 Error Source This bit is set whenever an On Chip Bus error occurred due to an action of MLI0 0B No On Chip Bus error occurred due to MLI0 1B An On Chip Bus error occ...

Page 890: ... 10 CTL 07 CTL 06 CTL 05 CTL 04 CTL 03 CTL 02 CTL 01 CTL 00 rw rw rw rw rw rw rw rw w w w w w w w w Field Bits Type Description CTL0n n 0 7 n w Clear Transaction Request Lost for DMA Channel 0n 0B No action 1B Clear DMA channel 0n transaction request lost flag ERRSR TRL0n CTL1n n 0 7 n 8 w Clear Transaction Request Lost for DMA Channel 1n 0B No action 1B Clear DMA channel 1n transaction request lo...

Page 891: ...CFPIER 20 w Clear FPI Error 0B No action 1B Clear error flag ERRSR FPIER CLMBER 21 w Clear LMB Error 0B No action 1B Clear error flag ERRSR LMBER CLCERBER US 22 w Clear Cerberus Error 0B No action 1B Clear error flag ERRSR Cerberus CLRMLI0 27 w Clear MLI0 Error 0B No action 1B Clear error flag ERRSR MLI0 0 26 23 30 28 31 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 892: ...H 12 ICH 11 ICH 10 ICH 07 ICH 06 ICH 05 ICH 04 ICH 03 ICH 02 ICH 01 ICH 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description ICH0n n 0 7 n rh Interrupt from Channel 0n This bit indicates that channel 0n has raised an interrupt for TCOUNT IRDV or if TCOUNT has been decremented depending on CHICR INTCT 0 This bit and IP0n is reset by software when writing a 1 to INTCR CICH0...

Page 893: ...a 1 to INTCR CICH0n or by a channel reset writing CHRSTR CH0n 1 0B A pattern has not been detected 1B A pattern has been detected IPM1n n 0 7 24 n rh Pattern Detection from Channel 1n This bit indicates that a pattern has been detected for channel 1n while the pattern detection has been enabled This bit and ICH1n is reset by software when writing a 1 to INTCR CICH1n or by a channel reset writing C...

Page 894: ...rh rh rh rh rh rh rh rh Field Bits Type Description WRPS0n n 0 7 n rh Wrap Source Buffer for Channel 0n These bits indicate which channels have done a wrap around of their source buffer s 0B No wrap around occurred for channel 0n 1B A wrap around occurred for channel 0n This bit is reset by software by writing a 1 to INTCR CWRP0n or CHRSTR CH0n WRPS1n n 0 7 8 n rh Wrap Source Buffer for Channel 1n...

Page 895: ...p Destination Buffer for Channel 1n These bits indicate which channels have done a wrap around of their destination buffer s 0B No wrap around occurred for channel 1n 1B A wrap around occurred for channel 1n This bit is reset by software by writing a 1 to INTCR CWRP1n or CHRSTR CH1n Field Bits Type Description ...

Page 896: ... 03 C ICH 02 C ICH 01 C ICH 00 w w w w w w w w w w w w w w w w Field Bits Type Description CICH0n n 0 7 n w Clear Interrupt for DMA Channel 0n These bits make it possible to reset the channel interrupt flags INTSR ICH0n and INTSR IPM0n of DMA channel 0n by software 0B No action 1B Bits INTSR ICH0n and INTSR IPM0n are reset CICH1n n 0 7 8 n w Clear Interrupt for DMA Channel 1n These bits make it po...

Page 897: ...ction 1B Bits WRPSR WRPS1n and WRPSR WRPD1n are reset DMA_MESR DMA Move Engine Status Register 030H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RBTLMB ME1 WS CH1 ME1 RS RBTFPI ME0 WS CH0 ME0 RS rh rh rh rh rh rh rh rh Field Bits Type Description ME0RS 0 rh Move Engine 0 Read Status 0B Move Engine 0 is not performing a read 1B Mov...

Page 898: ... a read 1B Move Engine 1 is performing a read CH1 11 9 rh Reading Channel in Move Engine 1 These bit field indicates which channel number is currently being processed by the Move Engine 1 ME1WS 12 rh Move Engine 1 Write Status 0B Move Engine 1 is not performing a write 1B Move Engine 1 is performing a write RBTLMB 15 13 rh Read Buffer Trace for LMB Bus Interface This bit field contains trace infor...

Page 899: ...Register 034H Reset Value 0000 0000H DMA_ME1R DMA Move Engine 1 Read Register 038H Reset Value 0000 0000H 31 24 23 16 15 8 7 0 RD03 RD02 RD01 RD00 rh rh rh rh Field Bits Type Description RD00 RD01 RD02 RD03 7 0 15 8 23 16 31 24 rh Read Value for Move Engine 0 Contains the 32 bit read data four bytes RD0 3 0 that is stored in the Move Engine 0 after each read move The content of ME0R is overwritten...

Page 900: ...tern detection configuration CHCR0n PATSEL and channel data width CHCR0n CHDW the patterns are processed as bytes or half words DMA_ME0AENR DMA Move Engine 0 Access Enable Register 044H Reset Value 0000 0000H DMA_ME1AENR DMA Move Engine 1 Access Enable Register 04CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AEN 31 AEN 30 AEN 29 AEN 28 AEN 27 AEN 26 AEN 25 AEN 24 AEN 23...

Page 901: ...ENx x 0 31 x rw Address Range x Enable This bit enables the read and write capability of the DMA Move Engines for address range x x 0 31 0B DMA read and write moves to address range x are disabled 1B DMA read and write moves to address range x are enabled If AENx 0 for a read write move to address range x the read write move is not executed and a source destination Move Engine interrupt is generat...

Page 902: ...0 19 18 17 16 SIZE3 SLICE3 SIZE2 SLICE2 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE1 SLICE1 SIZE0 SLICE0 rw rw rw rw Field Bits Type Description SLICE0 4 0 rw Address Slice 0 SLICE0 selects a specific sub range within address range extension 0 SIZE0 7 5 rw Address Size 0 SIZE0 determines the sub range size within address range extension 0 SLICE1 12 8 rw Address Slice 1 SLICE1 selects a ...

Page 903: ...nd address range extension definitions SIZE2 23 21 rw Address Size 2 SIZE2 determines the sub range size within address range extension 2 SLICE3 28 24 rw Address Slice 3 SLICE3 selects a specific sub range within address range extension 3 SIZE3 31 29 rw Address Size 3 SIZE3 determines the sub range size within address range extension 3 Field Bits Type Description ...

Page 904: ... CHDW CH MO DE RRO AT BLKM rw r rw r rw r rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSEL 0 TREL rw r rw Field Bits Type Description TREL 9 0 rw Transfer Reload Value This bit field contains the number of DMA transfers for s DMA transaction of DMA channel mn This10 bit transfer count value is loaded into CHSRmn TCOUNT at the start of a DMA transaction when TRSR CHmn becomes set and CHSRmn ...

Page 905: ...101B Input CHmn_REQI13 selected 1110B Input CHmn_REQI14 selected 1111B Input CHmn_REQI15 selected BLKM 18 16 rw Block Mode BLKM determines the number of DMA moves executed during one DMA transfer 000B One DMA transfer has 1 DMA move 001B One DMA transfer has 2 DMA move 010B One DMA transfer has 4 DMA move 011B One DMA transfer has 8 DMA move 100B One DMA transfer has 16 DMA move Other bit combinat...

Page 906: ...ves of DMA channel mn 00B 8 bit byte data width for moves selected 01B 16 bit half word data width for moves selected 10B 32 bit word data width for moves selected 11B Reserved PATSEL 25 24 rw Pattern Select This bit field selects the mode of the pattern detection logic Depending on the channel data width PATSEL selects different pattern detection configurations If pattern detection is enabled PAT...

Page 907: ... DMA channel mn has a low channel priority 1B DMA channel mn has a high channel priority DMAPRIO 31 30 rw DMA Priority This bit determines the DMA the request priority that is used when a move operation related to channel mn is requesting an On Chip Bus This bit has no effect in channel prioritization inside the Move Engine m in 00B Low priority selected 01B Medium priority selected 10B Reserved 1...

Page 908: ...Count Status TCOUNT holds the actual value of the DMA transfer count for DMA channel mx TCOUNT is loaded with the value of CHCRmx TREL when TRSR CHmx becomes set and TCOUNT 0 After each DMA transfer TCOUNT is decremented by 1 LXO 15 rh Old Value of Pattern Detection This bit contains the compare result of a pattern compare operation when 8 bit or 16 bit data width is selected 8 bit data width see ...

Page 909: ... Description WRPSE 0 rw Wrap Source Enable 0B Wrap source buffer interrupt disabled 1B Wrap source buffer interrupt enabled WRPDE 1 rw Wrap Destination Enable 0B Wrap destination buffer interrupt disabled 1B Wrap destination buffer interrupt enabled INTCT 3 2 rw Interrupt Control 00B No interrupt will be generated on changing the TCOUNT value The bit INTSR ICHmx is set when TCOUNT equals IRDV 01B ...

Page 910: ...ected for channel mx wrap buffer interrupt B 1111B SR15 selected for channel mx wrap buffer interrupt Note In the TC1784 SR 7 0 are connected to interrupt nodes SR 15 8 are used as DMA channel request inputs Page 11 102 INTP 11 8 rw Interrupt Pointer INTP determines the number n n 0 15 of the service request output SRn that becomes active on a channel interrupt 0000B SR0 selected for channel mx in...

Page 911: ...24 23 22 21 20 19 18 17 16 0 SHW EN SHCT r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBLD CBLS INCD DMF INCS SMF rw rw rw rw rw rw Field Bits Type Description SMF 2 0 rw Source Address Modification Factor This bit field and the data width as defined in CHCRmx CHDW determine an address offset value by which the source address is modified after each DMA move See also Table 11 10 000B Address offse...

Page 912: ...ich the destination address is modified after each DMA move The destination address is not modified if CBLD 0000B See also Table 11 10 000B Address offset is 1 x CHDW 001B Address offset is 2 x CHDW 010B Address offset is 4 x CHDW 011B Address offset is 8 x CHDW 100B Address offset is 16 x CHDW 101B Address offset is 32 x CHDW 110B Address offset is 64 x CHDW 111B Address offset is 128 x CHDW INCD...

Page 913: ...s not updated B 1110B Source address SADR 31 14 is not updated 1111B Source address SADR 31 15 is not updated CBLD 15 12 rw Circular Buffer Length Destination This bit field determines which part of the 32 bit destination address register remains unchanged and is not updated after a DMA move operation see also Page 11 20 Therefore CBLD also determines the size of the circular destination buffer 00...

Page 914: ...n SHADRmx and transferred to DADRmx with the start of the next DMA transaction 11B Reserved In case of SHCT 01B or 10B SHCT must not be changed until the next DMA transaction has been started SHWEN 18 rw Shadow Address Register Write Enable This bit determines whether the shadow address register SHADRmx is read only and automatically set to 0000 0000H or if the shadow register can also be directly...

Page 915: ...hould not be used Table 11 10 Address Offset Calculation Table CHCRmn CHDW 00B 8 bit Data Width CHCRmn CHDW 01B 16 bit Data Width CHCRmn CHDW 10B 32 bit Data Width SMF DMF INCS INCD Address Offset SMF DMF INCS INCD Address Offset SMF DMF INCS INCD Address Offset 000B 0 1 000B 0 2 000B 0 4 1 1 1 2 1 4 001B 0 2 001B 0 4 001B 0 8 1 2 1 4 1 8 010B 0 4 010B 0 8 010B 0 16 1 4 1 8 1 16 011B 0 8 011B 0 16...

Page 916: ... If DMA channel mn is active when writing to SADRmn the source address will not be written into SADRmn directly but will be buffered in the shadow register SHADRmn until the start of the next DMA transaction During this shadowed address register operation bit field ADRCRmn SHCT must be set to 01B DMA_SADR0x x 0 7 DMA Channel 0x Source Address Register 090H x 20H Reset Value 0000 0000H DMA_SADR1x x...

Page 917: ...n is active when writing to DADRmn the source address will not be written into DADRmn directly but will be buffered in the shadow register SHADRmn until the start of the next DMA transaction During this shadowed address register operation bit field ADRCRmn SHCT must be set to 10B DMA_DADR0x x 0 7 DMA Channel 0x Destination Address Register 094H x 20H Reset Value 0000 0000H DMA_DADR1x x 0 7 DMA Cha...

Page 918: ...er has already taken place If the value in SHADR is 0000 0000H no shadow transfer can take place and the corresponding address register is modified according to the circular buffer rules If ADRCRmn SHWEN 1 shadow register SHADRmn can be directly written The value stored in the SHADRmn is not modified when the shadow transfer takes place the shadow mechanism remains active and the shadow transfer w...

Page 919: ... The request sources of the peripheral modules ADC0 MSC0 MLI0 FADC MultiCAN and SCU are associated with Interrupt Node Pointers and individual interrupt enable bits As a result each of the internal requests of a module can be routed independently to any of the interrupt output lines INT_Ox of the module DMA Interrupt Nodes MCA06176 Clock Control fDMA SR 7 0 DMA Controller Arbiter Switch Control Bu...

Page 920: ...SR00 ADC CHCR00 PRSEL 0011B SSC0_RDR SSC0 CHCR00 PRSEL 0100B ASC0_RDR ASC0 CHCR00 PRSEL 0101B CAN_INT_O0 MultiCAN CHCR00 PRSEL 0110B MLI0_SR4 MLI0 CHCR00 PRSEL 0111B STMIRQ0 STM CHCR00 PRSEL 1000B GPTA_TRIG00 GPTA1 CHCR00 PRSEL 1001B GPTA_TRIG10 GPTA1 CHCR00 PRSEL 1010B INT1SRC ERAY CHCR00 PRSEL 1011B IBUSY ERAY CHCR00 PRSEL 1100B SSC2_RDR SSC2 CHCR00 PRSEL 1101B Reserved2 CHCR00 PRSEL 1110B Reser...

Page 921: ... PRSEL 0101B MSC0_SR2 MSC0 CHCR02 PRSEL 0110B MLI0_SR6 MLI0 CHCR02 PRSEL 0111B STMIRQ0 STM CHCR02 PRSEL 1000B GPTA_TRIG02 GPTA1 CHCR02 PRSEL 1001B GPTA_TRIG12 GPTA1 CHCR02 PRSEL 1010B NDAT1SRC ERAY CHCR02 PRSEL 1011B ASC0_TBDR ASC0 CHCR02 PRSEL 1100B SSC2_TDRed SSC2 CHCR02 PRSEL 1101B Reserved2 CHCR02 PRSEL 1110B Reserved2 CHCR02 PRSEL 1111B 03 DMA_SR11 DMA INT_O11 CHCR03 PRSEL 0000B IOUT3 SCU ERU...

Page 922: ...CR04 PRSEL 0011B SSC0_TDR SSC0 CHCR04 PRSEL 0100B ASC0_TDR ASC0 CHCR04 PRSEL 0101B MSC0_SR2 MSC0 CHCR04 PRSEL 0110B MLI0_SR4 MLI0 CHCR04 PRSEL 0111B STMIRQ0 STM CHCR04 PRSEL 1000B GPTA_TRIG04 GPTA1 CHCR04 PRSEL 1001B GPTA_TRIG14 GPTA1 CHCR04 PRSEL 1010B INT1SRC ERAY CHCR04 PRSEL 1011B ASC0_TBDR ASC0 CHCR04 PRSEL 1100B OBUSY ERAY CHCR04 PRSEL 1101B Reserved2 CHCR04 PRSEL 1110B Reserved2 CHCR04 PRSE...

Page 923: ...R06 PRSEL 0001B FADC_SR02 FADC CHCR06 PRSEL 0010B ADC_SR06 ADC CHCR06 PRSEL 0011B SSC0_RDR SSC0 CHCR06 PRSEL 0100B ASC0_RDR ASC0 CHCR06 PRSEL 0101B CAN_INT_O0 MultiCAN CHCR06 PRSEL 0110B MLI0_SR6 MLI0 CHCR06 PRSEL 0111B STMIRQ0 STM CHCR06 PRSEL 1000B GPTA_TRIG06 GPTA1 CHCR06 PRSEL 1001B GPTA_TRIG16 GPTA1 CHCR06 PRSEL 1010B NDAT1SRC ERAY CHCR06 PRSEL 1011B Reserved2 CHCR06 PRSEL 1100B Reserved2 CHC...

Page 924: ...annel request with the rising edge of the GPTA_TRIG signal if selected If channel requests for the positive and or negative GPTA_TRIG signal is required this can be realized either via the ERU some GPTA_TRIG signals are mapped to it or via GPTA programming by using additional GPTA cells 2 Reserved PRSEL combinations do not result to DMA Channel requests Table 11 12 DMA Request Assignment for DMA S...

Page 925: ...CR01 PRSEL 0101B CAN_INT_O1 MultiCAN CHCR01 PRSEL 0110B MLI0_SR5 MLI0 CHCR01 PRSEL 0111B STMIRQ0 STM CHCR01 PRSEL 1000B GPTA_TRIG01 GPTA1 CHCR01 PRSEL 1001B GPTA_TRIG11 GPTA1 CHCR01 PRSEL 1010B TINT0SRC ERAY CHCR01 PRSEL 1011B Reserved2 CHCR01 PRSEL 1100B Reserved2 CHCR01 PRSEL 1101B Reserved2 CHCR01 PRSEL 1110B Reserved2 CHCR01 PRSEL 1111B 12 DMA_SR10 DMA INT_O10 CHCR02 PRSEL 0000B IOUT2 SCU ERU ...

Page 926: ... CHCR03 PRSEL 0011B SSC1_TDR SSC1 CHCR03 PRSEL 0100B ASC1_TDR ASC1 CHCR03 PRSEL 0101B MSC0_SR3 MSC0 CHCR03 PRSEL 0110B MLI0_SR7 MLI0 CHCR03 PRSEL 0111B STMIRQ0 STM CHCR03 PRSEL 1000B GPTA_TRIG03 GPTA1 CHCR03 PRSEL 1001B GPTA_TRIG13 GPTA1 CHCR03 PRSEL 1010B MBSC1SRC ERAY CHCR03 PRSEL 1011B ASC1_TBDR ASC1 CHCR03 PRSEL 1100B Reserved2 CHCR03 PRSEL 1101B Reserved CHCR03 PRSEL 1110B Reserved2 CHCR03 PR...

Page 927: ...CR05 PRSEL 0001B FADC_SR01 FADC CHCR05 PRSEL 0010B ADC_SR05 ADC CHCR05 PRSEL 0011B SSC1_TDR SSC1 CHCR05 PRSEL 0100B ASC1_TDR ASC1 CHCR05 PRSEL 0101B MSC0_SR3 MSC0 CHCR05 PRSEL 0110B MLI0_SR5 MLI0 CHCR05 PRSEL 0111B STMIRQ0 STM CHCR05 PRSEL 1000B GPTA_TRIG05 GPTA1 CHCR05 PRSEL 1001B GPTA_TRIG15 GPTA1 CHCR05 PRSEL 1010B TINT1SRC ERAY CHCR05 PRSEL 1011B ASC1_TBDR ASC1 CHCR05 PRSEL 1100B Reserved2 CHC...

Page 928: ...eserved2 CHCR06 PRSEL 1111B 17 DMA_SR15 DMA INT_O15 CHCR07 PRSEL 0000B IOUT3 SCU ERU CHCR07 PRSEL 0001B FADC_SR03 FADC CHCR07 PRSEL 0010B ADC_SR07 ADC CHCR07 PRSEL 0011B SSC1_RDR SSC1 CHCR07 PRSEL 0100B ASC1_RDR ASC1 CHCR07 PRSEL 0101B CAN_INT_O1 MultiCAN CHCR07 PRSEL 0110B MLI0_SR7 MLI0 CHCR07 PRSEL 0111B STMIRQ0 STM CHCR07 PRSEL 1000B GPTA_TRIG07 GPTA1 CHCR07 PRSEL 1001B GPTA_TRIG17 GPTA1 CHCR07...

Page 929: ...e The DMA internal positive edge detection will generate the channel request with the rising edge of the GPTA_TRIG signal if selected If channel requests for the positive and or negative GPTA_TRIG signal is required this can be realized either via the ERU some GPTA_TRIG signals are mapped to it or via GPTA programming by using additional GPTA cells 2 Reserved PRSEL combinations do not result to DM...

Page 930: ...H STM 3 AEN3 F000 0400H F000 04FFH OCDS 4 AEN4 F000 0800H to F000 09FFH MSC0 5 AEN5 F000 0A00H to F000 0AFFH ASC0 6 AEN6 F000 0B00H to F000 0BFFH ASC1 7 AEN7 F000 0C00H F000 17FFH Port 0 Port 5 Port 6 Port7 Port8 Port9 Port10 8 AEN8 F030 0000H F030 04FFH 9 AEN9 F000 1800H F000 37FFH GPTA GPTA0 LTCA2 10 AEN10 F000 3C00H F000 3EFFH DMA 11 AEN11 F000 4000H F000 7FFFH MultiCAN 12 AEN12 F004 0000H F004...

Page 931: ...8FE0 0000H 8FE1 FFFFH AFE0 0000H AFE1 FFFFH Data Flash Space 26 AEN26 8FF0 0000H 8FFF BFFFH AFF0 0000H AFFF BFFFH Emulation Device Memory Space 27 AEN27 8FFF C000H 8FFF FFFFH AFFF C000H AFFF FFFFH Boot ROM 28 AEN28 F001 0000H F001 7FFFH ERAY 29 AEN29 8FE8 0000H 8FE8 1FFFH AFE8 0000H AFE8 1FFFH OVRAM 30 AEN30 D000 0000H D001 FFFFH E840 0000H E84F FFFFH DMI DMI Image E84x translated to D00x 31 AEN31...

Page 932: ...ection is valid for all memory views in parallel starting always with the base address of the memory views ending always with the end address of the address range The address ranges described by SLIZEx and SIZEx are defined as follows MEmARR SLICE0 MEmARR SIZE0 40 KB PMI RAM SPRAM assigned to address range 31 AEN31 The sub ranges are controlled by bit fields MEmARR SIZE0 and ME0ARR SLICE0 with a m...

Page 933: ...place holder for D40H E85H C00H E80H Table 11 14 PMI Address Protection Sub Range Definition SIZE0 Sub Ranges SLICE0 Selected Address Range1 000B 32 sub ranges of 512 bytes 00000B 00001B 11111B xxx0 0000H xxx0 01FFH xxx0 0200H xxx0 03FFH xxx0 3E00H xxx0 3FFFH 001B 32 sub ranges of 1 Kbyte 00000B 00001B 11111B xxx0 0000H xxx0 03FFH xxx0 0400H xxx0 07FFH xxx0 7C00H xxx0 7FFFH 010B 32 sub ranges of 2...

Page 934: ...xxx 7FFFH xxxx 8000H xxxx FFFFH 111B 64 Kbytes XXXXXB xxxx 0000H xxxx FFFFH 1 x in Table 11 15 column Selected Address Range is the place holder for DH and AH Table 11 15 OVRAM Address Protection Sub Range Definition SIZE1 Sub Ranges SLICE1 Selected Address Range1 000B 32 sub ranges of 512 bytes 00000B 00001B 11111B xFE0 0000H xFE0 01FFH xFE0 0200H xFE0 03FFH xFE0 3E00H xFE0 3FFFH 001B 32 sub rang...

Page 935: ...x0 E000H xxx0 FFFFH 101B 4 sub ranges of 16 Kbytes XXX00B XXX01B XXX10B XXX11B xxx0 0000H xxx0 3FFFH xxx0 4000H xxx0 7FFFH xxx0 8000H xxx0 BFFFH xxx0 C000H xxx0 FFFFH 110B 2 sub ranges of 32 Kbytes XXXX0B XXXX1B xxxx 0000H xxxx 7FFFH xxxx 8000H xxxx FFFFH 111B 64 Kbytes XXXXXB xxxx 0000H xxxx FFFFH Table 11 16 DMI Address Protection Sub Range Defintions SIZE2 Sub Ranges SLICE2 Selected Address Ran...

Page 936: ...xx0 0000H xxx0 3FFFH xxx0 4000H xxx0 7FFFH xxx1 C000H xxx1 FFFFH 101B 4 sub ranges of 32 Kbytes XXX00B XXX01B XXX10B XXX11B xxx0 0000H xxx0 7FFFH xxx0 8000H xxx0 FFFFH xxx1 0000H xxx1 7FFFH xxx1 8000H xxx1 FFFFH 110B 2 sub ranges of 64 Kbytes XXXX0B XXXX1B xxx0 0000H xxx0 FFFFH xxx1 0000H xxx1 FFFFH 111B 128 Kbytes XXXXXB xxx0 0000H xxx1 FFFFH 1 xxx in Table 11 16 column Selected Address Range is ...

Page 937: ...5 FFFFH 100B 8 sub ranges of 8 Kbytes XX000B XX001B XX111B F005 0000H F005 1FFFH F005 2000H F005 3FFFH F005 E000H F005 FFFFH 101B 4 sub ranges of 16 Kbytes XXX00B XXX01B XXX10B XXX11B F005 0000H F005 3FFFH F005 4000H F005 7FFFH F005 8000H F005 BFFFH F005 C000H F005 FFFFH 110B 2 sub ranges of 32 Kbytes XXXX0B XXXX1B F005 0000H F005 7FFFH F005 8000H F005 FFFFH 111B 64 Kbytes XXXXXB F005 0000H F005 F...

Page 938: ...m Units User s Manual The clock generation and interrupt control configuration as implemented in the DMA controller module is shown in Figure 11 29 The DMA controller the Cerberus and the MLI module MLI0 are supplied from a common module clock fDMA that has the frequency of the system clock fFPI and is controlled via the DMA_CLC clock control register The MLI module nor the Cerberus module does no...

Page 939: ...t interrupt requests of the DMA controller INT_O 15 8 are used ad DMA channel trigger inputs Four interrupt requests SR 3 0 INT_O 3 0 from the MLI0 module upper four interrupt requests of the MLI0 module INT_O 7 4 are not connected Figure 11 30 Implementation of the DMA Module and the MLI Module DMA Module Kernel Interrupt Control in DMA Module Clock Control Address Decoder MCA06178 INT_O 15 0 fML...

Page 940: ...0 0008H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE ONE SP EN DISS DISR r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable t...

Page 941: ...7 DMA Service Request Control Register x 2FCH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control 0B CPU service is initiated 1B PCP request is initiated SRE 12 rw Service Req...

Page 942: ... MLI0 service request registers is identical to that of the DMA Service Request Control Registers shown on the previous page DMA_MLI0SRCx x 0 3 DMA MLI0 Service Request Control Register x 2ACH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0...

Page 943: ... adds the absolute address information Figure 11 31 DMA Controller Register Block Address Map MCA06179 General Module Control DMA Control Status Registers F000 3C00H F000 3C10H F000 3C80H F000 3C30H DMA Channel 00 07 Registers Move Engine Registers DMA Control Status Registers F000 3C54H MLI Service Request Control Registers System Service Request Control Registers DMA Service Request Control Regi...

Page 944: ...ecker result register In order to start a memory check sequence the memory checker result register must be initialized e g written with FFFFFFFFH or with a desired start value and a DMA transaction must be set up start address length etc When programming the DMA channel for the memory checker with CHCRmn RROAT 1 one DMA transfer request software or hardware triggered starts the DMA transaction Dur...

Page 945: ...0 1 30 31 g32 MCHKIR memory checker input data bits MCHKRR memory checker result data bits X O R X O R X O R X O R F F 2 X O R 2 MCHK_structure g32 AND result bits with polynomial bits in MCHKPOR X O R X O R X O R X O R X O R 31 5 8 23 24 29 g26 g10 g7 g2 g0 XOR all bits X O R X O R 26 27 g4 X O R X O R 20 21 X O R 9 X O R X O R 19 15 g23 g22 g16 g12 g11 g8 g5 X O R g1 30 ...

Page 946: ... Checker Module Control Registers Short Name Description Offset Addr 1 Access Mode Reset Class Description See Read Write Reserved 000H 004H BE BE MCHK_ID Module Identification Register 008H US V BE Page 11 129 Reserved 00CH BE BE MCHK_IR0 Memory Checker Input Register 010H U SV U SV 3 Page 11 HID DEN MCHK_RR0 Memory Checker Result Register 014H U SV U SV 3 Page 11 HID DEN MCHK_IR1 Memory Checker ...

Page 947: ...ification Register 008H Reset Value 001B C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type The bit field is set to C0H ...

Page 948: ...A Memory Checker Result Register contains the result of the memory check operation Before starting a checksum calculation operation it should be written with an initial checksum calculation value MCHK_IRx x 0 1 Memory Checker Input Register 010H x 08H Reset Value 0000 0000H 31 0 MCHKIN w Field Bits Type Description MCHKIN 31 0 w Memory Checker Input The value written to MCHKIN is used for the next...

Page 949: ... the DMA controller is used Accessing MCHK_WR with the Move Engine of the MLI or DMA controller via the Bus Switch of the DMA controller see Figure 11 14 does not request the two FPI buses of the TC1784 SPB and DMA because it is near the MLI modules address ranges MCHK_WR Memory Checker Write Register 020H Reset Value 0000 0000H 31 0 WO w Field Bits Type Description WO 31 0 w Write Only This write...

Page 950: ...TC1784 Direct Memory Access Controller DMA User s Manual 11 132 V1 1 2011 05 DMA V3 03 ...

Page 951: ...nnected to the Local Memory Bus LMB 12 1 Feature List The main features of the memory controller are as follows 64 bit internal LMB interface 16 bit external multiplexed bus interface Flexibly programmable access parameters Different Device settings available for read and write accesses Programmable chip select lines Devices with separate address and data lines supported when an external address l...

Page 952: ... control either asynchronous external accesses or accesses to the registers The EBU further contains blocks that control the region selection as well as the data and address paths MCB05713 Address Bus Control Lines Local Memory Bus Data Path Control Asynchronous Access State Machine LMB Address Region Selection LMB Data 16 External Bus Unit EBU Address Data Bus 5 64 64 32 Address Path Control Regi...

Page 953: ...ds 16 address lines are multiplexed onto the comibined address data bus The uppermost four address lines A 20 16 are available as separate signals An external device can be selected via one of the chip select lines Since there are four chip select lines four such devices with up to 16 Mbytes of address range can be used in the external system 12 3 3 Chip Selects CS 3 0 The EBU provides four chip s...

Page 954: ... and AD 15 0 It can be used to latch these addresses externally 12 3 6 Byte Controls BC 1 0 The byte control signals BC 1 0 select the appropriate byte lanes of the data bus for both read and write accesses Table 12 2 shows the activation on access to a 16 bit or 8 bit external device Please note that this scheme supports little endian devices Signals BCx can be programmed for different timing The...

Page 955: ...re as defined below Control Mode 01B BCx signals have the same timing as the generated control signals RD or RD WR Write Enable Mode 10B BCx signals have the same timing as the generated control signal RD WR Table 12 4 EBU Interface Signals Required by Operating Mode Signal Pin When Needed by EBU AD 15 0 Always needed when the EBU is enabled EBU_MODCON ARBMODE 00B 1 A 20 16 RD RD WR ADV BC 1 0 WAI...

Page 956: ...s required by the applicatin during the initialisation of the EBU 1 If the EBU is disabled by writing 00 to the EBUCON ARBMODE field there will be a delay before the signals become available for GPIO usage as the EBU will wait for all pending external memory accesses to be completed and the arbitration logic to return to the nobus state before releasing the signals Table 12 5 Suggested Pull Compon...

Page 957: ...6 12 4 External Bus Arbitration The TC1784 memory controller does not support arbitration for the external memory bus However the EBU_MODCON ARBMODE field can be used to disable the memory controller Table 12 6 lists the programmable parameters for the external bus arbitration ...

Page 958: ...the EBU to devices on the external bus are prohibited and will generate a LMB bus error No Bus Mode is selected by EBU_MODCON ARBMODE 00B Note The EBU can be configured for optimal power saving by entering standby mode EBU_CLC DISR 1B once ARBMODE has been set to 00B 12 4 1 2 Sole Master Arbitration Mode The EBU has access to the external bus at any time Sole Master Mode is selected by EBU_MODCON ...

Page 959: ...fect the timing of signals generated using the negative edge of the internal clock and they will be delayed by half an LMB_CLK period from the rising edge and not half an internal clock period Clock ratios can be switched dynamically while the memory controller continues to process accesses to external memory provided that the register settings for the memory are valid for both clock frequencies T...

Page 960: ...are described The types of external access cycles provided by the EBU are Asynchronous devices with demultiplexed access if an external address latch is used ROMs EPROMs NOR flash devices Static RAMs and PSRAMs Asynchronous devices with multiplexed access NOR flash devices PSRAMs Note Not all memory types supported by the memory controller are known to be available in Automotive quality grades Eac...

Page 961: ...egions x 0 3 is the numbering index of these regions can be configured to respond to a particular address space through registers EBU_ADDRSELx The access parameters for each of the regions can be programmed individually to accommodate different types of external devices Separate control registers are available to control read and write accesses This allows optimal access types speeds and parameter...

Page 962: ... Chip Selects Region Associated Chip Select Address Select Registers Bus Configuration Registers Bus Access Parameters Registers Region 0 CS0 EBU_ADDRSEL0 EBU_BUSRCON0 EBU_BUSWCON0 EBU_BUSRAP0 EBU_BUSWAP0 Region 1 CS1 EBU_ADDRSEL1 EBU_BUSRCON1 EBU_BUSWCON1 EBU_BUSRAP1 EBU_BUSWAP1 Region 2 CS2 EBU_ADDRSEL2 EBU_BUSRCON2 EBU_BUSWCON2 EBU_BUSRAP2 EBU_BUSWAP2 Region 3 CS3 EBU_ADDRSEL3 EBU_BUSRCON3 EUB_...

Page 963: ...unction with the MASK parameter MASK Address mask for each external region Specifies the number of right most bits in the base address starting from bit 26 WPROT Write Protect bit for each region ALTENAB Alternate segment comparison enable of a region Determines whether or not parameter ALTSEG is always compared to LMB address REGENAB Enable bit for each region A disabled region will always genera...

Page 964: ...ntroller supports 16 bit multiplexed memory peripheral devices by setting the EBU_BUSRCONx portw bit field to 01B The EBU_BUSWCONx register also contain the portw field but in this case the field is read only and reflects the value set in the related one of the EBU_BUSRCONx registers The value set in the EBU_BUSRCONx registers are used for both read and write accesses Table 12 10 agen description ...

Page 965: ...larity only the address data signals are shown Table 12 11 Pins used to connect Multiplexed Devices to Memory Controller Memory Device Configuration Memory Controller Pins Device Configuration A 20 16 1 1 These pins are always outputs which are connected to address pins on the Multiplexed device s AD 15 0 16 bit MUX A 20 16 A 15 0 D 15 0 16 bit Multiplexed Memory Peripheral Configuration Table 12 ...

Page 966: ...User s Manual 12 16 V1 1 2011 05 EBUT13L A V1 16 Figure 12 3 Connection of a 16 bit Multiplexed Device to the Memory Controller Memory Interface AD 15 0 CSx RD RD WR WAIT A n 16 ADV Burst FLASH Mem DQ 15 0 C E OE WE ADV WAIT A n 16 ...

Page 967: ...e place for that region on a write access2 Bit field ALTSEG determines the number of an alternate segment that can be used for address comparison with A 31 28 if enabled by ALTENAB 1 Bit ALTENAB determines whether an additional alternate segment number as defined by ALTSEG is used for address comparison The address comparison scheme is shown in Figure 12 4 1 There is no hardware lockout preventing...

Page 968: ...red with the ALTSEG bit field alternate segment address The result of the comparison 1 if equal otherwise 0 is fed to an AND gate 2 If ALTENAB 0 the alternate segment function is disabled and the output of the AND gate is 0 With ALTENAB 1 the alternate segment function is enabled and the result of the comparison between ALTSEG and the segment part of the LMB address is fed to an OR gate MCA05722 3...

Page 969: ...ts the region from being selected The output of the NAND gate is fed to the final AND gate 8 The final AND gate delivers a 1 if a match occurs at the address comparison and the region x is enabled by REGENAB 1 and the access is not a write access when the region is defined as read only access This address decoding scheme has the following effects The smallest possible address region is 212 bytes 4...

Page 970: ... that there is no collision There is no checking mechanism in hardware that ensures that each segment defined either in BASE 31 28 or ALTSEG 11 8 or both is exclusive Therefore the user must ensure that each mapping from region 0 to 3 and the emulator region does not interfere with any other otherwise only the mapping with the highest priority will take effect 1010B 10 A 26 17 128 Kbyte A 16 0 100...

Page 971: ...tches this is the index number of the lowest matching region to the parameter selection logic During the third phase Cycle n 2 the parameter selection logic selects the appropriate access cycle parameters At the end of this cycle the access parameters associated with the highest priority region are checked for an invalid access e g a write access that does not lie within a defined writable region ...

Page 972: ...cking of CSy or when an internal fail safe timeout expires A programming sequence lock is aborted if an access is attempted from the processor instruction port to the locked device An aborted sequence will be flagged by the status bit LCKABRT in the EBU_MODCON register The LCKABRT flag will be cleared when 1B is written to the LCKABRT field Note This is to prevent a system livelock in the event th...

Page 973: ...d either Buffer 3 or Buffer 4 is enabled according to bit 1 of the LMB address being accessed This allows any LMB channel byte pair i e any properly aligned 16 bit data to be re aligned to the lower 16 bits of the external data bus D 15 0 12 7 8 Address Alignment During Bus Accesses During an external bus access the EBU will align the internal byte address to generate the appropriate external word...

Page 974: ...phase i e 1 first etc In the case of delays that can be extended by external control inputs the lower case letters e and i are inserted following the two letter phase identifier to differentiate between internally i and externally e generated delays For example AP2 identifies the second clock in the Address Phase CPe3 identifies the third clock in the Command Phase which is being extended by exter...

Page 975: ...for the multiplexed address bits after the ADV signal has returned to the inactive state At the end of the address hold phase the multiplexed address can be removed from the bus During a read access the multiplexed address data bus can return to the high impedance condition to allow the read data to be driven by the external memory During a write access the write data can be driven onto the multip...

Page 976: ...s the basic length of Command Phases during read cycles and bit field EBU_BUSAPx WAITWRC determines the basic length of Command Phases during write cycles Additionally when accessing asynchronous devices a Command Phase can also be extended externally using the WAIT signal when the region being accessed is programmed for external command delay control via bit EBU_BUSCONx WAIT or EBU_EMUBC WAIT The...

Page 977: ... single cycle of recovery is normally forced by the memory controller logic This means that it can also be programmed for a length of zero EBU_CLK clock cycles This phase allows the insertion of a delay following an external bus access that delays the start of the Address Phase for the next external bus access This permits flexible adjustment of the delay between accesses to the various external d...

Page 978: ...3L A V1 16 a region associated with CS2 the delay will be the highest of BUSRAP1 DTACS and BUSRAP1 RDRECOVC In this case if BUSRAP1 DTACS is greater than BUSRAP1 RDRECOVC then the number of recovery cycles between the two accesses is BUSRAP1 DTACS clock cycles minimum ...

Page 979: ... to calculate Highest Wins Recovery Phase Region Current Access Next Access Same CSn Read Read RDRECOVC Write Write WRRECOVC Read Write BUSRAPx DTACS RDRECOVC Write Read BUSWAPx DTACS WRRECOVC Different CSn Read Read BUSRAPx DTACS RDRECOVC Write Write BUSWAPx DTACS WRRECOVC Read Write BUSRAPx DTACS RDRECOVC Write Read BUSWAPx DTACS WRRECOVC ...

Page 980: ...recovery cycles when Switching between different memory regions CS Switching between read and write operations After each read cycle After each write cycle Software driver routines are required in order to support Nand Flash devices using asynchronous device accesses A single Nand Flash access sequence is performed by generating the appropriate sequence of discrete asynchronous device accesses in ...

Page 981: ... registers EBU_EMU include parameters that control the emulator chip select region CSEMU output while EBU_BUS x registers include parameters that control the four CS 3 0 chip select regions x The equivalent registers contain identical bits and bit fields Table 12 16 Asynchronous Access Programmable Parameters Register Parameter Bit Bit field Function EBU_BUSAPx ADDRC Number of cycles in address ph...

Page 982: ...BU_CLK cycle TCLK with respect to the other signals The Memory Controller allows these delays to be enabled and disabled independently via the register bits EBU_BUSCONx EBSE for ADV and EBU_BUSCONCx ECSE for the other control signals The default setting after reset has the delay disabled EBU_BUSCONx WAIT External Wait State control OFF asynchronous synchronous WAITINV Reversed polarity at WAIT act...

Page 983: ...is driven an EBU_CLK cycle after the bus is enabled The time at which write data is removed from the bus is delayed by one EBU_CLK Table 12 18 RD and RD WR Signal Timing EXTCLOCK is set to Set at Cleared at Delay Disabled1 1 See Figure 12 7 for details of this signal positioning Delay Enabled Delay Disabled1 Delay Enabled 00B Start of CP1 Start of CP1 TPH End of CPn2 2 CPn indicates the final Comm...

Page 984: ...a recovery phase the address for the next access will be delayed by one clock cycle to enforce a bus turnaround time on the data bus resulting in the valid address being driven one clock after ADV is asserted Table 12 20 Write Data Signal Timing EXTCLOCK is set to Driven at Removed at Delay Disabled1 1 See Figure 12 7 for details of this signal positioning Delay Enabled Delay Disabled1 Delay Enabl...

Page 985: ...gure 12 7 above shows an example of a read access to a multiplexed device This type of access cycle consists of two to six phases as follows EBU_CLK AP1 AH1 CPi1 RP2 new AP1 AD 15 0 ADV CSx A MAX 16 data in RD AP2 CDi1 CPi2 RP1 RP3 a Read Access EBU_CLK AP1 AH1 CPi1 DH2 new AP1 AD 15 0 ADV CSx A MAX 16 data out WR AP2 CDi1 CPi2 DH1 RP1 Address X address address X address ...

Page 986: ... for specific Nand Flash devices The required access sequences read or write are generated by connecting the Nand Flash device as an Asynchronous Device and using appropriate processor generated access sequences to emulate the NAND flash commands Figure 12 8 Shows an example of Memory Controller connected to a Nand Flash device Figure 12 8 Example of interfacing a Nand Flash device to the Memory C...

Page 987: ...rge transfer into multiple accesses to external memory but each of these accesses will have the overhead of the initial setup phase Enabling page mode using the agen field in EBU_BUSCONx will cause the standard flow of the controller to be modified as follows For a read if data remains to be fetched at the end of a command phase the controller will start a new command delay phase instead of a new ...

Page 988: ...he high state The command phase will be forced to have a minimum length of two clocks See Figure 12 9 for example waveforms Figure 12 9 NAND Flash Page Mode Accesses EBU_CLK AP1 AH1 CPi1 CPi2 AD 15 0 ADV CSx ALE CLE data in RD AP2 CDi1 CPi2 CDi1 CPi1 a Read Access EBU_CLK AP1 AH1 CPi1 AD 15 0 ADV CSx ALE CLE data out RD WR AP2 CDi1 CPi2 DH1 b Write Access A 17 16 A 17 16 CDi1 data in CPi1 CPi2 dat...

Page 989: ...nal Bus Unit User s Manual 12 39 V1 1 2011 05 EBUT13L A V1 16 Example Nand Flash Read Sequence Figure 12 10 shows an example of how the processor can generate a Nand Flash read access sequence given this configuration ...

Page 990: ...gure 12 10 Example of an Memory Controller Nand Flash access sequence read Nand F lash P ins CLE A 17 ALE A 16 CE CS2 WE W R I O 8 1 RE RD EBUL4038 Nand Flash Read Sequence E BUL 403 8 R B W AIT read command 1 address high byte 2 address middle byte 3 address low byte 4 1st data 5 ...

Page 991: ...tes by repeating cycle 5 Note A similar scheme can be used to generate write access sequences 12 10 7 Dynamic Command Delay and Wait State Insertion In general there are two critical phases during asynchronous device accesses These phases are Command Delay Phase see Page 12 26 Command Phase see Page 12 26 In the EBU internal length programming for the Command Delay Phase is available via bit field...

Page 992: ...EBU the Command Phase must always be programmed to be at least two EBU_CLK cycles via EBU_BUSAPx WAITRDC or EBU_BUSAP WAITWRC in this mode Figure 12 11 shows an example of the extension of the Command Phase through the WAIT input in synchronous mode At EBU_CLK edge 1 at the end of the Address Phase the EBU samples the WAIT input as low and starts the first cycle of the Command Phase CPi1 internall...

Page 993: ...Pi2 internally programmed At EBU_CLK edge 3 the EBU samples the WAIT input as high and starts an additional Command Phase cycle CPe3 externally generated as a result of the WAIT input sampled as low at EBU_CLK edge 1 At EBU_CLK edge 4 the EBU starts an additional Command Phase cycle CPe4 externally generated as a result of the WAIT input sampled as low at EBU_CLK edge 2 EBU_CLK A 23 0 Address AP C...

Page 994: ...0 and starts the Recovery Phase Figure 12 12 External Wait Insertion Asynchronous Mode EBU_CLK A 20 16 Address AP CPi1 CPi2 CPe3 CPe4 CSx RD AD 15 0 RP1 1 2 3 4 5 Data in In the example above the Command Delay phase is internally programmed to zero EBU_CLK cycles no Command Delay phase The Command Phase is internally programmed to two EBU_CLK cycles All other phases are programmed for one EBU_CLK ...

Page 995: ...ss Mode Description see Read Write EBU_CLC EBU Clock Control Register 0000H U SV 32 SV 32 64 E Page 12 48 EBU_MODCON EBU Configuration Register 0004H U SV 32 SV 32 64 Page 12 49 EBU_MODID EBU Module ID Register 0008H U SV 32 SV 32 64 Page 12 65 EBU_USERCON EBU Test Control Configuration Register 000CH U SV 32 SV 32 64 Page 12 65 EBU_EXTBOOT EBU External Boot Control Register 0010H U SV 32 SV 321 P...

Page 996: ... 32 SV 32 64 Page 12 54 EBU_BUSRAP1 EBU Bus Read AccessParameter Register 1 003CH U SV 32 SV 32 64 Page 12 59 EBU_BUSWCON1 EBU Bus Write Configuration Register 1 0040H U SV 32 SV 32 64 Page 12 57 EBU_BUSWAP1 EBU Bus Write AccessParameter Register 1 0044H U SV 32 SV 32 64 Page 12 62 EBU_BUSRCON2 EBU Bus Read Configuration Register 2 0048H U SV 32 SV 32 64 Page 12 54 EBU_BUSRAP2 EBU Bus Read AccessP...

Page 997: ...ite AccessParameter Register 2 0054H U SV 32 SV 32 64 Page 12 62 EBU_BUSRCON3 EBU Bus Read Configuration Register 3 0058H U SV 32 SV 32 64 Page 12 54 EBU_BUSRAP3 EBU Bus Read AccessParameter Register 3 005CH U SV 32 SV 32 64 Page 12 59 EBU_BUSWCON3 EBU Bus Write Configuration Register 3 0060H U SV 32 SV 32 64 Page 12 57 EBU_BUSWAP3 EBU Bus Write AccessParameter Register 3 0064H U SV 32 SV 32 64 Pa...

Page 998: ...Request Bit This bit is used for enable disable control of the EBU 0B EBU disable is not requested 1B EBU disable is requested Standby Mode DISS 1 r EBU Disable Status Bit DISS is always read as 0 as accessing the EBU will automatically enable it 0B EBU is enabled default after reset 1B EBU is disabled EPE 8 rw Endinit Protection Enable 0B Disable Endinit protection of the CLC register default aft...

Page 999: ... 21 r DDR Clocking Mode Status Always 0B EBUDIVACK 23 22 r EBU Clock Divide Ratio Status 00B EBU is running off input clock default after reset 01B EBU is running off input clock divided by 2 10B EBU is running off input clock divided by 3 11B EBU is running off input clock divided by 4 RES 31 24 r Reserved Read as 0 should be written with 0 EBU_MODCON EBU Configuration Register 0004H Reset Value ...

Page 1000: ...ved Read as 0 should be written with 0 EXTLOCK 4 rw External Bus Lock Control Reserved write 0 ARBSYNC 5 rw Arbitration Signal Synchronization Control Reserved write 0 ARBMODE 7 6 rw Arbitration Mode Selection 00B No Bus arbitration mode selected 01B reserved 10B reserved 11B Sole Master arbitration mode selected TIMEOUTC 15 8 rw Bus Time out Control Reserved write 00H LOCKTIMEOU T 23 16 rw Lock T...

Page 1001: ...r rh rh Field Bits Type Description CFGEND 0 rh Configuration End 0B Configuration fetch is running 1B Configuration fetch has completed or not started CFGERR 1 rh Configuration Fetch Error 0B No error 1B The configuration fetch has returned a word with all bits set This indicates an unprogrammed or missing flash EBUCFG 31 w Configuration Word Fetch Write 1B to trigger automatically set the EBU to...

Page 1002: ...ry Region Enable 0B Memory region is disabled default after reset1 1B Memory region is enabled ALTENAB 1 rw Alternate Segment Comparison Enable 0B ALTSEG is never compared to LMB address default after reset 1B ALTSEG is always compared to LMB address WPROT 2 rw Memory Region Write Protect 0B Region is enabled for write accesses 1B Region is write protected MASK 7 4 rw Memory Region Address Mask Sp...

Page 1003: ...1 16 BASE 31 12 rw Memory Region Base Address Base address to be compared to LMB address in conjunction with the mask control RES 3 r Reserved Read as 0 should be written with 0 1 except for ADDRSEL0 REGENAB in register ADDRSEL0 is 1B after reset Field Bits Type Description ...

Page 1004: ...BFS SS FBB MSEL FETBLEN r rw rw rw rw rw rw Field Bits Type Description FETBLEN 2 0 rw Burst Length for Synchronous Burst Reserved write 000B FBBMSEL 3 rw Synchronous burst buffer mode select Reserved write 0B BFSSS 4 rw Read Single Stage Synchronization Reserved write 0B FDBKEN 5 rw Burst FLASH Clock Feedback Enable Reserved write 0B BFCMSEL 6 rw Burst Flash Clock Mode Select Reserved write 1B NA...

Page 1005: ...ls 00B Byte control signals follow chip select timing 01B Byte control signals follow control signal timing RD RD WR default after reset 10B Byte control signals follow write enable signal timing RD WR only 11B Reserved PORTW 23 22 rw Device Addressing Mode See Table 12 12 Mandatory value of 01B required for correct operation WAIT 25 24 rw External Wait Control Function of the WAIT input This is s...

Page 1006: ...TC1784 LMB External Bus Unit User s Manual 12 56 V1 1 2011 05 EBUT13L A V1 16 AGEN 31 28 rw Device Type for Region See Section 12 7 3 Programmable Device Types Field Bits Type Description ...

Page 1007: ...SEL FETBLEN r r r rw rw Field Bits Type Description FETBLEN 2 0 rw Burst Length for Synchronous Burst Reserved write 000B FBBMSEL 3 rw Synchronous burst buffer mode select Reserved write 0B RES 6 4 r Reserved always reads 0 NAA 7 r Reserved RES 15 8 r Reserved 00H Reserved Value ECSE 16 rw Early Chip Select Enable 0B CS is delayed 1B CS is not delayed Note see Control of ADV Other Signal Delays Du...

Page 1008: ...ode See Table 12 12 mandatory value of 01B required for correct operation WAIT 25 24 rw External Wait Control Function of the WAIT input This is specific to the device type i e the agen field For Asynchronous Devices 0D OFF default after reset 1D Asynchronous input at WAIT 2D Synchronous input at WAIT 3D reserved Note See External Extension of the Command Phase by WAIT on Page 12 41 AAP 26 rw Asyn...

Page 1009: ...s between Different Regions This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access See Recovery Phase RP on Page 12 27 0000B No Recovery Phase clock cycles available 0001B 1 clock cycle selected B 1110B 14 clock cycles selected 1111B 15 clock cycles selected RDRECOVC 6 4 rw Recovery Cycles a...

Page 1010: ... hold clock cycles available EXTCLOCK 17 16 rw Frequency of external clock at pin BFCLKO BFCLKO is not implemented but this field can effect the relative timing of some output signals See Control of ADV Other Signal Delays During Asynchronous Accesses on Page 12 32 EXTDATA 19 18 rw Extended data Reserved write 11B CMDDELAY 23 20 rw Command Delay Cycles This bit field determines the basic number of...

Page 1011: ...BUT13L A V1 16 ADDRC 31 28 rw Address Cycles This bit field determines the number of clock cycles of the address phase 0000B1 clock cycle selected 0001B1 clock cycle selected B 1110B14 clock cycles selected 1111B15 clock cycles selected Field Bits Type Description ...

Page 1012: ...s between Different Regions This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access See Recovery Phase RP on Page 12 27 0000B No Recovery Phase clock cycles available 0001B 1 clock cycle selected B 1110B 14 clock cycles selected 1111B 15 clock cycles selected WRRECOVC 6 4 rw Recovery Cycles a...

Page 1013: ...ock cycles during write accesses 0000B No Recovery Phase clock cycles available 0001B 1 clock cycle selected B 1110B 14 clock cycles selected 1111B 15 clock cycles selected EXTCLOCK 17 16 rw Frequency of external clock at pin BFCLKO BFCLKO is not implemented but this field can effect the relative timing of some output signals See Control of ADV Other Signal Delays During Asynchronous Accesses on P...

Page 1014: ...s hold phase 0000B0 clock cycles selected 0001B1 clock cycle selected B 1110B14 clock cycles selected 1111B15 clock cycles selected ADDRC 31 28 rw Address Cycles This bit field determines the number of clock cycles of the address phase 0000B1 clock cycle selected 0001B1 clock cycle selected B 1110B14 clock cycles selected 1111B15 clock cycles selected Field Bits Type Description ...

Page 1015: ...0 rw Disable Internal Pipelining 0B The EBU can accept a new LMB transaction before the previous LMB transaction has been completed 1B The EBU will issue an LMB re try if an LMB access is received while a previous LMB transaction is still not completed RES 31 1 r Reserved Read as 0 should be written with 0 EBU_ID EBU Module Identification Register 0008H Reset Value 0014 C009H 31 0 ID_VALUE r Field...

Page 1016: ...nerate service requests to either of the two service providers As shown in Figure 13 1 each TC1784 unit that can generate service requests is connected to one or more Service Request Nodes SRNs Each SRN contains a Service Request Control Register mod_SRCx where mod is the identifier of the service requesting unit and x an optional index Two arbitration buses connect the SRNs with two Interrupt Con...

Page 1017: ...C1 4 SRNs 4 ASC0 4 SRNs ASC1 16 SRNs MultiCAN 6 SRNs ADC0 4 SRNs FADC 38 SRNs 38 GPTA0 PCP Interrupt Arbitration Bus CPU Interrupt Arbitration Bus 5 SRNs 2 SRNs PCP2 Int Ack CCPN 5 SRNs Int Req PIPN CPU CCPN Int Ack Software and Breakpoint Interrupts ICU 5 SRNs 2 SRNs 2 MSC0 8 SRNs 8 LTCA2 4 SRN 1 SRN 1 SRN 2 SRN 8 SRNs STM Service Requestors LBCU SBCU Cerberus DMA 2 SRNs Int Req PIPN SCU 3 4 16 6...

Page 1018: ...ardware each SRN can also be set or reset by software via two software initiated service request control bits The description given in this chapter characterizes all Service Request Control Registers of the TC1784 Information on peripheral module interrupt functions such as enable or request flags is provided in the corresponding sections of the module chapters 13 2 1 1 General Service Request Con...

Page 1019: ...SRE 12 rw Service Request Enable 0 Service request is disabled 1 Service request is enabled SRR 13 rh Service Request Flag 0 No service request is pending 1 A service request is pending CLRR 14 w Request Clear Bit CLRR is required to reset SRR 0 No action 1 Clear SRR bit value is not stored read always returns 0 no action if SETR is set also SETR 15 w Request Set Bit SETR is required to set SRR 0 ...

Page 1020: ...SRR bit is automatically set to 0 by hardware when the service request is acknowledged and serviced It is recommended that in this case software should not modify the SRR bit to avoid unexpected behavior due to the hardware controlling this bit If SRE 0 pending service requests are not passed on to service providers Software can poll the SRR bit to check whether a service request is pending To ack...

Page 1021: ...f Service Control TOS There are two service providers for service requests in the TC1784 the CPU and the PCP The TOS bit is used to select whether a service request generates an interrupt to the CPU TOS 0 or to the PCP TOS 1 Bit 11 of the Service Request Control Register is read only returning 0 when read Writing to this bit position has no effect However to ensure compatibility with future extens...

Page 1022: ...inable organization of the Interrupt Vector Table The 8 bit SRPNs permit up to 255 sources to be active at one time remembering that the special SRPN value of 00H excludes an SRN from taking part in arbitration Note Before modifying the content of an SRPN bit field the corresponding SRN must be disabled SRE 0 SRPNs in the TC1784 In the TC1784 interrupt sources selecting the same Service Provider a...

Page 1023: ...pt Control Register ICR The ICU Interrupt Control Register ICR holds the current CPU priority number CCPN the global interrupt enable disable bit IE the pending interrupt priority number PIPN and bit fields which control the interrupt arbitration process ICR ICU Interrupt Control Register F7E1FE2CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 C ONE CYC CARBCYC PIPN r rw...

Page 1024: ...is a read only bit field that is updated by the ICU at the end of each interrupt arbitration process It indicates the priority number of the pending service request PIPN is set to 0 when no request is pending and at the beginning of each new arbitration process 00H No valid pending request YYH A request with priority YYH is pending CARBCYC 25 24 rw Number of Arbitration Cycles CARBCYC controls the...

Page 1025: ...peration The full list of conditions which could block the CPU from immediately responding to an interrupt request generated by the ICU is Current CPU priority ICR CCPN is equal to or higher than the pending interrupt priority ICR PIPN Interrupt system is globally disabled ICR IE 0 CPU is in the process of entering an interrupt or trap service routine CPU is executing non interruptible trap servic...

Page 1026: ... a new interrupt request to the CPU according to the rules described in this section Once the CPU has acknowledged the current pending interrupt request any new service request generated by an SRN must wait at least until the end of the next service request arbitration process to be serviced Essentially arbitration in the ICU is performed whenever a new service request is detected regardless of wh...

Page 1027: ... service priorities If not all priorities are needed in a system arbitration can be accelerated by not examining all the bits used to identify all 255 unique priorities For instance if a 6 bit number is enough to identify all priority numbers used in a system meaning that bits 7 6 of all SRPNs are always 0 it is not necessary to perform arbitration on these two bits Three arbitration cycles will b...

Page 1028: ...ICR CCPN and the state of the global interrupt enable bit ICR IE are automatically saved with the PCXI register bit field PCPN and bit PIE 2 Interrupt system is globally disabled ICR IE is set to 0 3 Current CPU priority number ICR CCPN is set to the value of ICR PIPN 4 PSW is set to a default value a All permissions are enabled that is PSW IO 10B b Memory protection is switched to PRS0 that is PS...

Page 1029: ...struction to modify ICR IE and ICR CCPN However this should be performed together with an ISYNC instruction which synchronizes the instruction stream to ensure completion of this operation before the execution of following instructions Note The lower context can also be saved through execution of an SVLCX Save Lower Context instruction 13 6 Exiting an Interrupt Service Routine When an ISR exits wi...

Page 1030: ...address of the Interrupt Vector Table It can be assigned to any available code memory Its default on power up is fixed at 0000 0000H However the BIV register can be modified using the MTCR instruction during the initialization phase of the system before interrupts are enabled With this arrangement it is possible to have multiple Interrupt Vector Tables and switch between them by changing the conte...

Page 1031: ...anized according to the interrupt priorities the TC1784 offers an additional option by allowing spanning several Interrupt Vector Table entries as long as those entries are otherwise unused Figure 13 3 illustrates this The required size of the Interrupt Vector Table depends only on the range of priority numbers actually used in a system Of the 256 vector entries 255 may be used Vector entry 0 is n...

Page 1032: ...rrupt V1 4 Figure 13 3 Interrupt Vector Table 8 Words 8 Words MCA06183 Interrupt Vector Table 8 Words 8 Words BIV PN 0 never used PN 1 PN 2 PN 3 PN 4 PN 5 PN 255 Priority Number may not be used if spanned by ISR with PN 2 Service Routine may span several entries ...

Page 1033: ...ce There is a performance trade off that may arise when using this technique because the range of priority numbers used increases This may have an impact on the number of arbitration cycles required to perform arbitration Consider the case in which a system uses only three active interrupt sources that is where there are only three SRNs enabled to request service If these three active sources are ...

Page 1034: ...es of the interrupted program 13 8 3 Interrupt Priority Groups It is sometimes useful to create groups of interrupts at the same or different interrupt priorities that cannot interrupt each other s ISRs For instance devices that can generate multiple interrupts may need to have interrupts at different priorities interlocked in this way The TC1784 interrupt architecture can be used to create such i...

Page 1035: ...ps demonstrate the power of the TC1784 priority based interrupt ordering system Thus the flexibility of interrupt priority levels ranges from all interrupts in one group to each interrupt request building its own group and to all possible combinations in between Figure 13 4 Interrupt Priority Groups 13 8 4 Splitting Interrupt Service Across Different Priority Levels Interrupt service can be divide...

Page 1036: ...ise the value of ICR CCPN to a priority that would exclude some or all other interrupts or simply leave interrupts disabled 13 8 5 Using different Priorities for the same Interrupt Source For some applications the urgency of a service request may vary depending on the current state of the system To handle this different priority numbers SRPNs can be assigned at different times to a service request...

Page 1037: ...Request Control Register Thus software can initiate interrupts that are handled by the same mechanism as hardware interrupts After the SRR bit is set in an active SRN there is no way to distinguish between a software initiated interrupt request and a hardware interrupt request For this reason software should only use SRNs and interrupt priority numbers that are not being used for hardware interrup...

Page 1038: ...uest Nodes 7 0 DMA_SRC 7 0 4 MLI0 Service Request Nodes 3 0 DMA_MLI0SRC 3 0 PCP 12 PCP Service Request Nodes 11 0 PCP_SRC 11 0 1 STM 2 STM Service Request Nodes 1 0 STM_SRC 1 0 SCU 4 SCU Service Request Nodes 3 0 SCU_SRC 3 0 ASC0 4 ASC0 Transmit Interrupt Service Request Node ASC0_TSRC ASC0 Receive Interrupt Service Request Node ASC0_RSRC ASC0 Error Interrupt Service Request Node ASC0_ESRC ASC0 Tr...

Page 1039: ...SSC1_ESRC1 SSC2 3 SSC2 Transmit Interrupt Service Request Node SSC2_TSRC1 SSC2 Receive Interrupt Service Request Node SSC2_RSRC1 SSC2 Error Interrupt Service Request Node SSC2_ESRC1 MSC0 2 MSC0 Service Request Nodes 1 0 MSC0_SRC 1 0 CAN 16 CAN Service Request Nodes 15 0 CAN_SRC 15 0 1 GPTA0 38 GPTA0 Service Request Nodes 37 00 GPTA0_SRC 37 0 LTCA2 8 LTCA Service Request Nodes 07 00 LTCA2_SRC 07 00...

Page 1040: ...T0SRC1 New Data 1 Service Request Control Register ERAY_NDAT1SRC1 Message Buffer Status Changed 0 Service Request Control Register ERAY_MBSC0SRC1 Message Buffer Status Changed 1Service Request Control Register ERAY_MBSC1SRC1 Output Buffer Busy Service Request Control Register ERAY_OBUSYSRC1 Input Buffer Busy Service Request Control Register ERAY_IBUSYSRC1 1 These service request registers are not ...

Page 1041: ...t is capable of continuously timing the entire expected product life time of a system without overflowing 14 2 Operation The STM is an upward counter running either at the system clock frequency fSYS or at a fraction of it The STM clock frequency is fSTM fSYS RMC with RMC 0 7 default after reset is fSTM fSYS 2 selected by RMC 010B RMC is a bit field in register STM_CLC In case of an application re...

Page 1042: ... read The second read operation would then read the content of the STM_CAP to get the complete timer value The STM can also be read in sections from seven registers STM_TIM0 through STM_TIM6 that select increasingly higher order 32 bit ranges of the STM These can be viewed as individual 32 bit timers each with a different resolution and timing range The content of the 56 bit System Timer can be co...

Page 1043: ... STM Module 00H STM_CAP STM_TIM6 STM_TIM5 00H 56 bit System Timer Address Decoder Clock Control MCB06185_mod Compare Register 0 Interrupt Control Compare Register 1 PORST STM_TIM4 STM_TIM3 STM_TIM2 STM_TIM1 STM_TIM0 STM_CMP1 STM_CMP0 Enable Disable fSTM STM IR0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 STM IR1 to DMA etc ...

Page 1044: ...36 fSTM 178 ns 764 s STM_TIM2 39 8 256 fSTM 240 fSTM 2 8 µs 203 6 min STM_TIM3 43 12 4096 fSTM 244 fSTM 45 5 µs 54 3 h STM_TIM4 47 16 65536 fSTM 248 fSTM 0 728 ms 36 2 days STM_TIM5 51 20 220 fSTM 252 fSTM 11 7 ms 1 59 yr STM_TIM6 55 32 232 fSTM 256 fSTM 47 7 s 25 39 yr STM_CAP 55 32 232 fSTM 256 fSTM 47 7 s 25 39 yr STM_TIM0 31 0 1 fSTM 232 fSTM 22 2 ns 95 4 s 45 STM_TIM1 35 4 16 fSTM 236 fSTM 35...

Page 1045: ...6 bit STM that is taken for the compare operation can be programmed from 0 to 24 These programming capabilities make compare functionality very flexible It even makes it possible to detect bit transitions of a single bit n n 0 to 24 within the 56 bit STM by setting MSIZE 0 and MSTART n Figure 14 2 Compare Mode Operation Figure 14 2 shows an example of the compare operation In this example the foll...

Page 1046: ... STM_ISSR CMPxIRS or cleared STM_ISSR CMPxIRR by software Note that setting STM_ICR CMPxIR by writing a 1 into STM_ISSR CMPxIRS does not generate an interrupt at STMIRx The compare match interrupts from CMP0 and CMP1 can be further directed by STM_ICR CMPxOS to either output signal STMIR0 or STMIR1 The STMIR0 and STMIR1 outputs are each connected to interrupt service request control registers STM_...

Page 1047: ... Page 14 21 14 3 STM Registers This section describes the STM registers of the STM The STM registers can be divided into four types as shown in Figure 14 4 STM Registers Overview Figure 14 4 STM Registers In TC1784 all registers are readable is suspend mode The complete and detailed address map of the STM module with its registers is shown in Table 14 5 on Page 14 22 Table 14 2 Registers Address S...

Page 1048: ...TIM2 STM Timer Register 2 18H Page 14 12 STM_TIM3 STM Timer Register 3 1CH Page 14 12 STM_TIM4 STM Timer Register 4 20H Page 14 12 STM_TIM5 STM Timer Register 5 24H Page 14 13 STM_TIM6 STM Timer Register 6 28H Page 14 13 STM_CAP STM Timer Capture Register 2CH Page 14 14 STM_CMP0 STM Compare Register 0 30H Page 14 14 STM_CMP1 STM Compare Register 1 34H Page 14 14 STM_CMCON STM Compare Match Control...

Page 1049: ...SB WE E DIS SP EN DIS S DIS R r rw r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the STM module 0B No disable requested 1B Disable requested DISS 1 r Module Disable Status Bit Bit indicates the current status of the STM module 0B STM module is enabled 1B STM module is disabled SPEN 2 rw Module Suspend Enable for OCDS Used for ...

Page 1050: ...ock signal fSTM 7 selected 0 7 6 31 11 r Reserved Read as 0 should be written with 0 STM_ID STM Module Identification Register 08H Reset Value 0000 C0XXH 31 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field def...

Page 1051: ...TM counter STM_TIM0 STM Timer Register 0 10H Reset Value 0000 0000H 31 0 STM 31 0 r Field Bits Type Description STM 31 0 31 0 r System Timer Bits 31 0 This bit field contains bits 31 0 of the 56 bit STM STM_TIM1 STM Timer Register 1 14H Reset Value 0000 0000H 31 0 STM 35 4 r Field Bits Type Description STM 35 4 31 0 r System Timer Bits 35 4 This bit field contains bits 35 4 of the 56 bit STM ...

Page 1052: ...ntains bits 39 8 of the 56 bit STM STM_TIM3 STM Timer Register 3 1CH Reset Value 0000 0000H 31 0 STM 43 12 r Field Bits Type Description STM 43 12 31 0 r System Timer Bits 43 12 This bit field contains bits 43 12 of the 56 bit STM STM_TIM4 STM Timer Register 4 20H Reset Value 0000 0000H 31 0 STM 47 16 r Field Bits Type Description STM 47 16 31 0 r System Timer Bits 47 16 This bit field contains bi...

Page 1053: ...its Type Description STM 51 20 31 0 r System Timer Bits 51 20 This bit field contains bits 51 20 of the 56 bit STM STM_TIM6 STM Timer Register 6 28H Reset Value 0000 0000H 31 24 23 0 0 STM 55 32 r r Field Bits Type Description STM 55 32 23 0 r System Timer Bits 55 32 This bit field contains bits 55 32 of the 56 bit STM 0 31 24 r Reserved Read as 0 ...

Page 1054: ...ed System Timer Bits 55 32 The capture register STM_CAP always captures the STM bits 55 32 when one of the registers STM_TIM0 to STM_TIM5 is read This capture operation is performed in order to enable software to operate with a coherent value of all the 56 STM bits at one time stamp This bit field contains bits 55 32 of the 56 bit STM 0 31 24 r Reserved Read as 0 STM_CMPx x 0 1 STM Compare Registe...

Page 1055: ...arting from bit 0 that are used for the compare operation with the System Timer 00000B CMP0 0 used for compare operation 00001B CMP0 1 0 used for compare operation 11110B CMP0 30 0 used for compare operation 11111B CMP0 31 0 used for compare operation MSTART0 12 8 rw Start Bit Location for CMP0 This bit field determines the lowest bit number of the 56 bit STM that is compared with the content of r...

Page 1056: ...1B CMP1 31 0 used for compare operation MSTART1 28 24 rw Start Bit Location for CMP1 This bit field determines the lowest bit number of the 56 bit STM that is compared with the content of register CMP1 bit 0 The number of bits to be compared is defined by bit field MSIZE1 00000B STM 0 is the lowest bit number 00001B STM 1 is the lowest bit number 10111B STM 23 is the lowest bit number 11000B STM 2...

Page 1057: ...e compare match interrupt with compare register CMP0 0B Interrupt on compare match with CMP0 disabled 1B Interrupt on compare match with CMP0 enabled CMP0IR 1 rh Compare Register CMP0 Interrupt Request Flag This bit indicates whether or not a compare match interrupt request of compare register CMP0 is pending CMP0IR must be cleared by software 0B A compare match interrupt has not been detected sin...

Page 1058: ...her or not a compare match interrupt request of compare register CMP1 is pending CMP1IR must be cleared by software 0B A compare match interrupt has not been detected since the bit has been cleared for the last time 1B A compare match interrupt has been detected CMPIR1 must be cleared by software and can be set by software too see CMPISRR register After a STM reset CMP1IR is immediately set as a r...

Page 1059: ...S CMP 0 IRR r w w w w Field Bits Type Description CMP0IRR 0 w Reset Compare Register CMP0 Interrupt Flag 0B Bit ICR CMP0IR is not changed 1B Bit ICR CMP0IR is cleared CMP0IRS 1 w Set Compare Register CMP0 Interrupt Flag 0B Bit ICR CMP0IR is not changed 1B Bit ICR CMP0IR is set The state of bit CMP0IRR is don t care in this case CMP1IRR 2 w Reset Compare Register CMP1 Interrupt Flag 0B Bit ICR CMP1...

Page 1060: ...000H STM_SRC1 STM Service Request Control Register 1 F8H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR 13 rh Service Request Flag CLRR 14...

Page 1061: ...ead write access rights Table 14 4 System Timer On Chip Interconnections Service Request Signal Connected to STMIR0 DMA Channel 00 Request Input 8 DMA Channel 01 Request Input 8 DMA Channel 02 Request Input 8 DMA Channel 03 Request Input 8 DMA Channel 04 Request Input 8 DMA Channel 05 Request Input 8 DMA Channel 06 Request Input 8 DMA Channel 07 Request Input 8 DMA Channel 10 Request Input 8 DMA C...

Page 1062: ... 0000 0000H STM_TIM4 STM Timer Register 4 F000 0220H U SV U SV 0000 0000H STM_TIM5 STM Timer Register 5 F000 0224H U SV U SV 0000 0000H STM_TIM6 STM Timer Register 6 F000 0228H U SV U SV 0000 0000H STM_CAP STM Timer Capture Reg F000 022CH U SV U SV 0000 0000H STM_CMP0 STM Compare Register 0 F000 0230H U SV U SV 0000 0000H STM_CMP1 STM Compare Register 1 F000 0234H U SV U SV 0000 0000H STM_ CMCON S...

Page 1063: ...gger on instruction and data addresses as well as to control user program execution run stop breakpoint single step OCDS Level 3 The OCDS Level 3 is based on a Multi Core Debug Solution MCDS using an Emulation Device This device has the following features required for high end emulation purposes Emulation Device is available in the same package variants as TC1784 Higher current consumption due to ...

Page 1064: ...nterface Central time stamp unit to correlate traces from different cores or other sources Central mechanism to start and stop all cores simultaneously or selectively Halt the system when trace memory is full The Emulation Device includes the product chip part extended with additional emulation hardware For detailed information about the Emulation Device functionality e g as required by tool suppl...

Page 1065: ...3 V1 1 2011 05 OCDS V1 5 Figure 15 1 OCDS System Block Diagram Emulation Device only OCDS_BLOCKDIAGRAM LMB TriCore OCDS DMA OCDS Bus Switch Fabric MLI OCDS CERBERUS MCBS SCU OSCU SBCU OCDS PCP OCDS IOClient 1 DAP JTAG PINs MCDS EMEM IOC32 IOClient 2 SPB ...

Page 1066: ...mechanism allows control the device access in a secure way State aware watchdog timer suspension during debugging Control of SoC specific OCDS features Interrupt service request node for debug purposes TriCore OCDS features Hardware event generation Break by DEBUG instruction or Break signal from break switch Suspend by Suspend bus or Break signal from break switch Full hardware supported single s...

Page 1067: ... is that all relevant user and debug resources are memory mapped These resources include on chip memories CPU core registers and registers of the peripheral units A typical OCDS Level 1 debugging configuration is shown in Figure 15 2 It comprises two parts The tool software The tool access hardware interface adapter This configuration makes it possible to realize a cost effective debugging environ...

Page 1068: ...ta addresses or one data address range No break before make possible due to pipelined architecture Combinations of the above break conditions Suspend features Core Suspend Out to suspend bus Configurable Core Suspend In Real time features Read and write of memory registers independent of CPU with minimum intrusion stealing bus cycles by Cerberus High priority requests can still be serviced when th...

Page 1069: ...ible for generating debug events when a programmable set of debug triggers is active Debug triggers can be generated by the code and data protection logic These debug triggers provide the inputs to a programmable block of combinational logic that outputs debug events The aim is to be able to specify the breakpoints that use fairly simple criteria purely in the on chip debug event generation unit a...

Page 1070: ...s taken If the debug mode is not enabled then the DEBUG instruction is treated as a NOP instruction Execution of an MTCR MFCR Instruction In order to protect the emulator resource a debug event is raised whenever an MTCR or MFCR instruction is used to read or modify a user core SFR but an event is not raised when the user reads or modifies one of the dedicated core debug registers DBSR CREVT SWEVT...

Page 1071: ...on phase look for specific bus master the address phase look for specific address or range the data phase look for read write supervisor mode etc The results can be combined to generate a break request signal which is sent to the Break Switch The OCDS registers of SBCU are described in chapter On Chip System Buses and Bus Bridges starting from section System Bus Control Unit Registers 15 2 4 DMA O...

Page 1072: ... the Cerberus registers and arbitrary memory locations across the System Peripheral Bus Features OCDS Level 1 control via 5 pin standard JTAG interface 2 pin DAP interface Generation of external break condition via BRKIN BRKOUT pins possible Full access to the complete SPB Bus address space via DAP JTAG No user resources hardware software are required No or minimum run time impact Cerberus bus pri...

Page 1073: ...e is that the read or write request is not actively executed by Cerberus The request just sets bits in the CPU accessible IOSR register to signal the monitor that the debugger wants to send or receive a value The software monitor has to poll the IOSR register for that 15 3 3 Triggered Transfers Triggered transfers can be used to read from or write to a certain memory location when an OCDS trigger ...

Page 1074: ...in sources TriCore PCP DMA SBCU MLI0 MLI1 Up to two device pins configurable as BRKIN BRKOUT pins Two independent break buses Suspend generation supports delayed suspend Break to suspend converter OCDS_MCBS TriCore PCP MCDS ED only SBCU DMA MLI Multi Core Break Switch MCBS Port Control BRKIN HALT BRKIN BRKOUT BRKOUT BRKIN BRKOUT BRKOUT BRKIN BRKIN BRKOUT mode ERROR ...

Page 1075: ...ightforward half duplex protocol i e the DAP1 pin is used for data transfer from tool to device and from device to tool at different periods of time while the clock is provided by the tool to the DAP0 input 15 5 1 DAP Telegram Format All information transport between tool and device is done in telegrams Mandatory 6 bit CRC check sums assure secure transport even in noisy environments Splitting com...

Page 1076: ...er Client Telegrams The last group allows direct access to IOClients like Cerberus of the device completely hiding the asynchronous timing between tool clock and system clock of the device The following five telegrams belong to this group client_set define the current IOClient client_get ask for the index of the current IOClient client_reset reset the current IOClient client_write write to the cur...

Page 1077: ...ON JTAG Instruction Register 8 bit 1 IOPATH IO Client Selection Register 2 bit 1 Cerberus Registers OJCONF OSCU Configuration by JTAG Register 1 Register_file vsd CLIENT_ID 1 JDI Registers OJCONF 1 OSCU Registers MCDBBS MCBS Registers OEC OCNTRL OSTATE 1 These registers are only accessible via the JTAG interface BYPASS 1 JTAG Controller Registers MCDBBSS MCDSSG MCDSSGC SRC0 IOCONF1 IOINFO 1 IOADDR...

Page 1078: ...NTMOD Internal Mode Status and Control Register F000 0484H ICTSA Internal Controlled Trace Source Address Register F000 0488H ICTTA Internal Controlled Trace Target Address Register F000 048CH MCDBBS Break Bus Switch Configuration Register F000 0470H MCDBBSS Break Bus Switch Status Register F000 0490H MCDSSG Suspend Signal Generation Status and Control Register F000 0474H MCDSSGC Suspend Signal Ge...

Page 1079: ...kernel register names described in Section 16 2 are referenced in the TC1784 User s Manual by the module name prefix ASC0_ for the ASC0 interface and by ASC1_ for the ASC1 interface 16 1 ASC Kernel Description Figure 16 1 shows a global view of the ASC interface Figure 16 1 General Block Diagram of the ASC Interface The ASC module communicates with the external world via two I O lines The RXD line...

Page 1080: ...ess bytes from data bytes Testing is supported by a loop back option A 13 bit baud rate generator provides the ASC with a separate serial clock signal which can be accurately adjusted by a prescaler implemented as fractional divider Features Full duplex asynchronous operating modes 8 bit or 9 bit data frames LSB first Parity bit generation checking One or two stop bits Baud rate from 5 625 Mbit s ...

Page 1081: ...fered so a new character may be written to TBUF before the transmission of the previous character is complete This allows a back to back transmission of characters to take place without gaps Data reception is enabled by the receiver enable bit CON REN After a reception has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the r...

Page 1082: ...ure 16 2 shows the block diagram of the ASC when operating in Asynchronous Mode Figure 16 2 Asynchronous Mode of the ASC MCA06201 13 bit Baud Rate Timer 13 bit Reload Register fBRT fDIV R fASC Fractional Divider FDE fBR BRS Serial Port Control REN FEN PEN OEN LB Receive Int Req Transmit Int Req Transmit Buffer Int Req Error Int Req EIR TBIR TIR RIR M ODD STP OE PE FE Shift Clock Shift Clock Receiv...

Page 1083: ... be set if the modulo 2 sum of the seven data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit CON PEN always OFF in 8 bit data mode The parity error flag CON PE will be set along with the error interrupt request flag if a wrong parity bit is received The received parity bit itself will be stored in RBUF too Figure 16 3 Asynchronous 8 bit Frames MCT06202 ...

Page 1084: ...equest will be activated and no data will be transferred This feature can be used to control communication in multi processor systems for example When the master processor aims to transmit a block of data to one of several slaves it first sends out an address byte in this case a byte consists of nine bits that identifies the target slave An address byte differs from a data byte in that the additio...

Page 1085: ... Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXD on the condition that bits CON R and CON REN are set The receive data input pin RXD is sampled at sixteen times the rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the effective sampled bit value This avoids erroneous results that may be caused by noise If the detected va...

Page 1086: ... is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred 16 1 3 4 RXD TXD Data Path Selection in Asynchronous Modes The data paths for the serial input and output data in Asynchronous Modes are affected by control bit CON LB loop back as shown in Figure 16 5 Figure 16 5 RXD TXD Data Path Selection in Asynchronous Modes MCA06204 ASC Asynch Mode Logic RXD...

Page 1087: ...ON M 000B Eight data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is active only as long as data bits are transmitted or received Figure 16 6 Synchronous Mode of Serial Channel ASC MCA06205 BRS fBRT fDIV R fASC fBR Serial Port Control REN OEN LB Receive Int Req Transmit Int Req Transmit Buffer Int Req Error Int Req EIR ...

Page 1088: ...clock and the output data during synchronous transmission 16 1 4 2 Synchronous Reception Synchronous reception is initiated by setting bit CON REN 1 If bit CON R 1 the data applied at RXD is clocked into the receive shift register synchronously to the clock which is output at TXD After the 8th bit has been shifted in the contents of the receive shift register are transferred to the receive data bu...

Page 1089: ...f a data byte is received through RXD data is latched with the rising edge of the shift clock One shift clock cycle fBR delay is inserted between two consecutive receive or transmit data bytes Figure 16 7 ASC Synchronous Mode Waveforms D0 Valid Data n 2 Valid Data n Valid Data n 1 Data Bit n 2 Data Bit n Data Bit n 1 MCT06206 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 Rec...

Page 1090: ...N FDE In the asynchronous operating modes a fractional divider prescaler unit is available in addition to the two fixed dividers that allows selection of prescaler divider ratios of n 512 with n 0 511 Therefore the baud rate of ASC is determined by the module clock the content of register FDV the reload value in register BG and the operating mode asynchronous or synchronous Register BG is the dual...

Page 1091: ...e baud rate generator depends on the settings of the following bits and register values Input clock fASC Selection of the baud rate timer input clock fDIV by bits CON FDE and CON BRS If bit CON FDE 1 fractional divider value of register FDV Value of the 13 bit reload register BG The output clock of the baud rate timer with the reload register is the sample clock in the asynchronous operating modes...

Page 1092: ...ates together with the required reload values and the deviation errors compared to the intended baud rate Note CON FDE must be 0 to achieve the baud rates in the table above The deviation errors given in the table are rounded Using a baud rate crystal will provide correct baud rates without deviation errors Table 16 1 Asynchronous Baud Rate Formulas using the Fixed Input Clock Dividers FDE BRS BG ...

Page 1093: ...ote In fractional divider mode the clock fDIV can have a maximum period jitter of one fASC clock period BG represents the content of the reload register bit field BG BR_VALUE taken as an unsigned 13 bit integer FDV represents the contents of the fractional divider register bit field FDV FD_VALUE taken as an unsigned 9 bit integer Table 16 3 Asynchronous Baud Rate Formulas using the Fractional Inpu...

Page 1094: ...serial channel ASC can be determined by the formulas as shown in Table 16 5 BG represents the content of the reload register bit field BG BR_VALUE taken as an unsigned 13 bit integer The maximum baud rate that can be achieved in Synchronous Mode when using a module clock of 90 MHz is 11 25 Mbit s Table 16 5 Synchronous Baud Rate Formulas BRS BG Formula 0 0 8191 1 MCA06208 13 bit Baud Rate Timer Sh...

Page 1095: ...ftware or DMA transfer at the time the reception of a new frame is complete the overrun error flag CON OE is set indicating that the error interrupt request is due to an overrun error Asynchronous and Synchronous Modes 16 1 7 Interrupts Four interrupt sources are provided for serial channel ASC Line TIR indicates a transmit interrupt TBIR indicates a transmit buffer interrupt RIR indicates a recei...

Page 1096: ...r interrupt request in Synchronous Mode it is entirely impossible Using the Transmit Buffer Interrupt TBIR to reload transmit data provides the time necessary to transmit a complete frame for the service routine as TBUF may be reloaded while the previous data is still being transmitted Figure 16 10 ASC Interrupt Generation As shown in Figure 16 10 TBIR is an early trigger for the reload routine wh...

Page 1097: ...ailed address map of the of the ASC module and its registers is described in Table 16 10 on Page 16 41 Table 16 6 Registers Address Space Module Base Address End Address Note ASC0 F000 0A00H F000 0AFFH ASC1 F000 0B00H F000 0BFFH Table 16 7 Registers Overview ASC Kernel Registers Register Short Name Register Long Name Offset Address1 Description see PISEL Peripheral Input Select Register 0004H Page...

Page 1098: ...F Receive Buffer Register 0024H Page 16 29 WHBCON Write Hardware Bits Control Register 0050H Page 16 25 1 The absolute register address is calculated as follows Module Base Address Table 16 6 on Page 16 19 Offset Address shown in this column PISEL Peripheral Input Select Register 04H Reset Value 0000 0000H 31 0 0 RI S r rw Field Bits Type Description RIS 0 rw Receive Input Select 0B ASC receiver i...

Page 1099: ...le Identification Register 08H Reset Value 0000 44XXH 31 16 15 8 7 0 0 MODNUM MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MODNUM 15 8 r Module Number Value This bit field defines the module identification number for the ASC 44H 0 31 16 r Reserved Read as ...

Page 1100: ... rwh rwh rwh rw rw rw rwh rw rw Field Bits Type Description M 2 0 rw Mode Selection 000B 8 bit data Synchronous Mode 001B 8 bit data Asynchronous Mode 010B Reserved Do not use this combination 011B 7 bit data parity Asynchronous Mode 100B 9 bit data Asynchronous Mode 101B 8 bit data wake up bit Asynchronous Mode 110B Reserved Do not use this combination 111B 8 bit data parity Asynchronous Mode STP...

Page 1101: ...OEN 1 Must be reset by software FDE 11 rw Fractional Divider Enable 0B Fractional divider disabled 1B Fractional divider is enabled and used as prescaler for baud rate timer bit BRS is don t care ODD 12 rw Parity Selection 0B Even parity selected parity bit 1 on odd number of 1s in data parity bit 0 on even number of 1s in data 1B Odd parity selected parity bit 1 on even number of 1s in data parit...

Page 1102: ...he read access but before the write back access of the RMW instruction it is overwritten with the old bit value and the hardware change of the bit gets lost This problem does not affect the bits that are intended to be modified by the RMW instruction It only affects bits that were not intended to be changed with the RMW instruction The three error flags in register CON and the REN bit can be addit...

Page 1103: ...RREN 4 w Clear Receiver Enable Bit 0B No effect 1B Bit CON REN is cleared Bit is always read as 0 SETREN 5 w Set Receiver Enable Bit 0B No effect 1B Bit CON REN is set Bit is always read as 0 CLRPE 8 w Clear Parity Error Flag 0B No effect 1B Bit CON PE is cleared Bit is always read as 0 CLRFE 9 w Clear Framing Error Flag 0B No effect 1B Bit CON FE is cleared Bit is always read as 0 CLROE 10 w Clea...

Page 1104: ... time during a WHBCON write operation e g SETPE CLRPE 1 the error flag in CON is not affected SETFE 12 w Set Framing Error Flag 0B No effect 1B Bit CON FE is set Bit is always read as 0 SETOE 13 w Set Overrun Error Flag 0B No effect 1B Bit CON OE is set Bit is always read as 0 0 3 0 7 6 31 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1105: ...pe Description BR_VALUE 12 0 rwh Baud Rate Timer Reload Register Value Reading BR_VALUE returns the 13 bit content of the baud rate timer Writing BR_VALUE loads the baud rate timer reload register BG should only be written if CON R 0 0 31 13 r Reserved Read as 0 should be written with 0 FDV Fractional Divider Register 18H Reset Value 0000 0000H 31 9 8 0 0 FD_VALUE r rw Field Bits Type Description ...

Page 1106: ...Transmit Buffer Register 20H Reset Value 0000 0000H 31 9 8 0 0 TD_VALUE r rw Field Bits Type Description TD_VALUE 8 0 rw Transmit Data Register Value TBUF contains the data to be transmitted in the asynchronous and synchronous operating modes of the ASC Data transmission is double buffered therefore a new value can be written to TBUF before the transmission of the previous value is complete 0 31 9...

Page 1107: ... 9 8 0 0 RD_VALUE r rh Field Bits Type Description RD_VALUE 8 0 rh Receive Data Register Value RBUF contains the received data bits and depending on the selected mode the parity bit in the asynchronous and synchronous operating modes of the ASC In Asynchronous Mode with CON M 011B 7 bit data parity the received parity bit is written into RBUF 7 In Asynchronous Mode with CON M 111B 8 bit data parit...

Page 1108: ...e clock control port connections interrupt control and address decoding 16 3 1 Interfaces of the ASC Modules The serial I O lines of both modules are connected to Port 3 Each of the ASC modules is further supplied with interrupt control address decoding and port control logic Two DMA requests can be generated by each ASC module Both ASC modules are supplied by one common clock control unit ...

Page 1109: ...dule Details are described in the SCU and the GPTA chapters MCB06211_mod ASC0 Module Kernel Port 3 Control ASC1 Module Kernel P3 12 RXD0B P3 13 TXD0 P3 0 RXD0A P3 1 TXD0 P3 14 RXD1B P3 15 TXD1 P3 9 RXD1A P3 8 TXD1 RXD_I1 RXD_O RXD_I0 TXD_O RXD_I1 RXD_O RXD_I0 TXD_O Interrupt Control EIR TBIR TIR RIR Clock Control Address Decoder Interrupt Control fASC EIR TBIR TIR RIR To DMA ASC0_RDR ASC0_TDR To D...

Page 1110: ...egisters which are required for ASC0 ASC1 programming see also Figure 16 11 for the module kernel specific registers Figure 16 13 ASC0 ASC1 Implementation specific Special Function Registers MCA06212 ASC0_CLC ASC0_TSRC P3_IOCR0 ASC0_RSRC ASC0_ESRC ASC0_TBSRC ASC1_TSRC ASC1_RSRC ASC1_ESRC ASC1_TBSRC Control Registers Interrupt Registers Port Registers ASC0_PISEL ASC1_PISEL P3_IOCR8 P3_IOCR12 P3_PDR...

Page 1111: ...ter 00H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMC 0 FS OE SB WE E DIS SP EN DIS S DIS R rw r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspen...

Page 1112: ...led Note The number of module clock cycles wait states which are required for a destructive read access means flags bits are set reset by one read access to ASC module register depends on the selected CLC clock frequency which is selected via bit field RMC in the CLC register Therefore increasing ASC0_CLC RMC may result in a longer FPI Bus read cycle access time ...

Page 1113: ...le kernels between different pair of pins of Port 3 as shown in Figure 16 14 Register ASC0_PISEL controls the RXD input selection for ASC0 and ASC1_PISEL controls the RXD input selection for ASC1 Figure 16 14 RXD Input Line Selection of the ASC Modules ASC0 Module Kernel ASC1 Module Kernel MCB06213_mod P3 0 RXD0A P3 1 TXD0 RXD_I1 RXD_O PISEL RXD_I0 Port 3 Control TXD_O P3 9 RXD1A P3 8 TXD1 RXD_I1 ...

Page 1114: ...t Select 0B ASC0 receiver input RXD0A P3 0 selected 1B ASC0 receiver input RXD0B P3 12 selected 0 31 1 0 Reserved Read as 0 should be written with 0 ASC1_PISEL ASC1 Peripheral Input Select Register 04H Reset Value 0000 0000H 31 1 0 0 R I S r rw Field Bits Type Description RIS 0 rw Receive Input Select 0B ASC1 receiver input RXD1A P3 9 selected 1B ASC1 receiver input RXD1B P3 14 selected 0 31 1 0 R...

Page 1115: ...lect the digital output and input driver characteristics such as pull up down devices port direction input output open drain and alternate output selections individually for each pin The I O lines for the ASC modules are controlled by the port input output control registers P3_IOCR0 P3_IOCR8 and P3_IOCR12 Table 16 8 shows how bits and bit fields must be programmed for the required I O functionalit...

Page 1116: ...opriate bit field in the IOCR registers ASC1 P3 9 RXD1A ASC1_PISEL RIS 0 P3_IOCR8 PC9 0XXXB Input P3_IOCR8 PC9 1X01B Output 1 P3_IOCR8 PC9 1X10B P3 14 RXD1B ASC1_PISEL RIS 1 P3_IOCR12 PC14 0XXXB Input P3_IOCR12 PC14 1X01B Output 1 P3_IOCR12 PC14 1X10B P3 8 TXD1 P3_IOCR8 PC8 1X10B Output P3 15 TXD1 P3_IOCR12 PC15 1X10B Output 1 Applicable in Synchronous Mode only Table 16 8 ASC0 ASC1 I O Control Se...

Page 1117: ...rupt Service Request Control Register F0H Reset Value 0000 0000H RSRC Receive Interrupt Service Request Control Register F4H Reset Value 0000 0000H ESRC Error Interrupt Service Request Control Register F8H Reset Value 0000 0000H TBSRC Transmit Buffer Interrupt Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5...

Page 1118: ... module identification registers are 0000 4402H 0 9 8 11 31 16 r Reserved Read as 0 should be written with 0 Table 16 9 DMA Request Lines of ASC0 ASC1 Module Related ASC Interrupt DMA Request Line Description ASC0 RIR ASC0_RDR DMA Channel 00 Request Input 5 DMA Channel 06 Request Input 5 TIR ASC0_TDR DMA Channel 02 Request Input 5 DMA Channel 04 Request Input 5 TBIR ASC0_TBDR DMA Channel 02 Reques...

Page 1119: ...ister F000 0A08H U SV BE 0000 44XXH Reserved F000 0A0CH BE BE ASC0_ CON ASC0 Control Register F000 0A10H U SV U SV 0000 0000H ASC0_ BG ASC0 Baud Rate Timer Reload Register F000 0A14H U SV U SV 0000 0000H ASC0_ FDV ASC0 Fractional Divider Register F000 0A18H U SV U SV 0000 0000H Reserved F000 0A1CH BE BE ASC0_ TBUF ASC0 Transmit Buffer Register F000 0A20H U SV U SV 0000 0000H ASC0_ RBUF ASC0 Receiv...

Page 1120: ...00 0000H ASC1_ BG ASC1 Baud Rate Timer Reload Register F000 0B14H U SV U SV 0000 0000H ASC1_ FDV ASC1 Fractional Divider Register F000 0B18H U SV U SV 0000 0000H Reserved F000 0B1CH BE BE ASC1_ TBUF ASC1 Transmit Buffer Register F000 0B20H U SV U SV 0000 0000H ASC1_ RBUF ASC1 Receive Buffer Register F000 0B24H U SV U SV 0000 0000H Reserved F0000B28H F000 0B4CH BE BE ASC1_ WHBCON ASC1 Write Hardwar...

Page 1121: ...ASC1_ ESRC ASC1 Error Interrupt Service Req Control Reg F000 0BF8H U SV U SV 0000 0000H ASC1_ TBSRC ASC1 Transmit Buffer Interrupt Service Req Control Reg F000 0BFCH U SV U SV 0000 0000H Table 16 10 Address Map of ASC0 ASC1 cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1122: ...rupt control address decoding clock control see Page 17 43 Note The SSC kernel register names described in Section 17 2 are referenced in the TC1784 User s Manual by the module name prefix SSC0_ for the SSC0 interface by SSC1_ for the SSC1 interface and by SSC2_ for the SSC2 interface 17 1 SSC Kernel Description Figure 17 1 shows a global view of the SSC interface Figure 17 1 General Block Diagram...

Page 1123: ...y 1 to 15 data bits Programmable shift direction LSB or MSB shift first Programmable clock polarity Idle low or idle high state for the shift clock Programmable clock data phase Data shift with leading or trailing edge of the shift clock Baud rate generation Master Mode 33 25 Mbit s to 507 4 bit s 66 5 MHz module clock Master Mode 45 0 Mbit s to 686 65 bit s 90 MHz module clock Slave Mode 16 625 M...

Page 1124: ...lave or multi master interconnections or can operate compatibly with the popular SPI interface It can be used to communicate with shift registers I O expansion peripherals e g EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clo...

Page 1125: ...nerator MCB06214a_mod Error Int Request Internal Bus Status Control Receive Int Request Transmit Int Request TIR RIR EIR Shift Clock fSSC SLSO 7 0 1 MTSRB MRST MTSRA MRSTB 1 MTSR 1 MRSTA 1 SCLKB SCLK 1 SCLKA 1 These signals are used in master mode only fCLC SLSI 7 1 SSC Enabled M S Selected 7 Receive Buffer Register RB Transmit Buffer Register TB Slave Select Output Generation Unit SLSOANDO 7 0 1 ...

Page 1126: ...VAL and the receive interrupt request line RIR will be activated If no further transfer is to take place TB is empty STAT BSY will be cleared at the same time Software should not modify STAT BSY as this flag is hardware controlled Note Only one SSC can be master at a given time The following features of the serial data bit transfer can be programmed The data width can be selected from 2 to 16 data...

Page 1127: ...the clock line in the idle state For an idle high clock the leading edge is a falling one a 1 to 0 transition see Figure 17 3 Figure 17 3 Serial Clock SCLK Phase and Polarity Options 17 1 2 2 Full Duplex Operation The description in this section assumes that the SSC is used with software controlled bi directional GPIO port lines that have open drain capability see also Section 17 1 2 6 The various...

Page 1128: ...e 17 4 applies to both MSB first and LSB first operation When initializing the devices in this configuration one device must be selected for master operation while all other devices must be programmed for slave operation Initialization includes the operating mode of the device s SSC and also the function of the respective port lines Figure 17 4 SSC Full Duplex Configuration The data output pins MR...

Page 1129: ...faces are enabled the master device can initiate the first data transfer by writing the transmit data into register TB This value is copied into the shift register assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the shift clock generator transmission only starts if CON EN 1 Depending on the selected clock pha...

Page 1130: ...d the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line Only the ...

Page 1131: ...two successive frames if no delays are selected For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices that can operate with or require more than 16 data bits per transfer It is just a matter for software how long a total data frame length can be This option can also be used e g to interface to byte wide and word wide devices on t...

Page 1132: ... the parity bit preceeds or follows the transmitted data bits If receive parity is enabled CON PARREN 1 and the last bit of a frame has been received the received data of the frame is stored in RB and the received parity bit is stored in STAT PARRVAL The received and calculated parity bits are now compared If this comparison fails a parity error is detected and the error status flag STAT PARE is s...

Page 1133: ...lines to be connected to two inputs coming from different port pins Operation of the SSC I O lines depends on the selected operating mode master or slave The direction of the port lines depends on the operating mode The SSC will automatically use the correct kernel output or kernel input line of the ports when Parity Bit Bit BM Bit 3 Bit 1 SSC_Parity1_mod Bit 0 Parity Mode Disabled Data Frame with...

Page 1134: ...l should be typically used In this case port registers must be programmed for alternate output and input selection When switching between master and slave mode port registers must be reprogrammed Using the open drain output feature of port lines helps to avoid bus contention problems and reduces the need for hard wired hand shaking or slave select lines In open drain output mode it is not always n...

Page 1135: ...s mode the desired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baud rate 17 1 BR_VALUE represents the content of the reload register taken as an unsigned 16 bit integer while Baud rateSSC is equal to fSCLK as shown in Figure 17 7 The ma...

Page 1136: ...om fFPI must be taken into account Section 17 3 4 1 on Page 17 48 describes these dependencies in detail Table 17 1 Typical Asynchronous Baud Rates using Fixed Input Clock Dividers Reload Value Baud Rate fSCLK Deviation 0000H 45 Mbit s only in Master Mode 0 0 0001H 22 5 Mbit s 0 0 0003H 11 25 Mbit s 0 0 002CH 1 Mbit s 0 0 0063H 450 kbit s 0 0 01C1H 100 kbit s 0 0 1194H 10 kbit s 0 0 AFC7H 1 kbit s...

Page 1137: ...SLSIS 000B and Slave Mode selected the SLSI input line does not control the SSC I O lines The slave receive input signal MTSRA or MTSRB selected by PISEL SRIS and the slave clock input signal SCLKA or SCLKB selected by PISEL SCIS are passed further as MTRSI and SCLKI to the internal SSC control logic The slave transmit signal MRSTI from the internal SSC control logic MRSTI is passed directly to MR...

Page 1138: ...ve select output lines SLSO 7 0 for serial transmit operations The slave select output generation unit further makes it possible to adjust the chip select timing parameters The active inactive state of a slave select output as well as the enable disable state can be controlled individually for each slave select output see Figure 17 10 The basic slave select output timing is shown in Figure 17 9 as...

Page 1139: ...lled by bit fields in the Slave Select Output Timing Control Register SSOTC Each of these bit fields can contain a value from 0 to 3 defining delay cycles of 0 to 3 multiples of the tSCLK shift clock period The three parameters are 1 Number of leading delay cycles tSLSOL SSOTC LEAD tSCLK 2 Number of trailing delay cycles tSLSOT SSOTC TRAIL tSCLK 3 Number of inactive delay cycles tSLSOI SSOTC INACT...

Page 1140: ...e is not delayed The timing of SLSO7 in the delayed mode is shown in Figure 17 11 The bold lines show the timing of SLSO7 in normal operating mode and the dotted lines show the timing of SLSO7 in delayed mode Figure 17 11 SLSO7 Delayed Mode Slave Select Register Update At the start of an internal transmit sequence with the TB register write operation the parameters in registers SSOC and SSOTC are ...

Page 1141: ... the corresponding error enable bits have been set see Figure 17 12 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not cleared automatically but must be cleared via register EFM after servicing This allows servicing of some error conditions via interrupt while others may be polled by software The error status flags can b...

Page 1142: ...EN sets the error interrupt request line EIR The old data in the receive buffer RB will be overwritten with the new value and is irretrievably lost A Phase Error Master or Slave Mode is detected when the incoming data at pin MRST Master Mode or MTSR Slave Mode sampled with the same frequency as the module MCA05789a_mod_ist Error Interrupt EIR 1 EFM SETTE EFM CLRTE EFM SETRE EFM CLRRE EFM SETPE EFM...

Page 1143: ... after a finished transfer immediately a next clock cycle for a new transfer If baud rate error is enabled and the transmit buffer of the slave SSC is loaded with a new value for the next data frame while the current data frame is not yet finished while STAT BSY 1 the slave SSC expects continuation of the clock pulses for the next data frame transmission immediately after finishing the current dat...

Page 1144: ...N the error interrupt request line EIR Note A slave with push pull output drivers not selected for transmission will normally have its output drivers switched off However to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baud rate transmit error can be identified...

Page 1145: ... SSC Mode control logic Reading SSOTC returns the state of CON EN for SSOTC EN Writing to SSOTC with QSMEN 1 sets CON EN if SSOTC EN is written with 1 and clears CON EN if SSOTC EN is written with 0 Compared to the timing parameters stored in register SSOTC LEAD TRAIL INACT and SLSO7MOD the Queued SSC Mode control bits QSMEN and EN are a not latched and directly control the receive transmit functi...

Page 1146: ...e addresses with an offset of 4 With the CON write operation CON EN is set to 0 SSC disabled The BR SSOC and SSOTC write operations program the SSC slave parameters such as baud rate frame layout and slave select output timing The fourth write operation to SSOTC enables again the SSC by writing SSOTC QSMEN 1 and SSOTC EN 1 After DMA channel 1 has finished this 4 byte control setup transaction it c...

Page 1147: ... 17 26 V1 1 2011 05 SSC V1 5 Figure 17 14 SSC Error Interrupt Control QueuedSSCMode DMA Channel 1 CON DMA Channel 2 Control Tasks Transmit Data Task EN 0 BR SSOC SSOTC EN 1 QSMEN 1 10H Offset Addr 14H 18H 1CH TB 20H DMA Channel 3 Receive Data Task TB 24H ...

Page 1148: ...nterface and SSC2_ for the SSC2 interface All registers in the SSC address spaces are reset with the application reset definition see SCU section Reset Operation SSC Kernel Register Overview Figure 17 15 SSC Kernel Registers The complete and detailed address map of the SSC modules is described at the end of this chapter Table 17 3 Registers Address Space SSC Kernel Registers Module Base Address En...

Page 1149: ...7 28 CON Control Register 10H Page 17 31 BR Baud Rate Timer Reload Register 14H Page 17 41 STAT Status Register 28H Page 17 34 EFM Error Flag Modification Register 2CH Page 17 36 SSOC Slave Select Output Control Register 18H Page 17 38 SSOTC Slave Select Output Timing Control Register 1CH Page 17 39 TB Transmit Buffer Register 20H Page 17 42 RB Receive Buffer Register 24H Page 17 42 ID Module Iden...

Page 1150: ...19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 STIP 0 SLSIS SCIS SRIS MRI S r rw r rw rw rw rw Field Bits Type Description MRIS 0 rw Master Mode Receive Input Select MRIS selects the receive input line in Master Mode 0B Receive input line MRSTA is selected 1B Receive input line MRSTB is selected SRIS 1 rw Slave Mode Receive Input Select SRIS selects receive input line in Slave Mode 0B Rec...

Page 1151: ...r operation 101B SLSI input line 5 is selected for operation 110B SLSI input line 6 is selected for operation 111B SLSI input line 7 is selected for operation In the TC1784 other combinations of SLSIS except 000B and 001B are reserved and must not be used STIP 8 rw Slave Transmit Idle State Polarity This bit determines the logic level of the Slave Mode transmit signal MRST when the SSC slave selec...

Page 1152: ...r rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN MS 0 A REN BEN PEN REN TEN LB PO PH HB BM rw rw r rw rw rw rw rw rw rw rw rw rw Field Bits Type Description BM 3 0 rw Frame Width Selection BM determines the number of bits of the serial frame PAREN 0 parity mode disabled 0000B Reserved do not use this combination 0001B Frame width is 2 bits 2 data bits 0010B Frame width is 3 bits 3 data bits ...

Page 1153: ...ock line is high the leading clock edge is high to low transition LB 7 rw Loop Back Control 0B Normal output 1B Receive input is connected to transmit output Half duplex Mode TEN 8 rw Transmit Error Enable 0B Ignore transmit errors 1B Check transmit errors REN 9 rw Receive Error Enable 0B Ignore receive errors 1B Check receive errors PEN 10 rw Phase Error Enable 0B Ignore phase errors 1B Check pha...

Page 1154: ...ued SSC mode by bit SSOTC EN see Page 17 24 PARTEN 16 rw Parity Transmit Enable Bit This bit enables the parity mode for the transmission of frames 0B Parity mode for transmission is disabled 1B Parity mode for transmission is enabled PARREN 17 rw Parity Receive Enable Bit This bit enables the parity mode for the reception of frames 0B Parity mode for reception is disabled 1B Parity mode for recep...

Page 1155: ...d Bits Type Description BC 3 0 rh Bit Count Status BC indicates the current status of the shift counter The shift counter is updated with every shifted bit PARE 4 rh Parity Error Flag 0B No error 1B Received parity bit is wrong PARTVAL 5 rh Parity Transmit Value If parity mode is enabled this bit indicates the calculated parity bit for the transmission of the actual serial frame PARTVAL is written...

Page 1156: ...tion completed before the receive buffer was read PE 10 rh Phase Error Flag 0B No error 1B Received data changes during the sampling clock edge BE 11 rh Baud Rate Error Flag 0B No error 1B There is more than factor 2 or less than factor 0 5 between the slave s actual and the expected baud rate BSY 12 rh Busy Flag BSY is set while a transfer is in progress 0 7 31 13 r Reserved Read as 0 should be w...

Page 1157: ...TE CLR BE CLR PE CLR RE CLR TE 0 SET PAR E 0 CLR PAR E w w w w w w w w r w r w Field Bits Type Description CLRPARE 0 w Clear Parity Error Flag 0B No effect 1B Bit STAT PARE is cleared Bit is always read as 0 SETPARE 4 w Set Parity Error Flag 0B No effect 1B Bit STAT PARE is set Bit is always read as 0 CLRTE 8 w Clear Transmit Error Flag 0B No effect 1B Bit STAT TE is cleared Bit is always read as ...

Page 1158: ...STAT BE is cleared Bit is always read as 0 SETTE 12 w Set Transmit Error Flag 0B No effect 1B Bit STAT TE is set Bit is always read as 0 SETRE 13 w Set Receive Error Flag 0B No effect 1B Bit STAT RE is set Bit is always read as 0 SETPE 14 w Set Phase Error Flag 0B No effect 1B Bit STAT PE is set Bit is always read as 0 SETBE 15 w Set Baud Rate Error Flag 0B No effect 1B Bit STAT BE is set Bit is a...

Page 1159: ... 9 8 7 6 5 4 3 2 1 0 OEN 7 OEN 6 OEN 5 OEN 4 OEN 3 OEN 2 OEN 1 OEN 0 AOL 7 AOL 6 AOL 5 AOL 4 AOL 3 AOL 2 AOL 1 AOL 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description AOLn n 0 7 n rw Active Output Level 0B SLSOn is at low level during the chip select active time tSLSOACT The high level is the inactive level of SLSOn 1B SLSO line n is at high level during the chip select a...

Page 1160: ...This bit field determines the number of leading delay clock cycles A leading delay clock cycle is always a multiple of an SCLK shift clock period 00B Zero leading delay clock cycle selected1 01B One leading delay clock cycle selected 10B Two leading delay clock cycles selected 11B Three leading delay clock cycles selected TRAIL 3 2 rw Slave Output Select Trailing Delay This bit field determines th...

Page 1161: ...or the SLSO7 slave select output 0B Normal mode selected for SLSO7 1B Delayed mode selected for SLSO7 QSMEN 14 w Queued SSC Mode Enabled 0B When QSMEN is written with 0 the state of bit SSOTC EN is don t care In this case the enable disable of the SSC is controlled by bit CON EN only Note that EN should only be cleared by software while no transfer is in progress STAT BSY 0 1B When QSMEN is writte...

Page 1162: ...d rate timer BR Baud Rate Timer Reload Register 14H Reset Value 0000 0000H 31 16 15 0 0 BR_VALUE r rw Field Bits Type Description BR_VALUE 15 0 rw Baud Rate Timer Reload Register Value Reading BR returns the 16 bit content of the baud rate timer Writing BR loads the baud rate timer reload register with BR_VALUE 0 31 16 r Reserved Read as 0 should be written with 0 ...

Page 1163: ... 15 0 rw Transmit Data Register Value Register TB stores the data value to be transmitted TB_VALUE Unused bits of TB_VALUE as defined by CON BM are ignored during transmission 0 31 16 r Reserved Read as 0 should be written with 0 RB Receive Buffer Register 24H Reset Value 0000 0000H 31 16 15 0 0 RB_VALUE r rh Field Bits Type Description RB_VALUE 15 0 rh Receive Data Register Value Register RB cont...

Page 1164: ...The reset values of the SSCx_ID module identification registers are 0000 4512H 17 3 2 Interfaces of the SSC Modules Figure 17 16 and Figure 17 17 show the TC1784 specific implementation details and interconnections of the SSC0 SSC1 SSC2 modules Each of the SSC modules is supplied with a separate clock control interrupt control and address decoding logic Two interrupt outputs can be used to generat...

Page 1165: ...1 MRSTA MTSRB MRST MTSRA SCLKB SCLK SCLKA Slave Slave Master Slave SLSI 7 2 3 Port 1 Control SLSO6 SSC0_RDR SSC1_RDR To DMA To DMA Enable 1 M S Select 1 MCB06225_mod P3 7 SLSO02 SLSO12 P3 3 MRST0 P3 4 MTSR0 P3 2 SCLK0 P3 7 SLSI0 P3 5 SLSO00 SLSO10 SLSOANDO0 P1 10 SLSO17 P2 8 SLSO04 SLSO14 P2 9 SLSO05 SLSO15 P2 10 MRST1A P2 12 MTSR1A P2 11 SCLK1A P2 13 SLSI1 P3 8 SLSO06 P2 1 SLSO03 SLSO13 P1 9 MRST...

Page 1166: ...MA P5 6 MTSR2A MTSR2 P5 5 MRST2A MRST2 P5 7 SCLK2A SCLK2 P5 4 SLSO24 SLSI2A SLSO 4 0 A1 A1 A1 A1 P5 0 SLSO20 A1 P5 1 SLSO21 A1 P5 2 SLSO22 A1 P5 3 SLSO23 A1 Port 10 Control P10 1 MTSR2B MTSR2 P10 0 MRST2B MRST2 P10 2 SCLK2B SCLK2 P10 3 SLSO20 SLSI2B A1 A1 A1 A1 P10 4 SLSO21 A1 P10 5 SLSO22 A1 P10 6 SLSO23 SLSOANDO3 A1 P10 7 SLSO24 SLSOANDO4 A1 SLSI2 SLSO 7 5 1 5 1 These lines are not connected 2 T...

Page 1167: ... SSC0_RDR DMA Channel 00 Request Input 4 DMA Channel 10 Request Input 4 DMA Channel 06 Request Input 4 DMA Channel 16 Request Input 4 TIR SSC0_TDR DMA Channel 02 Request Input 4 DMA Channel 12 Request Input 4 DMA Channel 04 Request Input 4 DMA Channel 14 Request Input 4 SSC1 RIR SSC1_RDR DMA Channel 01 Request Input 4 DMA Channel 11 Request Input 4 DMA Channel 07 Request Input 4 DMA Channel 17 Req...

Page 1168: ...or the module kernel specific registers Figure 17 18 SSC0 SSC1 SSC2 Implementation specific Special Function Registers P1_IOCR8 MCA06226_3_mod SSC0_CLC SSC1_CLC SSC0_TSRC P2_IOCR0 SSC0_RSRC SSC0_ESRC SSC1_TSRC SSC1_RSRC SSC1_ESRC Clock Control Registers Interrupt Registers Port Registers P5_IOCR4 SSC0_FDR SSC1_FDR P3_IOCR0 P3_IOCR4 P1_PDR P2_PDR P3_PDR P2_IOCR8 P2_IOCR12 SSC2_FDR SSC2_CLC P5_IOCR1...

Page 1169: ...baud rate of the serial data The fractional divider registers SSCx_FDR control the frequency of fSSCx and make it possible to enable disable it independently of fCLCx The Baud Rate Timer Reload Register SSCx_BR define serial data baud rate dependent from the frequency of fSSCx Figure 17 19 SSC Clock Generation MCA06227_3_mod Clock Control Register SSC0_CLC fCLC0 SSC0 Clock Generation fSSC0 fSYS fF...

Page 1170: ...aximum shift clock frequency is fSSCx 4 Combined with the formulas of the baud rate generator see Page 17 14 and the fractional divider the resulting serial data baud rate is defined by 17 4 17 5 Note Equation 17 2 and Equation 17 4 apply to normal divider mode of the fractional divider FDR DM 01B Equation 17 3 and Equation 17 5 apply to fractional divider mode FDR DM 10B fSSCx fSYS 1 n with n 102...

Page 1171: ... 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the suspend mode EDIS 3 rw S...

Page 1172: ...Value 1000 0000H SSC2_FDR SSC2 Fractional Divider Register 0CH Reset Value 1000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or im...

Page 1173: ...n selection IOCR registers Pad driver characteristics selection for the outputs PDR registers The SSC0 SSC1 SSC2 port input output control registers contain the bit fields that select the digital output and input driver characteristics such as pull up down devices port direction input output open drain and alternate output selections SUSACK 28 rh Suspend Mode Acknowledge Indicates state of SPNDACK...

Page 1174: ...SO1 SLSO2 SLSO3 SLSO4 SLSO5 SLSO6 P3 5 SLSO00 SLSO10 SLSOANDO0 P3 6 SLSO01 SLSO11 SLSOANDO1 P3 7 SLSO02 SLSO12 P2 1 SLSO03 SLSO13 P2 8 SLSO04 SLSO14 P2 9 SLSO05 SLSO15 SLSOANDI0 SLSOANDO0 SLSOANDI1 SLSOANDO1 P5 13 SLSO16 A1 P5 12 SLSO07 A1 P1 10 SLSO17 A2 SSC2 SLSO1 SLSO2 SLSO3 SLSO4 SLSOANDI3 SLSOANDO3 SLSOANDI4 SLSOANDO4 P5 0 SLSO20 A1 P5 1 SLSO21 A1 P10 5 SLSO22 A1 P5 2 SLSO22 A1 A1 P5 3 SLSO23...

Page 1175: ...P3_IOCR0 PC3 0XXXB Input P3_IOCR0 PC3 1X01B Output P3_IOCR0 PC3 1X10B P3 2 SCLK0 P3_IOCR0 PC2 0XXXB Input P3_IOCR0 PC2 1X01B Output P3_IOCR0 PC2 1X10B P3 7 SLSI0 P3_IOCR4 PC7 0XXXB Input P3 5 SLSO00 P3_IOCR4 PC5 1X01B Output P3 6 SLSO01 P3_IOCR4 PC6 1X01B Output P3 7 SLSO02 P3_IOCR4 PC7 1X01B Output P2 1 SLSO03 P2_IOCR0 PC1 1X10B Output P2 8 SLSO04 P2_IOCR8 PC8 1X01B Output P2 9 SLSO05 P2_IOCR8 PC...

Page 1176: ...C9 0XXXB Input P1_IOCR8 PC9 1X11B Output P1 11 SCLK1B P1_IOCR8 PC11 0XXXB Input P1_IOCR8 PC11 1X11B Output P2 13 SLSI1 P2_IOCR12 PC13 0XXXB Input P3 5 SLSO10 P3_IOCR4 PC5 1X10B Output P3 6 SLSO11 P3_IOCR4 PC6 1X10B Output P3 7 SLSO12 P3_IOCR4 PC7 1X10B Output P2 1 SLSO13 P2_IOCR0 PC1 1X11B Output P2 8 SLSO14 P2_IOCR8 PC8 1X10B Output P2 9 SLSO15 P2_IOCR8 PC9 1X10B Output P1 10 SLSO17 P1_IOCR8 PC10...

Page 1177: ...1X01B Output P5 4 SLSI2A P5_IOCR4 PC4 0XXXB Input P10 3 SLSI2B P10_IOCR0 PC3 0XXXB Input P5 0 SLSO20 P5_IOCR0 PC0 1X11B Output P5 1 SLSO21 P5_IOCR0 PC1 1X11B Output P5 2 SLSO22 P5_IOCR0 PC2 1X11B Output P5 3 SLSO23 P5_IOCR0 PC3 1X11B Output P5 4 SLSI2A SLSO24 P5_IOCR4 PC4 0XXXB Input P5_IOCR4 PC4 1X11B Output P10 3 SLSI2B SLSO20 P10_IOCR0 PC3 0XXXB Input P10_IOCR0 PC3 1X01B Output P10 4 SLSO21 P10...

Page 1178: ... SSC2 P3 5 SLSOANDO0 P3_IOCR4 PC5 1X11B Output P3 6 SLSOANDO1 P3_IOCR4 PC6 1X11B Output P10 6 SLSOANDO3 P10_IOCR4 PC6 1X10B Output P10 7 SLSOANDO4 P10_IOCR4 PC7 1X10B Output Table 17 6 SSC0 SSC1 SSC2 I O Line Selection and Setup cont d Module Port Lines Input Output Control Register Bits I O ...

Page 1179: ...upt Service Request Control Register F4H Reset Value 0000 0000H RSRC Receive Interrupt Service Request Control Register F8H Reset Value 0000 0000H ESRC Error Interrupt Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description S...

Page 1180: ...BE 0000 45XXH SSC0_ FDR SSC0 Fractional Divider Register F010 010CH U SV SV E 1000 0000H SSC0_CON SSC0 Control Register F010 0110H U SV U SV 0000 0000H SSC0_ BR SSC0 Baud Rate Timer Reload Register F010 0114H U SV U SV 0000 0000H SSC0_ SSOC SSC0 Slave Select Output Control Register F010 0118H U SV U SV 0000 0000H SSC0_ SSOTC SSC0 Slave Select Output Timing Control Register F010 011CH U SV U SV 000...

Page 1181: ...R SSC1 Baud Rate Timer Reload Register F010 0214H U SV U SV 0000 0000H SSC1_ SSOC SSC1 Slave Select Output Control Register F010 0218H U SV U SV 0000 0000H SSC1_ SSOTC SSC1 Slave Select Output Timing Control Register F010 021CH U SV U SV 0000 0000H SSC1_ TB SSC1 Transmit Buffer Register F010 0220H U SV U SV 0000 0000H SSC1_ RB SSC1 Receive Buffer Register F010 0224H U SV U SV 0000 0000H SSC1_STAT ...

Page 1182: ...Slave Select Output Control Register F010 0318H U SV U SV 0000 0000H SSC2_ SSOTC SSC2 Slave Select Output Timing Control Register F010 031CH U SV U SV 0000 0000H SSC2_ TB SSC2 Transmit Buffer Register F010 0320H U SV U SV 0000 0000H SSC2_ RB SSC2 Receive Buffer Register F010 0324H U SV U SV 0000 0000H SSC2_STAT SSC2 Status Register F010 0328H U SV U SV 0000 0000H SSC2_ EFM SSC2 Error Flag Modifica...

Page 1183: ...al description of the MSC kernel see Page 18 3 MSC kernel register descriptions see Page 18 36 TC1784 implementation specific details and registers of the MSC module port connections and control interrupt control address decoding and clock control see Page 18 62 Note The MSC kernel register names described in Section 18 2 are also referenced in the TC1784 User s Manual by the module name prefix MS...

Page 1184: ...tream channel The MSC receives data and status back from the power device via a low speed asynchronous serial data stream upstream channel Figure 18 1 shows a typical TC1784 application in which an MSC interface controls two power devices Output data is provided by the GPTA module Figure 18 1 MSC to External Power Device Connection Some applications are Control of the external power switching unit...

Page 1185: ...s Eight output lines are required for the serial communication of the downstream channel clock data and enable signals One out of eight input lines SDI 7 0 is used as serial data input signal for the upstream channel The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL ALTINH input lines These input lines are ...

Page 1186: ...ecise frequency control of serial clock fMSC Command data and passive frame types Start of serial frame Software controlled timer controlled or free running Transmission with or without SEL bit Flexible chip select generation indicates status during serial frame transmission Emergency stop without CPU intervention Low speed asynchronous serial reception on upstream channel Baud rate fMSC divided b...

Page 1187: ...ownstream Channel Block Diagram The enable signals ENL ENH and ENC indicate certain phases of the serial transmission in relation to the serial clock FCL In the I O control logic these signals can be combined to four enable select outputs EN 3 0 For supporting differential output drivers the serial clock output FCL and the serial data output SO are available in both polarities indicated by the sig...

Page 1188: ...two parts The SRL active phase in which the content of the shift register low part SRL is transmitted and the SRH active phase in which the content of the shift register high part SRH is transmitted At the beginning of the SRL and SRH active phase a selection bit SELL can be optionally inserted into the serial data stream In the frame shown in Figure 18 4 SELL is generated at the beginning of the ...

Page 1189: ...to 32 bits In other words whenever bits of SRH are transmitted they are always preceded by the transmission of the complete SRL content During the active phase of a command frame the enable output signal ENC becomes active The enable output signals ENL and ENH remain inactive The passive phase of a command frame always has a fixed length of 2 tFCL The diagram shown in Figure 18 5 assumes that the ...

Page 1190: ...o bit shifted out 1 0 2 3 000001B SRL 0 shifted out 1 1 2 4 000010B SRL 1 0 shifted out 1 2 2 5 000011B SRL 2 0 shifted out 1 3 2 6 001111B SRL 14 0 shifted out 1 15 2 18 010000B SRL 15 0 shifted out 1 16 2 19 010001B SRL 15 0 and SRH 0 shifted out 1 17 2 20 010010B SRL 15 0 and SRH 1 0 shifted out 1 18 2 21 010011B SRL 15 0 and SRH 2 0 shifted out 1 19 2 22 011111B SRL 15 0 and SRH 14 0 shifted o...

Page 1191: ...tive and during the SRH active phase of a data frame the enable output signal ENH becomes active The enable output signal ENC remains inactive The length of the data frame s passive phase is variable and is defined by bit field DSC PPD It can be within a range of 2 tFCL up to 31 tFCL The diagram shown in Figure 18 6 assumes that the FCL clock is only generated during the active phase of the data f...

Page 1192: ...active phase Table 18 3 Data Frame SRL SRH Length Parameters DSC NDBL SRL Bits Transmitted in SRL Active Phase DSC NDBH SRH Bits Transmitted in SRH Active Phase 00000B No SRL bit transmitted 00000B No SRH bit transmitted 00001B SRL 0 00001B SRHL 0 00010B SRL 1 0 00010B SRH 1 0 00011B SRL 2 0 00011B SRH 2 0 01111B SRL 14 0 01111B SRH 14 0 10000B SRL 15 0 10000B SRH 15 0 Other bit combinations Reser...

Page 1193: ... has the length defined by the five data frame parameters according Equation 18 1 They are generated only in Data Repetition Mode Under special conditions command frame insertion passive time frames can be shortened see Figure 18 9 During passive time frames the data output SO have to be considered as invalid at the receiving device and the clock output FCL may toggle or not as selected by bit OCR...

Page 1194: ...18 7 shows the logic that is implemented for the SRL shift register loading operation The logic for the SRH shift register loading operation is equivalent to the one for the SRL register Its differences in data sources and register controls are described later in this section Figure 18 7 SRL Shift Register Data Loading Control MCA06233 ALTINL x To SRL bit x SLx DSDSL DDH 32 15 16 0 DDL x DDL Downs...

Page 1195: ... the downstream control register is loaded completely into SRL Table 18 5 summarizes all SRL data source selection capabilities x 0 15 SRH Shift Register Loading The SRH shift register load operation is equivalent to the SRL shift register load operation The following differences must be taken into account for SRH shift register loading Input lines ALTINH are connected instead of ALTINL input line...

Page 1196: ...e downstream channel is idle If a data frame or a command frame is currently processed and output the data frame transmission is delayed and started when the active downstream frame has been finished The data pending bit DSC DP becomes cleared by hardware when the first bit of the data frame is sent out A command frame always has priority over the data frame This means that if both frame pending b...

Page 1197: ... of the last transmitted passive time frame At the next TRP a data frame is started if no command frame has been requested and DSC DP is cleared again by hardware after the data frame has been started Data Frames are always aligned to time reference points This means they always start at a TRP Passive time frames can be shortened This is especially the case when command frames are inserted Continu...

Page 1198: ... data frame is not of the same length this is the case in diagram B to F a shortened passive time frame is inserted until the next TRP is reached This ensures that the next data or normal passive time frame is again aligned to a TRP Figure 18 10 is a flow diagram of the Data Repetition Mode This diagram especially shows the behavior of the data and command pending bits DSC DP and DSC CP If both fr...

Page 1199: ...tatus flags DSS DFA is set during a data frame transmission and DSS CFA is set during a command frame transmission Further the downstream counter DSS DC indicates the number of shift clock periods that have been elapsed since the start of the current data command or passive time frame MCA06236 Starting Data Repetition Mode writing DSC TM 1 DSC CP 1 yes no TRP reached DSC DP 1 Start passive time fr...

Page 1200: ...time frames have been already transmitted after the last regular data frame occurrence The passive time frame counter counts up from 0000B to the value which has been written into bit field DSS NPTF number of passive time frames DSS PFC 0000B indicates that a data frame is requested for transmission Figure 18 11 Passive Frame Counter Operation with DSS NPTF 0101B MCT06237 DF PTF PTF PTF PTF DF PTF...

Page 1201: ...p again with the next frame independently whether a data frame command frame or passive time frame is started as next frame Figure 18 12 shows an example of downstream channel data frame transmission In this example the selection bit for the SRL active frame is enabled ENSELL 1 and the selection bit for the SRH active frame is disabled ENSELH 0 With loading of the shift register SRL SRH the downst...

Page 1202: ...device specific and depends on the implementation of the MSC module The TC1784 specific clock generation is described on Page 18 65 18 1 2 6 Abort of Frames Only a reset condition of the device can abort a current transmission The MSC module does not start a new frame transmission when the downstream channel becomes disabled the suspend mode is requested or the sleep mode is entered If one of thes...

Page 1203: ...k Diagram The incoming data at SI is sampled after it has been filtered for spikes The detected logic states of the serial input are clocked into a shift register After the complete reception of the serial data frame the content of the shift register is transferred into one of the four data registers and an interrupt can be generated optionally The reception baud rate is directly coupled to the mo...

Page 1204: ... error flag PERR in the related Upstream Data Register UDx is set Note that a setting of the parity error flag PERR does not generate an interrupt The PERR bits must be checked by software The UDx registers also store the parity bit of the incoming data frame UDx P and the parity bit that is generated internally UDx IPF Bit USR PCTR determines the parity mode even or odd that is selected for parit...

Page 1205: ...bed on Page 18 30 Frame Reception with Address Field Frame reception for a 16 bit data frame see Figure 18 16 is selected by USR UFT 1 When the content of the receive buffer has been received completely it is transferred to one of the four UDx registers The two most significant address bits A 3 2 of the received 4 bit address field select the number x of register UDx in which the received frame co...

Page 1206: ...eme is comparable with that of the 16 bit data frame reception but there are a few differences The upstream counter is initially loaded with 01100B The received frame content is always stored in register UD0 Bit field UD0 LABF is always loaded with 00B when the frame is stored MCT06242 D0 D1 D7 D6 Start P 16 bit Upstream Data Frame A3 A2 Stop Stop 16 15 14 13 12 11 10 4 3 2 1 0 0 A1 5 Sampling Shi...

Page 1207: ...able clock divider The frequency of fBR determines the width of a received bit cell and therefore the baud rate for the received data The content of bit field USR URR selects the baud rate according Table 18 6 The resulting baud rate formula is 18 2 Note With the USR URR 000B the upstream channel is disabled and data reception is not possible Table 18 6 Upstream Channel Divide Factor DF Selection ...

Page 1208: ... DF as shown in Table 18 6 is reached In the middle of the sampling counter s count range the logic state at SI is evaluated and in case of a data bit latched in the receive buffer s shift register With the reload of the sampling counter the shift register is shifted by one bit position Figure 18 18 Upstream Channel Sampling with URR 010B 18 1 3 5 Spike Filter The upstream channel input line SDI i...

Page 1209: ...el Output Control As shown in Figure 18 5 and Figure 18 6 the active phases during downstream channel operation are indicated by three enable signals ENL indicates the SRL active phase of a data frame ENH indicates the SRH active phase of a data frame ENC indicates the active phase of a command frame The chip select output control logic of the MSC uses a signal compressing scheme similar to the in...

Page 1210: ...ine which chip enable output becomes active on a valid internal enable signal In the MSC enable signals are high level active signals If required in a specific application all chip enable outputs ENx can be assigned for low level active polarity by setting bit OCR CSLP Figure 18 20 Downstream Channel Chip Enable Output Control MCA06246 CSL OCR ENL CSH OCR CSC OCR EN0 ENH ENC 1 0 1 0 1 0 1 0 CSLP O...

Page 1211: ...OCR CLP 0 FCLP has identical and FCLN has inverted polarity compared to FCL Setting OCR CLP exchanges the signal polarities of FCLP and FCLN An equivalent control capability is available for the SOP and SON data outputs controlled by OCR SLP One additional control capability not shown in Figure 18 21 is available for the FCL signal With OCR CLKCTRL 1 the FCL clock signal will always be generated i...

Page 1212: ...nnected to up to eight SDI 7 0 serial inputs Bit field OCR SDISEL selects one out of these input lines input signal SDI If OCR ILP 0 SDI is directly connected to the serial receive buffer input SI If OCR ILP 1 SDI is connected to input SI via an inverter Figure 18 22 Upstream Channel Serial Data Input Control MCA06248 ILP OCR 1 0 SI SDI SDI 7 0 SDISEL OCR 3 8 ...

Page 1213: ... interrupt node pointer An interrupt event internally generated as a request pulse is always stored in an interrupt status flag that is located in the Interrupt Status Register ISR All interrupt status flag can be set or cleared individually by software via the interrupt Set Clear Register ISC Software controlled interrupt generation can be initiated by setting the interrupt status flag of the cor...

Page 1214: ...bit must be shifted out for the first data bit shifted interrupt to become active Figure 18 23 Data Frame Interrupt Control 18 1 5 2 Command Frame Interrupt A command frame interrupt can be generated at the end of a downstream channel command frame see also Figure 18 5 Figure 18 24 Command Frame Interrupt Control ISC SDEDI CDEDI Software Clear Software Set EDIE 00 11 Hardware Set EDIE ICR First da...

Page 1215: ... Interrupt A time frame finished interrupt can be generated at the end of a downstream channel passive time phase Figure 18 25 Time Frame Interrupt Control TFIE ICR TFI DTFI ISR Software Set Set MCA06251_mod Time Frame Interrupt to Int Comp Time Frame Finished ISC SDTFI CDTFI Software Set Hardware Set 1 ...

Page 1216: ...ated value is not equal 00H Only an update of register UD3 generates a receive data interrupt The selection of the interrupt generation condition is controlled by bit field ICR RDIE Setting ICR RDIE 0 disables the receive data interrupt in general ISR URDI is the interrupt status flag that can be set or clear when writing bits ISC SURDI or ISC CURDI with a 1 Figure 18 26 Receive Data Interrupt Con...

Page 1217: ...sible to connect more than one interrupt source to one interrupt output SRx Figure 18 27 MSC Interrupt Request Compressor Note The number of available MSC interrupt outputs depends on the implementation of the MSC module s in the specific product see Page 18 72 for TC1784 details MCA06253 EDIP ICR Data Frame Interrupt Receive Data Interrupt RDI EDI 2 2 ECIP ICR Command Frame Interrupt ECI 2 TFIP I...

Page 1218: ...egisters in the MSC address spaces are reset with the application reset definition see SCU section Reset Operation MSC Kernel Register Overview Figure 18 28 MSC Kernel Registers The complete and detailed address map of the MSC0 module is described in Table 18 12 on Page 18 73 Table 18 8 Registers Address Space MSC0 Kernel Registers Module Base Address End Address Note MSC0 F000 0800H F000 08FFH MC...

Page 1219: ... 14H Page 18 41 DSS Downstream Status Register 18H Page 18 44 DD Downstream Data Register 1CH Page 18 59 DC Downstream Command Register 20H Page 18 59 DSDSL Downstream Select Data Source Low Register 24H Page 18 46 DSDSH Downstream Select Data Source High Register 28H Page 18 47 ESR Emergency Stop Register 2CH Page 18 48 UD0 Upstream Data Register 0 30H Page 18 60 UD1 Upstream Data Register 1 34H ...

Page 1220: ...ter 08H Reset Value 0028 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the modu...

Page 1221: ... 10 9 8 7 6 5 4 3 2 1 0 0 P CTR URR UFT r rw rw rw Field Bits Type Description UFT 0 rw Upstream Channel Frame Type This bit determines the frame type used by the upstream channel for data reception 0B 12 bit upstream frame selected 1B 16 bit upstream frame selected with 4 bit address field URR 3 1 rw Upstream Channel Receiving Rate This bit field determines the baud rate for the upstream channel ...

Page 1222: ...A parity bit is set on an odd number of 1s in the serial address data stream 1B Odd parity mode is selected A parity bit is set on an even number of 1s in the serial address data stream UC 20 16 rh Upstream Counter This bit field indicates the content of the upstream counter that counts the bits during upstream channel reception 0 15 5 31 21 r Reserved Read as 0 should be written with 0 Field Bits...

Page 1223: ... NDBH NDBL DP CP TM rh rw rw rw rw rh rh rw Field Bits Type Description TM 0 rw Transmission Mode This bit selects the transmission mode of the downstream channel 0B Triggered Mode selected 1B Data Repetition Mode selected CP 1 rh Command Pending This bit is set when the downstream command register DC is written CP is cleared when the first bit of the related command frame is sent out DP 2 rh Data...

Page 1224: ...uring a data frame 00000B No SRH bit shifted no selection bit is generated the SRH active phase is completely skipped 00001B SRH 0 shifted 00010B SRH 1 0 shifted B 01111B SRH 14 0 shifted 10000B SRH 15 0 shifted Other bit combinations are reserved do not use these bit combinations ENSELL 13 rw Enable SRL Active Phase Selection Bit This bit determines whether a low level selection bit is inserted a...

Page 1225: ...ts of the SRL SRH shift registers are shifted out during transmission of a command frame 000000B No bit shifted 000001B SRL 0 shifted 000010B SRL 1 0 shifted 000011B SRL 2 0 shifted B 010000B SRL 15 0 shifted 010001B SRL 15 0 and SRH 0 shifted 010010B SRL 15 0 and SRH 1 0 shifted B 011111B SRL 15 0 and SRH 14 0 shifted 100000B SRL 15 0 and SRH 15 0 shifted Other bit combinations are reserved do no...

Page 1226: ...ield indicates the count of passive time frames that are currently transmitted In Triggered Mode PFC remains at 0000B 0000B Data frame is transmitted 0001B First passive time frame is transmitted 0010B Second passive time frame is transmitted B 1111B Fifteenth passive time frame is transmitted NPTF 11 8 rw Number Of Passive Time Frames This bit field indicates the number of passive time frames tha...

Page 1227: ...d H 7FH 127 shift clocks elapsed DC is reset at the end of a downstream frame DFA 24 rh Data Frame Active This bit indicates if a data frame is currently sent out 0B No data frame is currently sent out 1B A data frame is currently sent out CFA 25 rh Command Frame Active This bit indicates if a command frame is currently sent out 0B No command frame is currently sent out 1B A command frame is curre...

Page 1228: ...18 17 16 SL15 SL14 SL13 SL12 SL11 SL10 SL9 SL8 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 rw rw rw rw rw rw rw rw Field Bits Type Description SLx x 0 15 2 x 1 2 x rw Select Source for SRL SLx determines which data source is used for the shift register bit SRL x during data frame transmission 00B SRL x is taken from data register DD DDL x 01B Reser...

Page 1229: ... 19 18 17 16 SH15 SH14 SH13 SH12 SH11 SH10 SH9 SH8 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SH0 rw rw rw rw rw rw rw rw Field Bits Type Description SHx x 0 15 2 x 1 2 x rw Select Source for SRH SHx determines which data source is used for the shift register bit SRH x during data frame transmission 00B SRH x is taken from data register DD DDH x 01B R...

Page 1230: ...w rw rw rw Field Bits Type Description ENLx x 0 15 x rw Emergency Stop Enable for Bit x in SRL This bit enables the emergency stop feature selectively for each SRL bit If the emergency stop condition is met and enabled ENLx 1 the SRL x bit is of the data register DD DDL x is used for the shift register load operation 0B Emergency stop feature for bit SRL x is disabled 1B The emergency stop feature...

Page 1231: ...vice request output line SRn n 0 3 for the data frame interrupt 00B Service request output SR0 selected 01B Service request output SR1 selected 10B Service request output SR2 selected 11B Service request output SR3 selected EDIE 3 2 rw Data Frame Interrupt Enable This bit field determines the enable conditions for the data frame interrupt 00B Interrupt generation disabled 01B An interrupt is gener...

Page 1232: ...ime Frame Interrupt Pointer TFIP selects the service request output line SRn n 3 0 for the time frame interrupt 00B Service request output SR0 selected 01B Service request output SR1 selected 10B Service request output SR2 selected 11B Service request output SR3 selected TFIE 11 rw Time Frame Interrupt Enable This bit enables the time frame interrupt 0B Interrupt generation disabled 1B Interrupt g...

Page 1233: ... Interrupt generation disabled 01B An interrupt is generated when data is received and written into the upstream data registers UDx x 0 3 10B An interrupt is generated as with RDIE 01B but only if the received data is not equal to 00H 11B An interrupt is generated when data is received and written into register UD3 0 6 10 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Descript...

Page 1234: ... channel data frame interrupt is generated DEDI can be set or cleared by software when writing to register ISC with the appropriate bits ISC SDEDI or ISC CDEDI set DECI 1 rh Command Frame Interrupt Flag This flag is always set by hardware when a downstream channel command frame interrupt is generated whether or not it is enabled DECI can be set or cleared by software when writing to register ISC w...

Page 1235: ...is flag is always set by hardware when an upstream channel receive data interrupt is generated whether or not it is enabled URDI can be set or cleared by software when writing to register ISC with the appropriate bits SURDI or CURDI set 0 31 4 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1236: ... w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 C DDIS C CP C DP C URDI C DTFI C DECI C DEDI r w w w w w w w Field Bits Type Description CDEDI 0 w Clear DEDI Flag 0B No operation 1B Bit ISR DEDI is cleared CDECI 1 w Clear DECI Flag 0B No operation 1B Bit ISR DECI is cleared CDTFI 2 w Clear DTFI Flag 0B No operation 1B Bit ISR DTFI is cleared CURDI 3 w Clear URDI Flag 0B No operation 1B Bit ISR URDI...

Page 1237: ...n 1B Bit ISR DEDI is set SDECI 17 w Set DECI Flag 0B No operation 1B Bit ISR DECI is set SDTFI 18 w Set DTFI Flag 0B No operation 1B Bit ISR DTFI is set SURDI 19 w Set URDI Flag 0B No operation 1B Bit ISR URDI is set SDP 20 w Set DP Bit 0B No effect 1B Bit DSC DP is set SCP 21 w Set CP Flag 0B No operation 1B Bit DSC CP is set SDDIS 22 w Set DSDIS Flag 0B No operation 1B Bit DSC DSDIS is set 0 15 ...

Page 1238: ...rted FCL signal polarity 1B FCLP signal has inverted FCL signal polarity FCLN and FCL signal polarities are identical SLP 1 rw SOP Line Polarity 0B SOP and SO signal polarity is identical SON signal has inverted SO signal polarity 1B SOP signal has inverted SO signal polarity SON and SO signal polarities are identical CSLP 2 rw Chip Selection Lines Polarity 0B EN 3 0 and ENL ENH ENC signal polarit...

Page 1239: ...ine is selected for ENL 10B EN2 line is selected for ENL 11B EN3 line is selected for ENL CSH 12 11 rw Chip Enable Selection for ENH This bit field selects the chip enable output ENx that becomes active during the SRH active phase ENH 1 of a data frame The active level of ENx is defined by bit CSLP 00B EN0 line is selected for ENH 01B EN1 line is selected for ENH 10B EN2 line is selected for ENH 1...

Page 1240: ...pstream channel 000B SDI0 input is selected for SDI 001B SDI1 input is selected for SDI 010B SDI2 input is selected for SDI 011B SDI3 input is selected for SDI 100B SDI4 input is selected for SDI 101B SDI5 input is selected for SDI 110B SDI6 input is selected for SDI 111B SDI7 input is selected for SDI 0 7 4 15 31 19 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1241: ...hift Register Contains the data bits to be transmitted during the SRL active phase of a data frame DDH 31 16 rw Downstream Data for SRH Shift Register Contains the data bits to be transmitted during the SRH active phase of a data frame DC Downstream Command Register 20H Reset Value 0000 0000H 31 16 15 0 DCH DCL rw rw Field Bits Type Description DCL 15 0 rw Downstream Command for SRL Shift Register...

Page 1242: ...he 8 bit receive data V 16 rh Valid Bit This bit is set by hardware when the received data is written to UDx Writing bit C 1 clears V If hardware setting and software clearing of the valid bit occur simultaneously bit V will be cleared P 17 rh Parity Bit This flag contains the parity bit that has been received with the data frame C 18 w Clear Bit 0B No operation 1B Bit V is cleared C is always rea...

Page 1243: ...5 MSC V1 40 PERR 22 rh Parity Error This bit indicates if a start bit error parity error or stop bit error occurred during frame reception 0B No error detected 1B Error detected 0 15 8 31 23 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1244: ...g and interrupt control logic Two of the four modules service request outputs are connected with interrupt nodes and two with the DMA controller Outputs of the GPTA module are connected to the alternate input buses ALTINL ALTINH The emergency stop output from the SCU controls the corresponding inputs of MSC0 module The serial data and clock outputs of the downstream channels of the MSC0 module are...

Page 1245: ... 11 FCLP0B P2 12 SOP0B Upstream Channel Downstream Channel Clock Control Address Decoder Interrupt Control SR 1 0 EMGSTOPMSC ALTINL 15 0 ALTINH 15 0 To DMA SR 3 2 from GPTA from SCU fMSC0 fCLC0 SR15 from CAN SDI0 1 These inputs are connected to high level 2 These outputs are not connected 16 16 F A2 A2 A2 A2 A1 Port 6 Control F F F F A1 or LVDS Port 2 Control SDI1 EN2 2 EN32 SDI 7 3 1 SDI2 Port 0 ...

Page 1246: ...ch are required for MSC programming see also Figure 18 28 for the module kernel specific registers These registers are described in the following sections Figure 18 30 MSC Implementation specific Special Function Registers MCA06256_mod MSC0_SRCx Interrupt Registers P6_IOCR4 Port Registers Clock Control Registers MSC0_CLC x 0 1 MSC0_FDR P6_IOCR8 P6_PDR P6_IOCR0 P2_IOCR8 P2_IOCR12 P2_PDR ...

Page 1247: ...ertain conditions fMSC0 This clock is the module clock that is used inside the MSC for baud rate generation of the serial upstream and downstream channel The fractional divider register MSC0_FDR controls the frequency of fMSC0 and makes it possible to enable disable it independent of fCLC0 Figure 18 31 MSC0 Module Clock Generation The following two formulas define the frequency of fMSC0 18 3 18 4 ...

Page 1248: ...rom the module clock fMSC0 by a programmable clock divider selected by bit field MSC0_USR URR see also Equation 18 2 on Page 18 25 The divide factor DF can be at minimum 4 and at maximum 256 18 7 18 8 Equation 18 3 Equation 18 5 and Equation 18 7 are valid for normal divider mode MSC0 FDR DM 01B Equation 18 4 Equation 18 6 and Equation 18 8 are valid for fractional divider mode MSC0 FDR DM 10B Bau...

Page 1249: ...00 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to ena...

Page 1250: ... 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in suspend mode DM 15 14 rw Divider Mode DM selects normal or fractional divider mode RESULT 25 16 rh Result Value Bit field for the addition result SUSACK 28 rh Suspend Mode Ac...

Page 1251: ...racteristics such as port direction input output with alternate output selection pull up down devices and open drain selections The I O lines for the MSC0 module are controlled by the Port 6 input output control registers Table 18 10 shows in an overview how bits and bit fields must be programmed for the required I O functionality of the MSC0 I O lines 0 10 27 26 r Reserved Read as 0 should be wri...

Page 1252: ...P0B P2_IOCR8 PC11 1X11B Output P2 12 SOP0B P2_IOCR12 PC12 1X11B Output P2 13 SDI0 P2_IOCR12 PC13 0XXXB and MSC0_OCR SDISEL 000B Input P0 1 SDI1 P0_IOCR0 PC1 0XXXB and MSC0_OCR SDISEL 001B Input P3 14 SDI2 P3_IOCR12 PC14 0XXXB and MSC0_OCR SDISEL 010B Input P0 14 FCLP0C P2_IOCR8 PC11 1X10B Output P0 15 SOP0C P2_IOCR12 PC12 1X10B Output 1 Default after reset Table 18 10 MSC0 I O Line Selection and S...

Page 1253: ... emergency stop register 18 3 5 2 DMA Controller Service Requests Two service request outputs SR 3 2 of the MSC0 module are connected as DMA request input to the DMA controller The DMA request lines are connected to the DMA controller as shown in Table 18 11 Table 18 11 Service Request Lines of MSC0 Module Service Request Line Connected to Description MSC0 SR0 MSC0_SRC0 MSC0 Service Request Node 0...

Page 1254: ...A requests see Table 18 11 MSC0_SRCx x 0 1 MSC0 Service Request Control Register x FCH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR...

Page 1255: ...0 080CH U SV SV E 0000 0000H MSC0_ USR MSC0 Upstream Status Register F000 0810H U SV U SV 0000 0000H MSC0_ DSC MSC0 Downstream Control Register F000 0814H U SV U SV 0000 0000H MSC0_ DSS MSC0 Downstream Status Register F000 0818H U SV U SV 0000 0000H MSC0_ DD MSC0 Downstream Data Register F000 081CH U SV U SV 0000 0000H MSC0_ DC MSC0 Downstream Command Register F000 0820H U SV U SV 0000 0000H MSC0_...

Page 1256: ... Register F000 0844H U SV U SV 0000 0000H MSC0_ ISC MSC0 Interrupt Set Clear Register F000 0848H U SV U SV 0000 0000H MSC0_ OCR MSC0 Output Control Register F000 084CH U SV U SV 0000 0000H Reserved F000 0850H F000 0854H nBE nBE F000 0858H F000 08F4H BE BE MSC0_ SRC1 MSC0 Service Request Control Register 1 F000 08F8H U SV U SV 0000 0000H MSC0_ SRC0 MSC0 Service Request Control Register 0 F000 08FCH...

Page 1257: ... interrupt control address decoding clock control see Page 19 109 Note The MultiCAN register names described in this chapter are referenced in the TC1784 User s Manual by the module name prefix CAN_ Table 19 1 Fixed Module Constants Constant Description n_objects Number of Message Objects available n_interrupts Number of Interrupt Output Lines available n_pendings n_pendingregs Number of Message P...

Page 1258: ...ier indicates the contents of the message and its priority The lower the binary value of the identifier the higher is the priority of the message For bus arbitration CSMA CD with NDA Carrier Sense Multiple Access Collision Detection with Non Destructive Arbitration is used If bus node A attempts to transmit a message across the network it first checks that the bus is in the idle state Carrier Sens...

Page 1259: ...evel for hard synchronization of all nodes The SOF is followed by the Arbitration Field consisting of 12 bits the 11 bit identifier reflecting the contents and priority of the message and the RTR Remote Transmission Request bit With RTR at dominant level the frame is marked as Data Frame With RTR at recessive level the frame is defined as a Remote Frame The next field is the Control Field consisti...

Page 1260: ...e level Figure 19 1 CAN Data Frame Extended Data Frame In the Extended CAN Data Frame the message identifier of the standard frame has been extended to 29 bit A split of the extended identifier into two parts an 11 bit least Bus Idle Dominant Level Recessive Level Bus Idle Bus Idle Dominant Level Recessive Level MCT06258 11 Standard Data Frame ACK Delimiter ACK Slot CRC Delimiter CRC Sequence Data...

Page 1261: ...t by a node that is sending a Standard CAN Remote Frame The SRR and IDE bits are followed by the remaining 18 bits of the extended identifier and the RTR bit Control field and frame termination is identical to the Standard Data Frame 19 1 2 2 Remote Frames Normally data transmission is performed on an autonomous basis with the data source node e g a sensor sending out a Data Frame It is also possi...

Page 1262: ...MCT06259 11 Standard Remote Frame ACK Delimiter ACK Slot CRC Delimiter CRC Sequence Data Length Code Reserved D IDE Bit D RTR Bit D Identifier 4 1 1 1 1 1 1 15 Start of Frame Control Field Arbitration Field 12 bit 1 7 3 Inter Frame Space End of Frame EOF Acknowledge Field CRC Field 11 4 1 1 1 1 1 15 1 7 3 18 2 1 Extended Remote Frame SRR Bit R IDE Bit R 29 bit Identfier Arbitration Field 32 bit RT...

Page 1263: ...s the Error Frame After completion of the Error Frame bus activity returns to normal and the interrupted node attempts to re send the aborted message If an error passive node detects a bus error the node transmits an error passive flag followed again by the Error Delimiter field The error passive flag consists of six consecutive recessive bits and therefore the Error Frame for an error passive nod...

Page 1264: ...s are caused by signal propagation delay on the bus line and through the electronic interface circuits of the bus nodes The Phase Segments 1 and 2 PHASE_SEG1 PHASE_SEG2 are used to compensate for edge phase errors These segments can be lengthened or shortened by re synchronization PHASE_SEG2 is reserved for calculation of the subsequent bit level and is 2 tQ At the sample point the bus level is re...

Page 1265: ...d and an Error Frame is generated The message is repeated Bit Error A Bit Error occurs if a a transmitter sends a dominant bit and detects a recessive bit or b if the transmitter sends a recessive bit and detects a dominant bit when monitoring the actual bus level and comparing it to the just transmitted bit In case b no error occurs during the Arbitration Field ID RTR IDE and the Acknowledge Slot...

Page 1266: ...sing Basic CAN modules The main advantage of Basic CAN is a reduced chip size leading to low costs of these devices Full CAN devices this is the case for the MultiCAN controller as implemented in TC1784 manage the whole bus protocol in hardware including the acceptance filtering and message management Full CAN devices contain message objects that handle autonomously the identifier the data the dir...

Page 1267: ...can contain between two and eight independent CAN nodes depending on the device each representing one serial communication interface Figure 19 5 Overview of the MultiCAN Module MultiCAN Module Kernel MultiCAN_overview_x_n_noTT vsd Clock Control Address Decoder Interrupt Control fCAN Port Control CAN Node 1 CAN Control Message Object Buffer n Objects TXDC0 RXDC0 CAN Node 0 CAN Node x 1 TXDC1 RXDC1 ...

Page 1268: ...message object list A powerful command driven list controller performs all message object list operations The bit timings for the CAN nodes are derived from the module timer clock fCAN and are programmable up to a data rate of 1 Mbit s External bus transceivers are connected to a CAN node via a pair of receive and transmit pins Features Compliant with ISO 11898 CAN functionality according to CAN s...

Page 1269: ...ry number of gateways can be defined Advanced data management The message objects are organized in double chained lists List reorganizations can be performed at any time even during full operation of the CAN nodes A powerful command driven list controller manages the organization of the list structure and ensures consistency of the list Message FIFOs are based on the list structure and can easily ...

Page 1270: ...o the ISO 11898 standard This includes conversion between the serial data stream and the input output registers Bit Timing Unit The Bit Timing Unit determines the length of a bit time and the location of the sample point according to the user settings taking into account propagation delays and phase shift errors The Bit Timing Unit also performs resynchronization MultiCAN_Blockdiag_x vsd CAN Bus 0...

Page 1271: ...eived CAN frame Transmit acceptance filtering to determine the message object to be transmitted first individually for each CAN node Transfer contents between message objects and the CAN nodes taking into account the status control bits of the message objects Handling of the FIFO buffering and gateway functionality Aggregation of message pending notification bits List Controller The List Controlle...

Page 1272: ...urce is connected to the same interrupt node pointer in the interrupt node pointer register the requests are combined to one common line Figure 19 7 General Interrupt Structure MCA06264 Interrupt Flag Writing 0 Interrupt Enable Interrupt Event Set Reset Other Interrupt Sources on the same INP INP 1 To INT_O0 To INT_O1 To INT_O15 ...

Page 1273: ...clock fCLC but only every n th clock pulse is taken The suspend signal coming as acknowledge from the MultiCAN module in response to a OCDS suspend request freezes or resets the Fractional Divider Figure 19 8 MultiCAN Clock Generation Table 19 2 indicates the minimum operating frequencies in MHz for fCLC that are required for a baud rate of 1 Mbit s for the active CAN nodes If a lower baud rate is...

Page 1274: ...e of the module and to permit access to the registers at least for read actions The MultiCAN module provides two types of Suspend Modes All actions are immediately stopped Hard Suspend Mode The module clocks fCLC and fCAN are switched off as soon as the suspend request becomes active Read and write operations to the module are no longer possible This means that the CAN registers cannot be accessed...

Page 1275: ... the internal actions is indicated to the fractional divider by a suspend mode acknowledged signal Due to this behavior the communication network is not blocked Furthermore all registers are accessible for read and write actions As a result the debugger can stop the module actions and modify registers These modifications are taken into account after the Suspend Mode is left The Hard Suspend Mode c...

Page 1276: ...d If CAN Analyze Mode is enabled Remote Frames are not responded to by the corresponding Data Frame and Data Frames cannot be transmitted by setting the transmit request bit MOSTATn TXRQ Receive interrupts are generated in CAN Analyze Mode if enabled for all error free received frames The node specific interrupt configuration is also defined by the Node Control Logic via the NCRx register bits TRI...

Page 1277: ...tput driver on the CAN bus line and in the transceiver circuit For a working collision detection mechanism TProp must be two times the sum of all propagation delay quantities rounded up to a multiple of tq The phase buffer segments 1 and 2 Tb1 Tb2 before and after the signal sample point are used to compensate for a mismatch between transmitter and receiver clock phases detected in the synchroniza...

Page 1278: ...valid CAN bit timing must be written to the CAN Node Bit Timing Register NBTR before resetting the INIT bit in the Node Control Register i e before enabling the operation of the CAN node The Node Bit Timing Register may be written only if bit CCE Configuration Change Enable is set in the corresponding Node Control Register 19 3 5 2 Bitstream Processor Based on the message objects in the message bu...

Page 1279: ...C and the Transmit Error Counter TEC bit fields of the Node x Error Counter Register NECNTx see Page 19 83 are incremented and decremented by commands from the Bitstream Processor If the Bitstream Processor itself detects an error while a transmit operation is running the Transmit Error Counter is incremented by 8 An increment of 1 is used when the error condition was reported by an external CAN n...

Page 1280: ...f the NFCRx register After the successful transfer of the frame the captured value is copied to the CFCVAL bit field of the MOIPRn register of the message object involved in the transfer Bit Timing Mode Used for baud rate detection and analysis of the bit timing Chapter 19 3 7 3 19 3 5 5 CAN Node Interrupts Each CAN node has four hardware triggered interrupt request types that are able to generate...

Page 1281: ...rupts MCA06267 TRIE TRINP TXOK RXOK Receive Transmit Correct Message Object Transfer LECIE LECINP LEC CAN Error EWRN BOFF ALINP ALIE ALERT LLE LOE List Length Error List Object Error CFCIE CFCINP CFCOV Frame Counter Overflow Event NSRx NSRx NCRx NIPRx NIPRx NIPRx NIPRx NSRx NSRx NCRx NCRx NSRx NSRx NSRx NFCRx NFCRx 1 1 3 ...

Page 1282: ... first element in the list object 5 in the example and bit field END points to the last element in the list object 3 in the example The number of elements in the list is indicated by bit field SIZE of the List Register SIZE number of list elements 1 thus SIZE 2 for the 3 elements in the example The EMPTY bit of the List Register indicates whether or not a list is empty EMPTY 0 in the example becau...

Page 1283: ...e message objects caused by reset the list of all unallocated message objects is ordered by message number predecessor of message object n is object n 1 successor of object n is object n 1 19 3 6 3 Connection to the CAN Nodes Each CAN node is linked to one unique list of message objects A CAN node performs message transfer only with the message objects that are allocated to the list of the CAN nod...

Page 1284: ...s that modify the list structure result in a consistent list structure 2 Present maximum ease of use and flexibility to the user The list controller and the associated command panel allows the programmer to concentrate on the final properties of the list which are characterized by the allocation of message objects to a CAN node and the ordering relation between objects that are allocated to the sa...

Page 1285: ...matically initialized after reset by the list controller in order to ensure correct list pointers in each message object The end of this CAN RAM initialization is indicated by bit PANCTR BUSY becoming inactive In case of a dynamic allocation command that takes an element from the list of unallocated objects the PANCTR RBUSY bit is also set along with the BUSY bit Table 19 3 Panel Commands Overview...

Page 1286: ...e located inside the RAM delays the ongoing allocation process by one access cycle As soon as the command is finished the BUSY flag becomes inactive BUSY 0 and write accesses to the Panel Control Register are enabled again Also the No Operation command code is automatically written to the PANCTR PANCMD field A new command may be started any time when BUSY 0 All fields of the Panel Control Register...

Page 1287: ...message object functionality is available but no transmit request will be executed 19 3 7 2 Loop Back Mode The MultiCAN module provides a Loop Back Mode to enable an in system test of the MultiCAN module as well as the development of CAN driver software without access to an external CAN bus The loop back feature consists of an internal CAN bus inside the MultiCAN module and a bus select switch for...

Page 1288: ...he CAN baud rate as well as to analyze the timing of the CAN network Bit timing analysis for CAN node x is selected when bit field NFCRx CFMOD 10B Bit timing analysis does not affect the operation of the CAN node The bit timing measurement results are written into the NFCRx CFC bit field Whenever NFCRx CFC is updated in bit timing analysis mode bit NFCRx CFCOV is also set to indicate the CFC updat...

Page 1289: ...Rx CFSEL 010B The time between the first dominant edge and the sample point is measured and stored in the NFCRx CFC bit field The bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points Synchronization analysis can be used for example for fine tuning of ...

Page 1290: ...the IDE bit of the received frame is don t care In this case message objects with standard and extended frames are accepted The identifier of the received frame matches the identifier stored in the Arbitration Register of the message object as qualified by the acceptance mask in the MOAMRn register This means that each bit of the received message object identifier is equal to the bit field MOARn I...

Page 1291: ...nes which one of all qualifying message objects is transmitted first It is assumed that message object a MOa and message object b MOb are two message objects qualified for transmission MOb is a list successor of MOa For both message objects CAN messages CANa and CANb are defined identifier IDE and RTR are taken from the message specific bit fields and bits MOARn ID MOARn IDE and MOCTRn DIR If both...

Page 1292: ...ity wins the transmit acceptance filtering and will be transmitted first All other message objects lose the current transmit acceptance filtering round They get a new chance in subsequent acceptance filtering rounds Figure 19 15 Effective Transmit Request of Message Object MCA06272 MSGVAL 0 Object will not be transmitted 1 Object is requested for transmission TXRQ TXEN0 TXEN1 ...

Page 1293: ...s see Figure 19 16 A receive interrupt occurs also after a frame storage event that has been induced by a FIFO or a gateway action The status bits TXPND and RXPND in the Message Object n Status Register are always set after a successful transmission reception whether or not the respective message interrupt is enabled A third FIFO full interrupt condition of a message object is provided If bit fiel...

Page 1294: ... Message Interrupt Request Routing MCA06273 TXIE TXINP TXPND RXINP MOSTATn MOFCRn MOIPRn MOIPRn OVIE RXIE RXPND MMC 0001B 0010B MMC 0001B Message object n is a Receive FIFO Base Object MMC 0010B Message object n is a Transmit FIFO Base Object 1 1 Message n received Message n transmitted Message n FIFO full ...

Page 1295: ...bits in case that the maximum possible number of eight Message Pending Registers are implemented and available on the chip Figure 19 17 Message Pending Bit Allocation 255 224 MCA06274 7 6 5 4 3 2 1 0 MPN Message Object n Interrupt Pointer Register MOIPRn 15 0 3 2 1 0 TXINP 3 2 1 0 RXINP 15 D E M U X 0 7 D E M U X 0 31 31 0 3 2 1 0 MPSEL Modul Control Register MCR 31 0 MSB Message Pending Registers...

Page 1296: ... MPSEL 1111B the location selection operates in the following way At a transmit event the upper 3 bits of TXINP determine the number k of a Message Pending Register MSPNDk in which the pending bit will be set At a receive event the upper 3 bits of RXINP determine the number k The bit position 0 31 in MSPNDk for the pending bit to be set is selected by the lowest bit of TXINP or RXINP selects betwe...

Page 1297: ...ject and sets MSGVAL again the following scenario can occur 1 The message object wins receive acceptance filtering 2 The CPU clears MSGVAL to re configure the message object 3 The CPU sets MSGVAL again after re configuration 4 The end of the received frame is reached As MSGVAL is set the received data is stored in the message object a message interrupt request is generated gateway and FIFO actions...

Page 1298: ...ges the message object no longer wins receive acceptance filtering RXUPD NEWDAT and MSGLST An ongoing frame storage process is indicated by the RXUPD Receive Updating flag in the MOSTATn register RXUPD is set with the start and cleared with the end of a message object update which consists of frame storage as well as flag updates After storing the received frame identifier IDE bit DLC including th...

Page 1299: ...ing yes yes no no CAN rec successful MSGVAL RTSEL 1 MSGVAL 1 DIR 1 NEWDAT 1 RXIE 1 RTSEL 1 RXUPD 1 Copy frame to message object TXRQ 1 in this or in foreign objects Copy frame to message object RXUPD 1 MSGLST 1 yes NEWDAT 1 RXUPD 0 RXPND 1 no no yes yes no MSGLST 1 no yes 1 2 3 4 no Time Milestones Get data from gateway FIFO source Start receiving CAN frame Done yes ...

Page 1300: ...emantics Table 19 4 Message Transmission Bit Definitions Bit Description MSGVAL Message Valid This is the main switch bit of the message object TXRQ Transmit Request This is the standard transmit request bit This bit must be set whenever a message object should be transmitted TXRQ is cleared by hardware at the end of a successful transmission except when there is new data indicated by NEWDAT 1 to ...

Page 1301: ...XRQ time stamp update message interrupt etc within the old context of the object can occur after the message object becomes valid again but within a new context NEWDAT When the contents of a message object have been transferred to the internal transmit buffer of the CAN node bit MOSTATn NEWDAT New Data is cleared by hardware to indicate that the transmit message object data is no longer new When t...

Page 1302: ...76 RTSEL 1 NEWDAT 1 TXIE 1 RTSEL 1 NEWDAT 0 no yes 1 2 3 Copy Message to internal transmit buffer MSGVAL TXRQ TXEN0 TXEN1 1 continuously valid Request transmission of internal buffer on CAN bus yes Transmission successful yes MSGVAL RTSEL 1 yes TXRQ 0 Issue interrupt no no no no no Time Milestones Done Object wins transmit acc filtering yes yes ...

Page 1303: ...e contents of the new received message indicated by MSGLST 1 If SDT is set Single Data Transfer Mode activated bit MSGVAL of the message object is automatically cleared by hardware after the storage of a received Data Frame This prevents the reception of further messages After the reception of a Remote Frame bit MSGVAL is not automatically cleared Message Transmission When a message object receive...

Page 1304: ...ed to be allocated to the same list as the slave objects Only the slave object must be allocated to a common list as they are chained together Several pointers BOT CUR and TOP that are located in the Message Object n FIFO Gateway Pointer Register MOFGPRn link the base object to the slave objects regardless whether the base object is allocated to the same or to another list than the slave objects T...

Page 1305: ...ible to detect the end of a predefined message transfer series or to issue a warning interrupt when the FIFO becomes full Figure 19 20 FIFO Structure with FIFO Base Object and n FIFO Slave Objects MCA06277 Slave Object fi PPREV f i 1 PNEXT f i 1 Slave Object fn PPREV f n 1 PNEXT Slave Object f2 PPREV f1 PNEXT f3 Slave Object f1 PPREV PNEXT f2 Base Object PPREV PNEXT TOP fn CUR fi BOT f1 ...

Page 1306: ...ored For the slave object no acceptance filtering takes place that checks the received frame for a match with the identifier IDE bit and DIR bit With the reception of a CAN frame the current pointer CUR of the base object is set to the number of the next message object in the FIFO structure This message object will then be used to store the next incoming message If bit field MOFCRn OVIE Overflow I...

Page 1307: ...t be tagged valid MSGVAL 1 first Before a Transmit FIFO becomes de installed during operation its slave objects must be tagged invalid MSGVAL 0 The Transmit FIFO uses the TXEN1 bit in the Message Object Control Register of all FIFO elements to select the actual message for transmission Transmit acceptance filtering evaluates TXEN1 for each message object and a message object can win transmit accep...

Page 1308: ...s DLC is copied from the gateway source object to the gateway destination object 2 If bit MOFCRs IDC is set the identifier MOARs ID and the identifier extension MOARs IDE are copied from the gateway source object to the gateway destination object 3 If bit MOFCRs DATC is set the data bytes stored in the two data registers MODATALs and MODATAHs are copied from the gateway source object to the gatewa...

Page 1309: ...e reception of Remote Frames source object is transmit object Figure 19 21 Gateway Transfer from Source to Destination MCA06278 Copy if IDCSource 1 Pointer to Destination Message Object Destination CAN Bus Source CAN Bus Set CUR Identifier IDE DLC Data Source Message Object MMC 0100B Copy if DLCCSource 1 Copy if DATCSource 1 Set if GDFSSource 1 Identifier IDE DLC Data TXRQ NEWDAT TXRQ Destination ...

Page 1310: ...on object there are two capabilities to handle remote requests that appear on the destination side assuming that the source object is a receive object and the destination is a transmit object i e DIRsource 0 and DIRdestination 1 FRREN 0 in the Gateway Destination Object 1 A Remote Frame is received by gateway destination object 2 TXRQ is set automatically in the gateway destination object 3 A Data...

Page 1311: ...Registers Node Registers for each CAN node x Message Object Registers for each message object n Figure 19 22 MultiCAN Kernel Registers The registers of the MLI module kernel are listed below Table 19 5 Registers Address Space MLI Kernel Registers Module Base Address End Address Note CAN F000 4000H F000 7FFFH LISTi MSPNDk MSIDk MCA06279_x vsd NCRx Global Module Registers CAN Node Registers NSRx MSI...

Page 1312: ...e 19 74 NIPRx Node x Interrupt Pointer Reg 0208H x 100H Page 19 78 NPCRx Node x Port Control Register 020CH x 100H Page 19 80 NBTRx Node x Bit Timing Register 0210H x 100H Page 19 81 NECNTx Node x Error Counter Register 0214H x 100H Page 19 83 NFCRx Node x Frame Counter Register 0218H x 100H Page 19 84 MOFCRn Message Object n Function Control Register 1000H n 20H Page 19 98 MOFGPRn Message Object ...

Page 1313: ... Control Register Node x Status Register NO Node x 0 to Number of Nodes 1 Node x Interrupt Ptr Reg Node x Port Control Reg Node x Bit Timing Reg Node x Error Counter Reg Node x Frame Counter Reg 300H Node 1 Registers NOBASE 00H Message Object Registers MO n Function Control Reg MO n FIFO Gtw Ptr Reg MO Message Object n 0 to Number of Message Objects 1 MO n Interrupt Ptr Reg MO n Accept Mask Reg MO...

Page 1314: ...nd the LIST registers Module Identification Register ID Module Identification Register 008H Reset Value 002B C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MODE_REV r rwh Field Bits Type Description MOD_REV 7 0 r Module Revision Number MOD_REV defines the revision number The value of a module revision starts with 01H first revision...

Page 1315: ...sed to start a new command by writing a panel command code into it At the end of a panel command the NOP no operation command code is automatically written into PANCMD The coding of PANCMD is defined in Table 19 7 BUSY 8 rh Panel Busy Flag 0B Panel has finished command and is ready to accept a new command 1B Panel operation is in progress RBUSY 9 rh Result Busy Flag 0B No update of PANAR1 and PANA...

Page 1316: ...IST 7 0 are set to their reset values This results in the de allocation of all message objects The initialization command requires that bits NCRx INIT and NCRx CCE are set for all CAN nodes Bit 7 of PANAR2 ERR reports the success of the operation 0B Initialization was successful 1B Not all NCRx INIT and NCRx CCE bits are set Therefore no initialization is performed The initialize lists command is ...

Page 1317: ...rt Before Remove a message object source object from the list that it currently belongs to and insert it before a given destination object into the list structure of the destination object The source object thus becomes the predecessor of the destination object 05H Argument Destination Object Number Result Bit 7 ERR Bit 6 0 undefined Result Object Number of inserted object Dynamic Insert Before In...

Page 1318: ...nation object 07H Argument Destination Object Number Result Bit 7 ERR Bit 6 0 undefined Result Object Number of inserted object Dynamic Insert Behind Insert a new message object behind a given destination object The new object is taken from the list of unallocated elements the first element is chosen The number of the new object is delivered as result to PANAR1 An ERR bit bit 7 of PANAR2 reports t...

Page 1319: ... 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPSEL 0 rw r Field Bits Type Description MPSEL 15 12 rw Message Pending Selector Bit field MPSEL makes it possible to select the bit position of the message pending bit after a message reception transmission by a mixture of the MOIPRn register bit fields RXINP TXINP and MPN Selection details are given in Figure 19 17 on...

Page 1320: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IT w Field Bits Type Description IT 15 0 w Interrupt Trigger Writing a 1 to IT n n 0 15 generates an interrupt request on interrupt output line INT_O n Writing a 0 to IT n has no effect Bit field IT is always read as 0 Multiple interrupt requests can be generated with a single write operation to MITR by writing a 1 ...

Page 1321: ...es the list for CAN node 1 LIST3 provides the list for CAN node 2 LIST 7 4 are not associated to a CAN node free lists LIST0 List Register 0 100H Reset Value 007F 7F00H LISTx x 1 7 List Register x 100H x 4H Reset Value 0100 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 EMP TY SIZE r rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 END BEGIN rh rh Field Bits Type Description BEGIN 7 0 rh List ...

Page 1322: ... User s Manual 19 66 V1 1 2011 05 MLI V2 0 EMPTY 24 rh List Empty Indication 0B At least one message object is allocated to list i 1B No message object is allocated to the list x List x is empty 0 31 25 r Reserved Read as 0 Field Bits Type Description ...

Page 1323: ...nted in the MultiCAN module to select the highest priority object within a collection of message objects The Message Pending Register MSPNDk contains the pending interrupt notification of list i MSPNDk k 0 7 Message Pending Register k 140H k 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PND rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PND rwh Field Bits Type Description PN...

Page 1324: ...1 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 INDEX r rh Field Bits Type Description INDEX 5 0 rh Message Pending Index The value of INDEX is given by the bit position i of the pending bit of MSPNDk with the following properties 1 MSPNDk i IM i 1 2 i 0 or MSPNDk i 1 0 IM i 1 0 0 If no bit of MSPNDk satisfies these conditions then INDEX reads 100000B Thus INDEX shows the position of ...

Page 1325: ... used commonly for all Message Pending registers and their associated Message Index registers MSIMASK Message Index Mask Register 1C0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IM rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM rw Field Bits Type Description IM 31 0 rw Message Index Mask Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribu...

Page 1326: ...hat is directly related to the operation of the CAN nodes and are shared among the nodes The Node Control Register contains basic settings that determine the operation of the CAN node NCRx x 0 2 Node x Control Register 200H x 100H Reset Value 0000 0001H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SUS EN CAL M CCE 0 CAN DIS ALIE LECI E TRIE INIT r rw ...

Page 1327: ...AN traffic Any ongoing frame transfer is cancelled and the transmit line goes recessive If the CAN node is in the bus off state then the running bus off recovery sequence is continued If the INIT bit is still set after the successful completion of the bus off recovery sequence i e after detecting 128 sequences of 11 consecutive recessive bits 11 1 then the CAN node leaves the bus off state but rem...

Page 1328: ... 1B Alert interrupt is enabled Bit field NIPRx ALINP selects the interrupt output line which becomes activated at this type of interrupt CANDIS 4 rw CAN Disable Setting this bit disables the CAN node The CAN node first waits until it is bus idle or bus off Then bit INIT is automatically set and an alert interrupt is generated if bit ALIE is set CCE 6 rw Configuration Change Enable 0B The Bit Timin...

Page 1329: ... chip debug support 0B An OCDS suspend trigger is ignored by the CAN node 1B An OCDS suspend trigger disables the CAN node As soon as the CAN node becomes bus idle or bus off bit INIT is internally forced to 1 to disable the CAN node The actual value of bit INIT remains unchanged Bit SUSEN is reset via OCDS Reset 0 31 9 5 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1330: ...e Description LEC 2 0 rwh Last Error Code This bit field indicates the type of the last most recent CAN error The encoding of this bit field is described in Table 19 8 TXOK 3 rwh Message Transmitted Successfully 0B No successful transmission since last most recent flag reset 1B A message has been transmitted successfully error free and acknowledged by at least another node TXOK must be reset by so...

Page 1331: ...it EWRNLVL BOFF 7 rh Bus off Status 0B CAN controller is not in the bus off state 1B CAN controller is in the bus off state LLE 8 rwh List Length Error 0B No List Length Error since last most recent flag reset 1B A List Length Error has been detected during message acceptance filtering The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list ter...

Page 1332: ...have occurred in a part of a received message where this is not allowed 010B Form Error A fixed format part of a received frame has the wrong format 011B Ack Error The transmitted message was not acknowledged by another node 100B Bit1 Error During a message transmission the CAN node tried to send a recessive level 1 outside the arbitration field and the acknowledge slot but the monitored bus value...

Page 1333: ...Error The CRC checksum of the received message was incorrect 111B CPU write to LEC Whenever the the CPU writes the value 111 to LEC it takes the value 111 Whenever the CPU writes another value to LEC the written LEC value is ignored Table 19 8 Encoding of the LEC Bit Field cont d LEC Value Signification ...

Page 1334: ...NP ALINP rw rw rw rw Field Bits Type Description ALINP 3 0 rw Alert Interrupt Node Pointer ALINP selects the interrupt output line INT_Om m 0 15 for an alert interrupt of CAN Node x 0000B Interrupt output line INT_O0 is selected 0001B Interrupt output line INT_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected LECINP 7 4 rw Last Error C...

Page 1335: ... 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected CFCINP 15 12 rw Frame Counter Interrupt Node Pointer CFCINP selects the interrupt output line INT_Om m 0 15 for a frame counter overflow interrupt of CAN Node x 0000B Interrupt output line INT_O0 is selected 0001B 000Interrupt output line INT_O1 is selected B 1110B Interrupt output line INT_O14 is sele...

Page 1336: ...rw Receive Select RXSEL selects one out of 8 possible receive inputs The CAN receive signal is performed only through the selected input Note In TC1784 only specific combinations of RXSEL are available see also Receive Input Selection on Page 19 115 LBM 8 rw Loop Back Mode 0B Loop Back Mode is disabled 1B Loop Back Mode is enabled This node is connected to an internal virtual loop back CAN bus All...

Page 1337: ...V8 0 The duration of one time quantum is given by 8 BRP 1 clock cycles if DIV8 1 SJW 7 6 rw Re Synchronization Jump Width SJW 1 time quanta are allowed for re synchronization TSEG1 11 8 rw Time Segment Before Sample Point TSEG1 1 time quanta is the user defined nominal time between the end of the synchronization segment and the sample point It includes the propagation segment which takes into acco...

Page 1338: ... User s Manual 19 82 V1 1 2011 05 MLI V2 0 DIV8 15 rw Divide Prescaler Clock by 8 0B A time quantum lasts BRP 1 clock cycles 1B A time quantum lasts 8 BRP 1 clock cycles 0 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1339: ...ve Error Counter Bit field REC contains the value of the receive error counter of CAN node x TEC 15 8 rwh Transmit Error Counter Bit field TEC contains the value of the transmit error counter of CAN node x EWRNLVL 23 16 rw Error Warning Level Bit field EWRNLVL determines the threshold value warning level default 96 to be reached in order to set the corresponding error warning bit EWRN LETD 24 rh L...

Page 1340: ...r rwh rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFC rwh Field Bits Type Description CFC 15 0 rwh CAN Frame Counter In Frame Count Mode CFMOD 00B this bit field contains the frame count value In Time Stamp Mode CFMOD 01B this bit field contains the captured bit time count value captured with the start of a new frame In all Bit Timing Analysis Modes CFMOD 10B CFC always displays the number of...

Page 1341: ...been transmitted successfully by the node Time Stamp Mode 000B The frame counter is incremented internally at the beginning of a new bit time The value is sampled during the SOF bit of a new frame The sampled value is visible in the CFC field Bit Timing Mode The available bit timing measurement modes are shown in Table 19 9 If CFCIE is set then an interrupt on request node x where x is the CAN nod...

Page 1342: ...24 r Reserved Read as 0 should be written with 0 Table 19 9 Bit Timing Analysis Modes CFMOD 10 CFSEL Measurement 000B Whenever a dominant edge transition from 1 to 0 is monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 001B Whenever a recessive edge transition from 0 to 1 is monitored on the receive input the time ...

Page 1343: ...6 EOF bits IFS 01B NewBit This code represents the first bit of a new frame segment The current bit is the first bit in one of the following frame segments Bit 10 MSB of standard ID transmit only RTR reserved bits IDE DLC MSB bit 7 MSB in each data byte and the first bit of the ID extension 10B Bit This code represents a bit inside a frame segment with a length of more than one bit not the first b...

Page 1344: ...7 26 25 24 23 22 21 20 19 18 17 16 0 SET DIR SET TXE N1 SET TXE N0 SET TXR Q SET RXE N SET RTS EL SET MSG VAL SET MSG LST SET NEW DAT SET RXU PD SET TXP ND SET RXP ND w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RES DIR RES TXE N1 RES TXE N0 RES TXR Q RES RXE N RES RTS EL RES MSG VAL RES MSG LST RES NEW DAT RES RXU PD RES TXP ND RES RXP ND w w w w w w w w w w w w w Field Bits ...

Page 1345: ...r RXEN see Table 19 11 RESTXRQ SETTXRQ 8 24 w Reset Set Transmit Request These bits control the set reset condition for TXRQ see Table 19 11 RESTXEN0 SETTXEN0 9 25 w Reset Set Transmit Enable 0 These bits control the set reset condition for TXEN0 see Table 19 11 RESTXEN1 SETTXEN1 10 26 w Reset Set Transmit Enable 1 These bits control the set reset condition for TXEN1 see Table 19 11 RESDIR SETDIR ...

Page 1346: ...2011 05 MLI V2 0 Write 1 Write 0 Reset element No write Write 0 Write 1 Set element No write 1 The parameter y stands for the second part of the bit name RXPND TXPND up to DIR Table 19 11 Reset Set Conditions for Bits in Register MOCTRn cont d RESy Bit1 SETy Bit Action on Write ...

Page 1347: ... 20H Rest Value n 1 01000000H n 1 00010000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PNEXT PPREV rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIST DIR TX EN1 TX EN0 TX RQ RX EN RTS EL MSG VAL MSG LST NEW DAT RX UPD TX PND RX PND rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description RXPND 0 rh Receive Pending 0B No CAN message has been received 1B A CAN message has been received ...

Page 1348: ...en stored in message object n NEWDAT is cleared by hardware when a CAN transmission of message object n has been started NEWDAT should be set by software after the new transmit data has been stored in message object n to prevent the automatic reset of TXRQ at the end of an ongoing transmission MSGLST 4 rh Message Lost 0B No CAN message is lost 1B A CAN message is lost because NEWDAT has become set...

Page 1349: ...sion RTSEL is set by hardware when message object n has been identified to be transmitted next A check is performed to determine if RTSEL is still set before message object n is actually set up for transmission and bit NEWDAT is cleared It is also checked that RTSEL is still set before its message object n is verified due to the successful transmission of a frame RTSEL needs to be checked only whe...

Page 1350: ...TXEN0 9 rh Transmit Enable 0 0B Message object n is not enabled for frame transmission 1B Message object n is enabled for frame transmission Message object n can be transmitted only if both bits TXEN0 and TXEN1 are set The user may clear TXEN0 in order to inhibit the transmission of a message that is currently updated or to disable automatic response of Remote Frames TXEN1 10 rh Transmit Enable 1 ...

Page 1351: ...ist Allocation LIST indicates the number of the message list to which message object n is allocated LIST is updated by hardware when the list allocation of the object is modified by a panel command PPREV 23 16 rh Pointer to Previous Message Object PPREV holds the message object number of the previous message object in a message list structure PNEXT 31 24 rh Pointer to Next Message Object PNEXT hol...

Page 1352: ...interrupt output line INT_Om m 0 15 for a receive interrupt event of message object n RXINP can also be taken for message pending bit selection see Page 19 39 0000B Interrupt output line INT_O0 is selected 0001B Interrupt output line INT_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected TXINP 7 4 rw Transmit Interrupt Node Pointer TXIN...

Page 1353: ...the bit position of the bit in the Message Pending Register that is set upon a message object n receive transmit interrupt CFCVAL 31 16 rwh CAN Frame Counter Value When a message is stored in message object n or message object n has been successfully transmitted the CAN frame counter value NFCRx CFC is then copied to CFCVAL Field Bits Type Description ...

Page 1354: ...rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DAT C DLC C IDC GDF S 0 MMC rw rw rw rw rw rw rw Field Bits Type Description MMC 3 0 rw Message Mode Control MMC controls the message mode of message object n 0000B Standard Message Object 0001B Receive FIFO Base Object 0010B Transmit FIFO Base Object 0011B Transmit FIFO Slave Object 0100B Gateway Source Object B Reserved GDFS 8 rw Gateway Dat...

Page 1355: ...ly to a gateway source object ignored in other nodes DATC 11 rw Data Copy 0B Data fields are not copied 1B Data fields in registers MODATALn and MODATAHn of the gateway source object after storing the received frame in the source are copied to the gateway destination Applicable only to a gateway source object ignored in other nodes RXIE 16 rw Receive Interrupt Enable RXIE enables the message recei...

Page 1356: ...L in the FIFO Gateway Pointer Register 0B FIFO full interrupt is disabled 1B FIFO full interrupt is enabled If message object n is a Receive FIFO base object bit field MOIPRn TXINP selects the interrupt output line which becomes activated at this type of interrupt If message object n is a Transmit FIFO base object bit field MOIPRn RXINP selects the interrupt output line which becomes activated at ...

Page 1357: ...n a successful data transfer receive or transmit If SDT 1 and message object n is a FIFO base object then MSGVAL is reset when the pointer to the current object CUR reaches the value of SEL in the FIFO Gateway Pointer Register With SDT 0 bit MSGVAL is not affected STT 23 rw Single Transmit Trial If this bit is set then TXRQ is cleared on transmission start of message object n Thus no transmission ...

Page 1358: ...T points to the first element in a FIFO structure TOP 15 8 rw Top Pointer Bit field TOP points to the last element in a FIFO structure CUR 23 16 rwh Current Object Pointer Bit field CUR points to the actual target object within a FIFO Gateway structure After a FIFO gateway operation CUR is updated with the message number of the next message object in the list structure given by PNEXT of the messag...

Page 1359: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 AM rw Field Bits Type Description AM 28 0 rw Acceptance Mask for Message Identifier Bit field AM is the 29 bit mask for filtering incoming messages with standard identifiers AM 28 18 or extended identifiers AM 28 0 For standard identifiers bits AM 17 0 are don t care MIDE 29 rw Acceptance Mask Bit for Message IDE Bit 0B Message object n accepts the reception of both s...

Page 1360: ... 26 25 24 23 22 21 20 19 18 17 16 PRI IDE ID rw rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID rwh Field Bits Type Description ID 28 0 rwh CAN Identifier of Message Object n Identifier of a standard message ID 28 18 or an extended message ID 28 0 For standard identifiers bits ID 17 0 are don t care IDE 29 rwh Identifier Extension Bit of Message Object n 0B Message object n handles standard frame...

Page 1361: ...ss PRI also determines the acceptance filtering method for transmission 00B Reserved 01B Transmit acceptance filtering is based on the list order This means that message object n is considered for transmission only if there is no other message object with valid transmit request MSGVAL TXEN0 TXEN1 1 somewhere before this object in the list 10B Transmit acceptance filtering is based on the CAN ident...

Page 1362: ...e B MOAR IDE 1 send Extended Frame Standard Frames have higher transmit priority than Extended Frames with equal standard identifier A MOAR 28 18 B MOAR 28 18 A MOAR IDE B MOAR IDE 0 A MOCTR DIR 1 send Data Frame B MOCTR DIR 0 send Remote Fame Standard Data Frames have higher transmit priority than standard Remote Frames with equal identifier A MOAR 28 0 B MOAR 28 0 A MOAR IDE B MOAR IDE 1 A MOCTR...

Page 1363: ... and ignored for transmission MODATALn n 0 127 Message Object n Data Register Low 1010H n 20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB3 DB2 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB1 DB0 rwh rwh Field Bits Type Description DB0 7 0 rwh Data Byte 0 of Message Object n DB1 15 8 rwh Data Byte 1 of Message Object n DB2 23 16 rwh Data Byte 2 of Message Object n DB...

Page 1364: ... and ignored for transmission MODATAHn n 0 127 Message Object n Data Register High 1014H n 20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 DB6 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 DB4 rwh rwh Field Bits Type Description DB4 7 0 rwh Data Byte 4 of Message Object n DB5 15 8 rwh Data Byte 5 of Message Object n DB6 23 16 rwh Data Byte 6 of Message Object n D...

Page 1365: ... Port 3 The MultiCAN module is also supplied by clock control interrupt control and address decoding logic MultiCAN interrupts can be directed to the DMA controller and the GPTA modules CAN interrupts are able to trigger DMA transfers and GPTA operations Figure 19 24 CAN Module Implementation and Interconnections MultiCAN Module Kernel mca06281_3_128 vsd Interrupt Control fCAN CAN Control Message ...

Page 1366: ...sters listed in Figure 19 25 are not included in the MultiCAN module kernel but must be programmed for proper operation of the MultiCAN module Figure 19 25 CAN Implementation specific Special Function Registers CAN_CLC MCA06282_15 P3_IOCR12 Clock Control Registers Port Registers P3_PDR CAN_SRCm Interrupt Registers CAN_FDR m 0 15 P9_IOCR0 P9_PDR ...

Page 1367: ... clock frequency fSYS The clock control register CAN_CLC makes it possible to enable disable fCLC under certain conditions The module timer clock fCAN is used inside the MultiCAN module as input clock for all timing relevant operations e g bit timing The settings in the CAN_FDR register determine the frequency of the module timer clock fCAN according the following two formulas 19 1 19 2 Equation 1...

Page 1368: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the suspen...

Page 1369: ...ranted or immediate Suspend Mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in Suspend Mode DM 15 14 rw Divider Mode This bit field selects normal divider mode fractional divider mode and off state RESULT 25 16 rh Result Value Bit field for the addition result SUSACK 28 rh Suspend Mode Acknowledge Indicates state of SPNDACK signal SUSREQ 29 rh Susp...

Page 1370: ...d for the required I O functionality of the CAN I O lines 19 5 4 2 Node Receive Input Selection Additionally to the I O control selection as defined in Table 19 14 the selection of a CAN node s receive input line requires that bit field RXSEL in its node port control register NPCRx must be set according to Table 19 15 Values for NPCRx RXSEL other than those of Table 19 15 result in a recessive rec...

Page 1371: ...19 15 Receive Input Selection Receive Input of Connected to Selected by CAN Node 0 P3 12 RXDCAN0 NPCR0 RXSEL 000B P3 14 RXDCAN1 NPCR0 RXSEL 001B CAN Node 1 P3 14 RXDCAN1 NPCR1 RXSEL 000B P3 12 RXDCAN0 NPCR1 RXSEL 001B P9 0 RXDCAN2 NPCR1 RXSEL 010B CAN Node 2 P9 0 RXDCAN2 NPCR2 RXSEL 000B P3 12 RXDCAN0 NPCR2 RXSEL 001B P4 0 RXDCAN2 NPCR2 RXSEL 010B Table 19 16 CAN to DMA Request Connections DMA Cha...

Page 1372: ... Each of the 140 hardware initiated interrupt sources is controlled by a 4 bit interrupt pointer that directs the interrupt source to one of the sixteen interrupt outputs INT_Om m 0 15 This makes it possible to connect more than one interrupt source between one and all to one interrupt output line The interrupt wiring matrix shown in Figure 19 27 is built up according to the following rules Each o...

Page 1373: ...ser s Manual 19 117 V1 1 2011 05 MLI V2 0 Figure 19 27 Interrupt Compressor Mca06284_3a_128 vsd 16 Register MITR CAN Node 0 4 4 CAN Node 1 INT_O14 INT_O15 1 1 INT_O0 INT_O1 1 1 Interrupt Wiring Matrix 2 Message Object 0 2 Message Object 128 4 CAN Node 2 ...

Page 1374: ... Some of the sixteen interrupt outputs of the MultiCAN module can be used to trigger operations in the DMA controller CAN_SRCm m 0 15 CAN Service Request Control Register m 0FCH m 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Req...

Page 1375: ... address map from Page 19 57 the complete MultiCAN module register address map of Figure 19 28 also shows the general implementation specific registers for clock control module identification and interrupt service request control and adds the absolute address information For the implementation parameters number of nodes and objects of the specific device see the Table 19 24 ...

Page 1376: ...Reg NodexFrameCounterReg 300H Node1Registers NBASE 00H MOnFunctionControl Reg MOnFIFO Gtw Ptr Reg MO MessageObject n 0to MessageObjects 1 MOnInterrupt Ptr Reg MOnAccept MaskReg MOnArbitrationReg MOnDataRegisterLow MOnDataRegisterHigh MOBASE 14H 1000H MessageObject 0 MessageObject n 1020H MOBASE MOnControl StatusReg MOBASE 1CH MOBASE 18H MOBASE 10H MOBASE 08H MOBASE 0CH MOBASE 00H MOBASE 04H 3FFFH ...

Page 1377: ...bal view of the E Ray interface Figure 20 1 General Block Diagram of the E Ray Interface The E Ray module communicates with the external world via three I O lines each channel The RXDAx and RXDBx lines are the receive data input signals TXDA and 1 Infineon Infineon Technologies are trademarks of Infineon Technologies AG FlexRay is a trademark of FlexRay Consortium eray_overview_fpi vsd Address Dec...

Page 1378: ...ent Service Request Control and to access the Message RAM via Input Output Buffer The E Ray IP module supports the following features Conformance with FlexRay protocol specification v2 1 Data rates of up to 10 Mbit s on each channel Up to 128 Message Buffers configurable 8 Kbyte of Message RAM for storage of e g 128 Message Buffers with max 48 byte data field or up to 30 Message Buffers with 254 b...

Page 1379: ...bmodules Figure 20 2 E Ray Block Diagram Customer Host Interface CIF Connects the FPI Bus to the E Ray IP module via the Generic Host Interface Generic Host Interface GIF The E Ray IP module is provided with an 8 16 32 bit Generic Host Interface prepared for the connection to a wide range of customer specific Hosts Configuration registers status registers and service request registers are attached...

Page 1380: ...elected Message Buffer to the Output Buffer After the transfer has completed the Host can read the Header and Data Section of the transferred Message Buffer from the Output Buffer Message Handler MHD The E Ray Message Handler controls data transfers between the following components Input Output Buffer and Message RAM Transient Buffer RAMs of the two FlexRay Protocol Controllers and Message RAM Mes...

Page 1381: ...erant clock synchronization by FTM algorithm Rate correction Offset correction Cycle counter Timing control of static segment Timing control of dynamic segment minislotting Support of external clock correction System Universal Control SUC The System Universal Control controls the following functions Configuration Wakeup Startup Normal Operation Passive Operation Monitor Mode Frame and Symbol Proce...

Page 1382: ...ption transmission Addresses 0004H 000FH 03C8H 03ECH and 0800H 0FFFH are reserved for customer specific purposes All functions related to these addresses are located in the Customer Host Interface The test registers located on address 0010H and 0014H are writable only under the conditions described in Special Registers on Page 20 23 The assignment of the Message Buffers is done according to the sc...

Page 1383: ...figured with the key slot ID and can be re configured in DEFAULT_CONFIG or CONFIG state only The second group consists of Message Buffers assigned to the static or to the dynamic segment Message Buffers belonging to this group may be reconfigured during run time from dynamic to static or vice versa depending on the state of MRC SEC The Message Buffers belonging to the third group are concatenated ...

Page 1384: ...ister 0000H SV U SV E 3 Page 20 264 CUST1 Busy and Input Buffer Control Register 0004H SV U SV U 3 Page 20 17 ID Module Identification Register 0008H SV U BE 3 Page 20 16 CUST3 Customer Interface Timeout Counter 000CH SV U SV U 3 Page 20 20 Special Registers TEST1 Test Register 1 0010H SV U SV U 3 Page 20 23 TEST2 Test Register 2 0014H SV U SV U 3 Page 20 28 Reserved 0018H BE BE LCK Lock Register ...

Page 1385: ...SV U 3 Page 20 81 STPW2 Stop Watch Register 2 0050H SV U SV U 3 Page 20 83 Reserved 0054H 007CH BE BE Communication Controller Control Registers SUCC1 SUC Configuration Register 1 0080H SV U SV U 3 Page 20 84 SUCC2 SUC Configuration Register 2 0084H SV U SV U 3 Page 20 92 SUCC3 SUC Configuration Register 3 0088H SV U SV U 3 Page 20 93 NEMC NEM Configuration Register 008CH SV U SV U 3 Page 20 94 PR...

Page 1386: ...0 105 GTUC08 GTU Configuration Register 8 00BCH SV U SV U 3 Page 20 106 GTUC09 GTU Configuration Register 9 00C0H SV U SV U 3 Page 20 107 GTUC10 GTU Configuration Register 10 00C4H SV U SV U 3 Page 20 108 GTUC11 GTU Configuration Register 11 00C8H SV U SV U 3 Page 20 109 Reserved 00CCH 00FCH BE BE Communication Controller Status Registers CCSV Communication Controller Status Vector 0100H SV U BE 3...

Page 1387: ...OSIDnn Odd Sync ID Symbol Window nn 0170H 01A8H SV U BE 3 Page 20 131 Reserved 01ACH SV U BE NMVx Network Management Vector 1 3 01B0H 01B8H SV U BE 3 Page 20 133 Reserved 01BCH 02FCH nBE BE Message Buffer Control Registers MRC Message RAM Configuration 0300H SV U SV U 3 Page 20 134 FRF FIFO Rejection Filter 0304H SV U SV U 3 Page 20 137 FRFM FIFO Rejection Filter Mask 0308H SV U SV U 3 Page 20 139...

Page 1388: ...Page 20 155 NDAT3 New Data Register 3 0338H SV U BE 3 Page 20 156 NDAT4 New Data Register 4 033CH SV U BE 3 Page 20 157 MBSC1 Message Buffer Status Changed 1 0340H SV U BE 3 Page 20 158 MBSC2 Message Buffer Status Changed 2 0344H SV U BE 3 Page 20 159 MBSC3 Message Buffer Status Changed 3 0348H SV U BE 3 Page 20 160 MBSC4 Message Buffer Status Changed 4 034CH SV U BE 3 Page 20 161 Reserved 0350H 0...

Page 1389: ...utput Buffer Busy Service Request Control Register 03CCH SV U SV U 3 Page 20 275 MBSC1SRC Message Buffer Status Changed 1 Service Request Control Register 03D0H SV U SV U 3 Page 20 275 MBSC0SRC Message Buffer Status Changed 0 Service Request Control Register 03D4H SV U SV U 3 Page 20 275 NDAT1SRC New Data 1 Service Request Control Register 03D8H SV U SV U 3 Page 20 275 NDAT0SRC New Data 0 Service ...

Page 1390: ...4H SV U SV U 3 Page 20 169 WRHS3 Write Header Section 3 0508H SV U SV U 3 Page 20 170 Reserved 050CH BE BE IBCM Input Buffer Command Mask 0510H SV U SV U 3 Page 20 171 IBCR Input Buffer Command Request 0514H SV U SV U 3 Page 20 173 Reserved 0518H 05FCH BE BE Output Buffer RDDSn Read Data Section 1 64 0600H 06FCH SV U BE 3 Page 20 175 RDHS1 Read Header Section 1 0700H SV U BE 3 Page 20 176 RDHS2 Re...

Page 1391: ...ol 0808H SV U SV E 3 Page 20 31 ECCR ECC Data Read 080CH SV U SV U 3 Page 20 33 ECCW ECC Data Write 0810H SV U SV U 3 Page 20 34 Reserved 0814H BE BE 1 The absolute register address is calculated as follows Module Base Address Offset Address shown in this column Table 20 3 Registers OverviewE Ray Kernel Registers cont d Register Short Name Register Long Name Offset Addr 1 Access Mode Reset Class D...

Page 1392: ...egister 0008H Reset Value 0044 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number MOD_REV defines the module revision number The value of a module revision starts with 01H first revision MOD_TYPE 15 8 r Module Type The value of this bit field is C0H It defines...

Page 1393: ...timeout has occurred during the auto delay scheme and must be reset by writing zero to INT0 Note In case hardware sets INT0 and at the same point of time software clears INT0 INT0 is cleared OEN 1 rw Enable auto delay scheme for Output Buffer Control Register OBCR This control bit controls the delay scheme for Output Buffer Control Register OBCR read accesses 0B Disable auto delay scheme for Outpu...

Page 1394: ...active Read 0B Lower Page 256 Bytes of Input Buffer RAM 1 selected 1B Upper Page 256 Bytes of Input Buffer RAM 1 selected Write 0B Select Lower Page 256 Bytes of Input Buffer RAM 1 1B Select Upper Page 256 Bytes of Input Buffer RAM 1 Note Write is only possible if Input Buffer RAM 1 is currently accessible by the host via CIF and therefore IBFS set IBF2PAG 7 rw Input Buffer 2 Page Select Register ...

Page 1395: ...ve Input Select Channel B 00B Channel B receiver input RXDB0 selected 01B Channel B receiver input RXDB1 selected 10B Channel B receiver input RXDB2 selected 11B Channel B receiver input RXDB3 selected STPWTS 15 14 rw Stop Watch Trigger Input Select 00B Stop Watch Trigger input STPWT0 selected 01B Stop Watch Trigger input STPWT1 selected 10B Stop Watch Trigger input STPWT2 selected 11B Stop Watch ...

Page 1396: ... a service request will be generated A canceled read access provides a 0 value A canceled write access does not modify any bits in the OBCR or IBCR In addition the bit CUST1 INT0 of the service request status register will be set and must be reset by the host to disable the service request line The read and write access to the Output Buffer Control Register OBCR may be configured without automatic...

Page 1397: ...BF and host IBF to shadow IBF the content of the shadow IBF is copied into the MBF IBF MBF and IBCR IBSYS is set Writing to IBCR IBRH a second time while IBCR IBSYS remained set previously initiated copy process IBF MBF ongoing will correctly update IBCR IBRH and set IBCR IBSYH This will set the signal IBUSY A third access read or write to IBCR while IBCR IBSYH remains set will cancel this third a...

Page 1398: ...shadow IBF During this time the bus is locked and no further access to E Ray module is possible due to the ongoing stalled read or write operation Because no access is possible to the E Ray module read or write stall may only be detected through the signal TIBC or due to other not processed read or write accesses to the E Ray module So setting CUST3 TO FFFFFFFFH CUST1 IEN 1 and CUST1 OEN 1 will al...

Page 1399: ... chapter and as required by the FlexRay protocol specification and the FlexRay conformance test is not possible Test mode functions may not be combined with each other or with FlexRay protocol functions The test mode features are intended for hardware testing or for FlexRay bus analyzer tools They are not intended to be used in FlexRay applications TEST1 Test Register 1 0010H Reset Value 0000 0300...

Page 1400: ...re multiplexed to make all RAM blocks of the E Ray module directly accessible by the Host This mode is intended to enable testing of the embedded RAM blocks during production testing 10B I O Test Mode Output pins are driven to the values defined by bits TXA TXB TXENA TXENB The values applied to the input pins can be read from register bits RXA and RXB 11B Reserved should not be used AOA 8 rh Activ...

Page 1401: ...ort Channel A1 Set when a coding error is detected on channel A Reset to zero when register TEST1 is read or written Once the CERA is set it will remain unchanged until the Host accesses the TEST1 register 0000B No coding error detected 0001B Header CRC error detected 0010B Frame CRC error detected 0011B Frame Start Sequence FSS too long 0100B First bit of Byte Start Sequence BSS seen LOW 0101B Se...

Page 1402: ...it IBCM STXRS in the Input Buffer Command Mask register is set to 1 In this mode wake up startup and clock synchronization are bypassed The CHI command SEND_MTS results in the immediate transmission of an MTS symbol CERB 31 28 rh Coding Error Report Channel B1 Set when a coding error is detected on channel B Reset to zero when register TEST1 is read or written Once the CERB is set it will remain u...

Page 1403: ...e pins TXDA and TXDB are set to HIGH pins RXDAn and RXDBn are not evaluated When the Communication Controller is in loop back mode a loop back test is started by the Host writing a message to the Input Buffer and requesting the transmission by writing to the Input Buffer Command Request register IBCR The Message Handler will transfer the message into the Message RAM and then into the Transient Buf...

Page 1404: ...et Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WR ECC 0 SSEL 0 RS r rw r rw r rw Field Bits Type Description RS 2 0 rw RAM Select In RAM Test mode the RAM blocks selected by RS are mapped to module address 0000 0400H to 0000 07FFH 1024 byte addresses 000B Input Buffer RAM 1 IBF1 001B Input Buffer RAM 2 IBF2 010B Output Buffer RAM 1 O...

Page 1405: ...800H to 0BFFH enabled 011B access to RAM byte 0C00H to 0FFFH enabled 100B access to RAM byte 1000H to 11FFH enabled 101B access to RAM byte 1400H to 17FFH enabled 110B access to RAM byte 1800H to 1BFFH enabled 111B access to RAM byte 1C00H to 1FFFH enabled WR ECC 14 rw Write ECC Data Enable Content of ECCW is transferred to the RAM 0B disabled 1B enabled Note Test mode must be entered See Test Reg...

Page 1406: ...yte addresses or 256 word addresses Because the length of the Message RAM exceeds the available address space the Message RAM is segmented into segments of 1024 byte The segments can be selected by programming TEST2 SSEL in the Test Register 2 Figure 20 3 RAM test mode Access to E Ray RAM Blocks Normal Operation RAM Test OBF2 TBF1 TBF2 RS 010B 011B 100B SSEL 000B 000H 3FCH 400H 000B 001B 010B 011B...

Page 1407: ...ED O2 EN DED O1 EN DED T2 EN DED T1 EN DED M EN r rw rw rw rw rw rw rw Field Bits Type Description DED M EN 0 rw Double Bit Error Detection for Message Buffer MBF RAM Enable Test Disable 0B OFF 1B ON DED T1 EN 1 rw Double Bit Error Detection for Transfer Buffer 1 TBF1 RAMs Enable Test Disable 0B OFF 1B ON DED T2 EN 2 rw Double Bit Error Detection for Transfer Buffer 2 TBF2 RAMs Enable Test Disable...

Page 1408: ... I1 EN 5 rw Double Bit Error Detection for Input Buffer 1 IBF1 RAM Enable Test Disable 0B OFF 1B ON DED I2 EN 6 rw Double Bit Error Detection for Input Buffer 2 IBF2 RAM Enable Test Disable 0B OFF 1B ON 0 31 7 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1409: ...CPU For dedicated RAM access to selected addresses by the CPU Test mode must be entered See Test Register 2 TEST2 on Page 20 28 ECCR ECC Data Read Register 080CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ECC r rh Field Bits Type Description ECC 6 0 rh Error Correction Data of the last accessed RAM address 0 31 7 r Reserved Re...

Page 1410: ...ECCW to become effective and for dedicated RAM access to selected addresses by the CPU Test mode must be entered See Test Register 1 TEST1 on Page 20 23 The referring RAM must be selected See Test Register 2 TEST2 on Page 20 28 Note Content of ECCW is transferred to the RAM only if TEST2 WRECC is set ECCW ECC Data Write Register 0810H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 1411: ...FIG state by writing to SUCC1 CMD commands READY MONITOR_MODE ATM LOOP_BACK in the SUC Configuration Register 1 the write operation has to be directly preceded by two consecutive write accesses to the Configuration Lock Key unlock sequence If the write sequence below is interrupted by other write accesses between the second write to the Configuration Lock Key and the write access to the SUCC1 regi...

Page 1412: ...es to other locations the Communication Controller remains in CONFIG state and the sequence has to be repeated First write LCK CLK CEH 1100 1110B Second write LCK CLK 31H 0011 0001B TMK 15 8 w Test Mode Key To set bit TEST1 WRTEN the write operation has to be directly preceded by two consecutive write accesses to the Test Mode Key If the write sequence is interrupted by other write accesses betwee...

Page 1413: ...LTV B EDB 0 TAB A LTV A EDA r rwh rwh rwh r rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MHF IO BA II BA EFA RFO EER R CCL CCF SFO SFB M CNA PEM C r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description PEMC 0 rwh POC Error Mode Changed This flag is set whenever the error mode signalled by CCEV ERRM in the Communication Controller Error Vector register has changed 0B E...

Page 1414: ...he last communication cycle or the total number of SYNC Frames received during the last double cycle exceeds the maximum number of SYNC Frames as defined by GTUC02 SNM in the GTU Configuration Register 2 0B Number of received SYNC Frames GTUC02 SNM 1B More SYNC Frames received than configured by GTUC02 SNM This flag is cleared by writing a 1 CCF 4 rwh Clock Correction Failure This flag is set at t...

Page 1415: ...s from 0 to 1 See also Message Handler Status MHDS on Page 20 141 0B No error detected 1B Error detected RFO 7 rh Receive FIFO Overrun The flag is set by the Communication Controller when a receive FIFO overrun is detected When a receive FIFO overrun occurs the oldest message is overwritten with the actual received message The actual state of the FIFO is monitored in register FSR 0B No receive FIF...

Page 1416: ...n of any message buffer belonging to the receive FIFO 2 The Host writes to any register of the Input Buffer while IBCR IBSYS is set 0B No illegal Host access to Input Buffer occurred 1B Illegal Host access to Input Buffer occurred IOBA 10 rwh Illegal Output Buffer Access This flag is set by the Communication Controller when the Host requests the transfer of a Message Buffer from the Message RAM to...

Page 1417: ...ion Across Boundary Channel A The flag signals to the Host that a transmission across a slot boundary occurred for channel A 0B No transmission across slot boundary detected on channel A 1B Transmission across slot boundary detected on channel A This flag is cleared by writing a 1 EDB 24 rwh Error Detected on Channel B This bit is set whenever one of the flags ACS SEDB ACS CEDB ACS CIB ACS SBVB ch...

Page 1418: ...g signals to the Host that a transmission across a slot boundary occurred for channel B 0B No transmission across slot boundary detected on channel B 1B Transmission across slot boundary detected on channel B This flag is cleared by writing a 1 0 15 12 23 19 31 27 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1419: ...AS WST rwh rwh rwh rwh rwh rwh rwh rwh rwh rh rh rwh rwh rwh rwh rwh Field Bits Type Description WST 0 rwh Wakeup Status This flag is set when the wakeup status vector CCSV WSV in the Communication Controller Status Vector register changes to a value other than UNDEFINED 0B Wake up status unmodified 1B Wake up status modified and not UNDEFINED This flag is cleared by writing a 1 CAS 1 rwh Collisio...

Page 1420: ... been set to 1 1B At least one ND flag of a receive buffer with WRHS1 MBI 1 has been set to 1 This flag is cleared by writing a 1 RFNE 5 rh Receive FIFO Not Empty This flag is set by the Communication Controller when a received valid Frame was stored into the empty receive FIFO m The actual state of the receive FIFO is monitored in register FSR 0B Receive FIFO is empty 1B Receive FIFO is not empty...

Page 1421: ...This flag is set whenever a transfer from Input Buffer to the Message RAM has completed and bit IBCR IBSYS in the Input Buffer Command Request register has been reset by the Message Handler 0B No transfer completed 1B Transfer between Input Buffer and Message RAM completed This flag is cleared by writing a 1 TOBC 11 rwh Transfer Output Buffer Completed This flag is set whenever a transfer from Mes...

Page 1422: ... This flag is cleared by writing a 1 SDS 15 rwh Start of Dynamic Segment This flag is set by the Communication Controller when the dynamic segment starts 0B Dynamic segment not yet started 1B Dynamic segment started WUPA 16 rwh Wakeup Pattern Channel A This flag is set by the Communication Controller when a wakeup pattern was received on channel A Only set when the Communication Controller is in W...

Page 1423: ... pattern received on channel B 1B Wake up pattern received on channel B This flag is cleared by writing a 1 MTSB 25 rwh MTS Received on Channel B vSS ValidMTSB Media Access Test symbol received on channel B during the proceeding symbol window Updated by the Communication Controller for each channel at the end of the symbol window 0B No MTS symbol received on channel B 1B MTS symbol received on cha...

Page 1424: ...L EDB L 0 TAB AL LTV AL EDA L r rw rw rw r rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MHF L IOB AL IIBA L EFA L RFO L EER RL CCL L CCF L SFO L SFB ML CNA L PEM CL r rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description PEMCL 0 rw POC Error Mode Changed Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request lin...

Page 1425: ...quest assigned to service request line INT1SRC EERRL 6 rw ECC Error Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC RFOL 7 rw Receive FIFO Overrun Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC EFAL 8 rw Empty FIF...

Page 1426: ...ervice request line INT1SRC LTVAL 17 rw Latest Transmit Violation Channel A Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC TABAL 18 rw Transmission Across Boundary Channel A Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line...

Page 1427: ...BL 26 rw Transmission Across Boundary Channel A Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC 0 15 12 23 19 31 27 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1428: ...UP BL 0 MTS AL WUP AL r rw rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDS L MBS IL SUC SL SWE L TOB CL TIBC L TI1L TI0L NMV CL RFC LL RFN EL RXIL TXIL CYC SL CAS L WST L rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description WSTL 0 rw Wakeup Status Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service requ...

Page 1429: ...ed to service request line INT1SRC RFCLL 6 rw Receive FIFO Critical Level Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC NMVCL 7 rw Network Management Vector Changed Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC...

Page 1430: ...t assigned to service request line INT1SRC SUCSL 13 rw Startup Completed Successfully Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC MBSIL 14 rw Message Buffer Status Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SR...

Page 1431: ...NT1SRC WUPBL 24 rw Wakeup Pattern Channel B Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC MTSBL 25 rw Media Access Test Symbol Channel B Service Request Line 0B Service Request assigned to service request line INT0SRC 1B Service Request assigned to service request line INT1SRC 0 23 18 31 26 r Reserved Re...

Page 1432: ...16 0 TAB BE LTV BE EDB E 0 TAB AE LTV AE EDA E r rwh rwh rwh r rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MHF E IOB AE IIBA E EFA E RFO E EER RE CCL E CCF E SFO E SFB ME CNA E PEM CE r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description PEMCE 0 rwh POC Error Mode Changed Service Request Enable Read 0B Protocol Error Mode Changed Service Request disabled 1B Protocol...

Page 1433: ...able Protocol Error Mode Changed Service Request CCFE 4 rwh Clock Correction Failure Service Request Enable Read 0B Clock Correction Failure Service Request disabled 1B Clock Correction Failure Service Request enabled Write 0B Unchanged 1B Enable Clock Correction Failure Service Request CCLE 5 rwh CHI Command Locked Service Request Enable Read 0B CHI Command Locked Service Request disabled 1B CHI ...

Page 1434: ...vice Request Enable Read 0B Illegal Input Buffer Access Service Request disabled 1B Illegal Input Buffer Access Service Request enabled Write 0B Unchanged 1B Enable Illegal Input Buffer Access Service Request IOBAE 10 rwh Illegal Output Buffer Access Service Request Enable Read 0B Illegal Output Buffer Access Service Request disabled 1B Illegal Output Buffer Access Service Request enabled Write 0B...

Page 1435: ...iolation Channel A Service Request enabled Write 0B Unchanged 1B Enable Latest Transmit Violation Channel A Service Request TABAE 18 rwh Transmission Across Boundary Channel A Service Request Enable Read 0B Transmission Across Boundary Channel A Service Request disabled 1B Transmission Across Boundary Channel A Service Request enabled Write 0B Unchanged 1B Enable Transmission Across Boundary Chann...

Page 1436: ...abled Write 0B Unchanged 1B Enable Latest Transmit Violation Channel B Service Request TABBE 26 rwh Transmission Across Boundary Channel B Service Request Enable Read 0B Transmission Across Boundary Channel B Service Request disabled 1B Transmission Across Boundary Channel B Service Request enabled Write 0B Unchanged 1B Enable Transmission Across Boundary Channel B Service Request 0 15 12 23 19 31...

Page 1437: ...0 TAB BE LTV BE EDB E 0 TAB AE LTV AE EDA E r rwh rwh rwh r rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MHF E IOB AE IIBA E EFA E RFO E EER RE CCL E CCF E SFO E SFB ME CNA E PEM CE r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description PEMCE 0 rwh POC Error Mode Changed Service Request Enable Read 0B Protocol Error Mode Changed Service Request disabled 1B Protocol Er...

Page 1438: ...ble Protocol Error Mode Changed Service Request CCFE 4 rwh Clock Correction Failure Service Request Enable Read 0B Clock Correction Failure Service Request disabled 1B Clock Correction Failure Service Request enabled Write 0B Unchanged 1B Disable Clock Correction Failure Service Request CCLE 5 rwh CHI Command Locked Service Request Enable Read 0B CHI Command Locked Service Request disabled 1B CHI ...

Page 1439: ...ice Request Enable Read 0B Illegal Input Buffer Access Service Request disabled 1B Illegal Input Buffer Access Service Request enabled Write 0B Unchanged 1B Disable Illegal Input Buffer Access Service Request IOBAE 10 rwh Illegal Output Buffer Access Service Request Enable Read 0B Illegal Output Buffer Access Service Request disabled 1B Illegal Output Buffer Access Service Request enabled Write 0B...

Page 1440: ...iolation Channel A Service Request enabled Write 0B Unchanged 1B Disable Latest Transmit Violation Channel A Service Request TABAE 18 rwh Transmission Across Boundary Channel A Service Request Enable Read 0B Transmission Across Boundary Channel A Service Request disabled 1B Transmission Across Boundary Channel A Service Request enabled Write 0B Unchanged 1B Enable Transmission Across Boundary Chan...

Page 1441: ...bled Write 0B Unchanged 1B Disable Latest Transmit Violation Channel B Service Request TABBE 26 rwh Transmission Across Boundary Channel B Service Request Enable Read 0B Transmission Across Boundary Channel B Service Request disabled 1B Transmission Across Boundary Channel B Service Request enabled Write 0B Unchanged 1B Disable Transmission Across Boundary Channel B Service Request 0 15 12 23 19 3...

Page 1442: ... 0 SDS E MBS IE SUC SE SWE E TOB CE TIBC E TI1E TI0E NMV CE RFC LE RFN EE RXIE TXIE CYC SE CAS E WST E rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description WSTE 0 rwh Wakeup Status Service Request Enable Read 0B Wake up Status Service Request disabled 1B Wake up Status Service Request enabled Write 0B Unchanged 1B Enable Wakeup Status Service Request CASE 1 r...

Page 1443: ...O Not Empty Service Request disabled 1B Receive FIFO Not Empty Service Request enabled Write 0B Unchanged 1B Enable Receive FIFO Not Empty Service Request RFCLE 6 rwh Receive FIFO Critical Level Service Request Enable Read 0B Receive FIFO Critical Level Service Request disabled 1B Receive FIFO Critical Level Service Request enabled Write 0B Unchanged 1B Enable Receive FIFO Critical Level Service R...

Page 1444: ...ervice Request Enable Read 0B Wakeup Status Service Request disabled 1B Wakeup Status Service Request enabled Write 0B Unchanged 1B Enable Wakeup Status Service Request TOBCE 11 rwh Transfer Output Buffer Completed Service Request Enable Read 0B Transfer Input Buffer Completed Service Request disabled 1B Transfer Input Buffer Completed Service Request enabled Write 0B Unchanged 1B Enable Transfer ...

Page 1445: ... Status Service Request disabled 1B Message Buffer Status Service Request enabled Write 0B Unchanged 1B Enable Message Buffer Status Service Request SDSE 15 rwh Start of Dynamic Segment Service Request Enable Read 0B Start of Dynamic Service Request disabled 1B Start of Dynamic Service Request enabled Write 0B Unchanged 1B Enable Start of Dynamic Service Request WUPAE 16 rwh Wakeup Pattern Channel...

Page 1446: ...ern Channel B Service Request Enable Read 0B Wakeup Pattern Channel B Service Request disabled 1B Wakeup Pattern Channel B Service Request enabled Write 0B Unchanged 1B Enable Wakeup Pattern Channel A Service Request MTSBE 25 rwh Media Access Test Symbol Channel B Service Request Enable Read 0B Media Access Test Symbol Channel B Service Request disabled 1B Media Access Test Symbol Channel B Servic...

Page 1447: ... 2 1 0 SDS E MBS IE SUC SE SWE E TOB CE TIBC E TI1E TI0E NMV CE RFC LE RFN EE RXIE TXIE CYC SE CAS E WST E rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description WSTE 0 rwh Wakeup Status Service Request Enable Read 0B Wakeup Status Service Request disabled 1B Wakeup Status Service Request enabled Write 0B Unchanged 1B Disable Wakeup Status Service Request CASE ...

Page 1448: ...0B Receive FIFO Not Empty Service Request disabled 1B Receive FIFO Not Empty Service Request enabled Write 0B Unchanged 1B Disable Receive FIFO Not Empty Service Request RFCLE 6 rwh Receive FIFO Critical Level Service Request Enable Read 0B Service Request disabled 1B Receive FIFO Critical Level Service Request enabled Write 0B Unchanged 1B Disable Receive FIFO Critical Level Service Request NMVCE...

Page 1449: ...ice Request Enable Read 0B Wakeup Status Service Request disabled 1B Wakeup Status Service Request enabled Write 0B Unchanged 1B Disable Wakeup Status Service Request TOBCE 11 rwh Transfer Output Buffer Completed Service Request Enable Read 0B Transfer Input Buffer Completed Service Request disabled 1B Transfer Input Buffer Completed Service Request enabled Write 0B Unchanged 1B Disable Transfer I...

Page 1450: ...Status Service Request disabled 1B Message Buffer Status Service Request enabled Write 0B Unchanged 1B Disable Message Buffer Status Service Request SDSE 15 rwh Start of Dynamic Segment Service Request Enable Read 0B Start of Dynamic Service Request disabled 1B Start of Dynamic Service Request enabled Write 0B Unchanged 1B Disable Start of Dynamic Service Request WUPAE 16 rwh Wakeup Pattern Channe...

Page 1451: ...rn Channel B Service Request Enable Read 0B Wakeup Pattern Channel B Service Request disabled 1B Wakeup Pattern Channel B Service Request enabled Write 0B Unchanged 1B Disable Wakeup Pattern Channel A Service Request MTSBE 25 rwh Media Access Test Symbol Channel B Service Request Enable Read 0B Media Access Test Symbol Channel B Service Request disabled 1B Media Access Test Symbol Channel B Servic...

Page 1452: ...t Line Enable 0040H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EINT 1 EINT 0 r rw rw Field Bits Type Description EINT0 0 rw Enable Service Request Line 0 INT0SRC 0B Service Request line disabled 1B Service Request line enabled EINT1 1 rw Enable Service Request Line 1 INT1SRC 0B Service Request line disabled 1B Service Request ...

Page 1453: ...o be halted first by writing 0 to bit T0RC T0C Timer 0 Configuration 0044H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 T0MO r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 T0CC 0 T0M S T0R C r rw r rw rwh Field Bits Type Description T0RC 0 rwh Timer 0 Run Control 0B Timer 0 halted 1B Timer 0 running T0MS 1 rw Timer 0 Mode Select 0B Single shot mode 1B Continuous mode T0CC...

Page 1454: ...st the Macrotick counter value there is no separate counter for timer 0 In case the Communication Controller leaves NORMAL_ACTIVE or NORMAL_PASSIVE state or if timer 0 is halted by Host command output signal TINT0SR is reset to 0 immediately 0 7 2 15 31 30 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1455: ...o states Before reconfiguration of the timer the timer has to be halted first by resetting bit T1RC to 0 T1C Timer 1 Configuration 0048H Reset Value 0002 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 T1MC r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 T1M S T1R C r rw rwh Field Bits Type Description T1RC 0 rwh Timer 1 Run Control 0B Timer 1 halted 1B Timer 1 running T1MS 1 rw Timer 1 Mode ...

Page 1456: ...oller E Ray User s Manual 20 80 V1 1 2011 05 E Ray V3 13 Note In case the Communication Controller leaves NORMAL_ACTIVE or NORMAL_PASSIVE state or if timer 1 is halted by Host command output signal TINT1SR is reset to 0 immediately ...

Page 1457: ...ue 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SMTV r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SCCV 0 EINT 1 EINT 0 EET P SSW T EDG E SWM S ESW T r rh r rw rw rw rwh rw rw rwh Field Bits Type Description ESWT 0 rwh Enable Stop Watch Trigger If enabled an edge on input STPW or a service request 0 or 1 event rising edge on signal INT0SR or INT1SR activates the stop watch In single...

Page 1458: ...event via signal STPW if ESWT 1 0B Stop watch trigger via signal STPW disabled 1B Edge on signal STPW triggers stop watch EINT0 5 rw Enable Service Request 0 Trigger Enables stop watch trigger by service request 0 event if ESWT 1 0B Stop watch trigger by service request 0 disabled 1B Service Request 0 event triggers stop watch EINT1 6 rw Enable Service Request 1 Trigger Enables stop watch trigger ...

Page 1459: ...0 SSCVA r rh r rh Field Bits Type Description SSCVA 10 0 rh Stop Watch Captured Slot Counter Value Channel A State of the slot counter for channel A when the stop watch event occurred Valid values are 0 to 2047 0H to 7FFH SSCVB 26 16 rh Stop Watch Captured Slot Counter Value Channel B State of the slot counter for channel B when the stop watch event occurred Valid values are 0 to 2047 0H to 7FFH 0...

Page 1460: ...or writing in DEFAULT_CONFIG state The configuration data is reset when DEFAULT_CONFIG state is entered from application reset To change POC state from DEFAULT_CONFIG to CONFIG state the Host has to apply CHI command CONFIG If the Host wants the Communication Controller to leave CONFIG state the Host has to proceed as described on Lock Register LCK on Page 20 35 SUC Configuration Register 1 SUCC1 ...

Page 1461: ...hange command applied while the Communication Controller is already in the requested POC state will be ignored 0000B COMMAND_NOT_ACCEPTED 0001B CONFIG 0010B READY 0011B WAKEUP 0100B RUN 0101B ALL_SLOTS 0110B HALT 0111B FREEZE 1000B SEND_MTS 1001B ALLOW_COLDSTART 1010B RESET_STATUS_INDICATORS 1011B MONITOR_MODE 1100B CLEAR_RAMS 1101B Reserved 1110B Reserved 1111B Reserved Reading SUCC1 CMD shows wh...

Page 1462: ...e 1B Key slot used to transmit SYNC Frames node is sync node CSA 15 11 rw Cold Start Attempts1 gColdStartAttempts Configures the maximum number of attempts that a cold starting node is permitted to try to start up the network without receiving any valid response from another node It can be modified in DEFAULT_CONFIG or CONFIG state only Must be identical in all nodes of a cluster Valid values are ...

Page 1463: ... or CONFIG state only In ALL slot mode the Communication Controller may transmit in all slots The bit can be written in DEFAULT_CONFIG or CONFIG state only The communication controller changes to ALL slot mode when the Host successfully applied the ALL_SLOTS command by writing SUCC1 CMD 0101B in POC states NORMAL_ACTIVE or NORMAL_PASSIVE The actual slot mode is monitored by CCSV SLM 0B ALL Slot Mo...

Page 1464: ...B disabled for MTS transmission 1B Channel B selected for MTS transmission CCHA 26 rw Connected to Channel A1 pChannels Configures whether the node is connected to channel A 0B Not connected to channel A 1B Node connected to channel A default after application reset CCHB 27 rw Connected to Channel B1 pChannels Configures whether the node is connected to channel B 0B Not connected to channel B 1B N...

Page 1465: ...TS Leave SINGLE slot mode after successful startup integration at the next end of cycle when called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE When called in any other state SUCC1 CMD will be reset to 0000B COMMAND_NOT_ACCEPTED HALT Set the halt request CCSV HRQ bit in the Communication Controller Status Vector register and go to POC state HALT at the next end of cycle when called in POC states...

Page 1466: ...Status register when called in DEFAULT_CONFIG or CONFIG state When called in any other state SUCC1 CMD will be reset to 0000B COMMAND_NOT_ACCEPTED MHDS CRAM is also set when the Communication Controller leaves application reset By setting MHDS CRAM all internal RAM blocks are initialized to zero Note that only the currently active IBF bank is cleared To clear the 2nd bank as well CUST1 IBF1PAG and...

Page 1467: ...ace Table 20 4 below references the CHI commands from the FlexRay Protocol Specification v2 1 section 2 2 1 1 Table 2 2 to the E Ray CHI command vector CMD Table 20 4 Reference to CHI Host command summary from FlexRay protocol specification CHI Command Where processed POC State CHI Command Vector CMD ALL_SLOT POC NORMAL_ACTIVE POC NORMAL_PASSIVE ALL_SLOTS ALLOW_COLDSTART All except POC DEFAULT_CON...

Page 1468: ...ription LT 20 0 rw Listen Timeout1 pdListenTimeout Configures wakeup startup listen timeout in Microticks The range for wakeup startup listen timeout pdListenTimeout is 1284 to 1283846 504H to 139706H Microticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only LTN 27 24 rw Listen Time out Noise1 gListenNoise 1 Configures the upper limit for startup and wakeup listen timeout in the ...

Page 1469: ...s the number of consecutive even odd cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE to NORMAL_PASSIVE state Must be identical in all nodes of a cluster Valid values are 1 to 15 1H to FH cycle pairs 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only WCF 7 4 rw Maximum Without Clock Correction Fatal1 gMaxWithoutClockCorrecti on Fatal Def...

Page 1470: ...0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NML r rw Field Bits Type Description NML 3 0 rw Network Management Vector Length1 gNetworkManagementVectorLength These bits configure the length of the NM Vector The configured length must be identical in all nodes of a cluster Valid values are 0 to 12 0H to CH bytes 1 This bit can be updated in DEFAULT_CONF...

Page 1471: ... Microticks 100ns at 10Mbps Must be identical in all nodes of a cluster Valid values are 3 to 15 3H to FH Bit Times CASM 10 4 rw Collision Avoidance Symbol Maximum1 gdCASRxLowMax Configures the upper limit of the acceptance window for a collision avoidance symbol CAS Valid values are 67 to 99 43H to 63H Most significant bit of CASM is hard wired to 1 and can not be modified SPP 13 12 rw Strobe Poi...

Page 1472: ...otick 50ns single sampled with fSCLK 4 gdSampleClockPeriod 50 ns 4 fSCLK pSamplesPerMicrotick 1 11B Reserved should not be used 2 5 Mbit s 1 Microtick 50 ns single sampled with fSCLK 4 gdSampleClockPeriod 50 ns 4 fSCLK pSamplesPerMicrotick 1 RXW 24 16 rw Wakeup Symbol Receive Window Length1 gdWakeupSymbolRxWindow Configures the number of Bit Times used by the node to test the duration of the recei...

Page 1473: ...mes 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only RXL 13 8 rw Wakeup Symbol Receive Low1 gdWakeupSymbolRxLow Configures the number of Bit Times used by the node to test the duration of the low phase of the received wakeup symbol Must be identical in all nodes of a cluster Valid values are 10 to 55 AH to 37H Bit Times TXI 23 16 rw Wakeup Symbol Transmit Idle1 gdWakeupSymbolTxIdle...

Page 1474: ... Data Length gPayloadLengthStatic 1 Configures the cluster wide payload length for all Frames sent in the static segment in double byte The payload length must be identical in all nodes of a cluster Valid values are 0 to 127 0 to 7FH 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only SLT 28 16 rw Start of Latest Transmit pLatestTx 1 Configures the maximum minislot value allowed befor...

Page 1475: ...ister 1 00A0H Reset Value 0000 0280H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 UT r rw Field Bits Type Description UT 19 0 rw Microtick per Cycle pMicroPerCycle 1 Configures the duration of the communication cycle in Microticks Valid values are 640 to 640000 280H to 9C400H Microticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only 0 31...

Page 1476: ... r rw Field Bits Type Description MPC 13 0 rw Macrotick Per Cycle gMacroPerCycle 1 Configures the duration of one communication cycle in Macroticks The cycle length must be identical in all nodes of a cluster Valid values are 10 to 16000 AH to 3E80H Macroticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only SNM 19 16 rw Sync Node Max gSyncNodeMax 1 Maximum number of Frames within ...

Page 1477: ...Initial Offset Channel B1 pMicroInitialOffset B Configures the number of Microticks between the actual time reference point on channel B and the subsequent Macrotick boundary of the secondary time reference point The parameter depends on pDelayCompensation B and therefore has to be set for each channel independently Valid values are 0 to 240 0H to F0H Microticks MIOA 22 16 rw Macrotick Initial Off...

Page 1478: ... gMacroPerCycle gdNIT 1 Configures the starting point of the Network Idle Time NIT at the end of the communication cycle expressed in terms of Macroticks from the beginning of the cycle The start of network idle time NIT is recognized if Macrotick gMacroPerCycle gdNIT 1 and the increment pulse of Macrotick is set Must be identical in all nodes of a cluster Valid values are 7 to 15997 7H to 3E7DH M...

Page 1479: ...ed Valid values are 0 to 200 0H to C8H Microticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only DCB 15 8 rw Delay Compensation Channel B1 pDelayCompensation B Used to compensate for reception delays on channel B This covers assumed propagation delay up to cPropagationDelayMax for Microticks in the range of 0 0125 to 0 05µs In practice the minimum of the propagation delays of all...

Page 1480: ...Field Bits Type Description ASR 10 0 rw Accepted Startup Range1 pdAcceptedStartupRange Number of Microticks constituting the expanded range of measured deviation for startup Frames during integration Valid values are 0 to 1875 0H to 753H Microticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only MOD 26 16 rw Maximum Oscillator Drift pdMaxDrift 1 Maximum drift offset between two no...

Page 1481: ...9 0 rw Static Slot Length gdStaticSlot 1 Configures the duration of a static slot in Macroticks The static slot length must be identical in all nodes of a cluster Valid values are 4 to 659 4H to 293H Macroticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only NSS 25 16 rw Number of Static Slots gNumberOfStaticSlots 1 Configures the number of static slots in a cycle At least 2 colds...

Page 1482: ... rw Field Bits Type Description MSL 5 0 rw Minislot Length gdMinislot 1 Configures the duration of a minislot in Macroticks The minislot length must be identical in all nodes of a cluster Valid values are 2 to 63 2H to 3FH Macroticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only NMS 28 16 rw Number of Minislots gNumberOfMinislots 1 Configures the number of minislots within the d...

Page 1483: ...static slots and symbol window Must be identical in all nodes of a cluster Valid values are 1 to 63 1H to 3FH Macroticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only MAPO 12 8 rw Minislot Action Point Offset1 gd Minislot Action Point Offset Configures the action point offset in Macroticks within the minislots of the dynamic segment Must be identical in all nodes of a cluster Va...

Page 1484: ...value to be applied by the internal clock synchronization algorithm absolute value The Communication Controller checks only the internal offset correction value against the maximum offset correction value Valid values are 5 to 15266 5H to 3BA2H Microticks 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only MRC 26 16 rw Maximum Rate Correction1 pRateCorrectionOut Holds the maximum perm...

Page 1485: ...lue 11B External offset correction value added to calculated offset correction value ERCC 9 8 rw External Rate Correction Control pExternRateControl By writing to ERCC the external rate correction is enabled as specified below Should be modified only outside network idle time NIT 00B No external rate correction 01B No external rate correction 10B External rate correction value subtracted from calc...

Page 1486: ...internal clock synchronization algorithm The value is subtracted added from to the calculated rate correction value The value is applied during network idle time NIT May be modified in DEFAULT_CONFIG or CONFIG state only Valid values are 0 to 7 Microticks 0 7 2 15 10 23 19 31 27 r Reserved Returns 0 if read should be written with 0 1 This bit can be updated in DEFAULT_CONFIG or CONFIG state only F...

Page 1487: ...ation Controller between two accesses non atomic read accesses The status vector may change faster than the Host can poll the status vector depending on fCLC_ERAY frequency Communication Controller Status Vector CCSV CCSV Communication Controller Status Vector 0100H Reset Value 0010 4000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PSL RCA WSV r rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 1488: ...peration of the POC in the wakeup path 010000B WAKEUP_STANDBY state 010001B WAKEUP_LISTEN state 010010B WAKEUP_SEND state 010011B WAKEUP_DETECT state 010100B 011111B are reserved Indicates the actual state of operation of the POC in the startup path 100000B STARTUP_PREPARE state 100001B COLDSTART_LISTEN state 100010B COLDSTART_COLLISION_RESOLUTION state 100011B COLDSTART_CONSISTENCY_CHECK state 10...

Page 1489: ... of the POC in states READY WAKEUP STARTUP NORMAL_ACTIVE and NORMAL_PASSIVE Default is SINGLE Changes to ALL depending on configuration bit SUCC1 TSM In NORMAL_ACTIVE or NORMAL_PASSIVE state the CHI command ALL_SLOTS will change the slot mode from SINGLE over ALL_PENDING to ALL Set to SINGLE in all other states 00B SINGLE 01B Reserved 10B ALL_PENDING 11B ALL CSNI 12 rh Coldstart Noise Indicator vP...

Page 1490: ... Header without coding violation on either channel in WAKEUP_LISTEN state 010B RECEIVED_WUP Set when the Communication Controller finishes wakeup due to the reception of a valid wakeup pattern on the configured wakeup channel in WAKEUP_LISTEN state 011B COLLISION_HEADER Set when the Communication Controller stops wakeup due to a detected collision during wakeup pattern transmission by receiving a ...

Page 1491: ...N command resets this counter to the maximum number of coldstart attempts as configured by SUCC1 CSA PSL 29 24 rh POC Status Log Status of CCSV POCS immediately before entering HALT state Set when entering HALT state Set to HALT when FREEZE command is applied during HALT state Reset to 000000B when leaving HALT state 0 11 10 15 31 30 rh Reserved Returns 0 if read should be written with 0 Field Bit...

Page 1492: ... offset correction error or missing rate correction error are active The Clock Correction Failed Counter is reset to 0 at the end of an odd communication cycle if neither the offset correction failed nor the rate correction failed errors are active The Clock Correction Failed Counter stops at 15 ERRM 7 6 rh Error Mode vPOC ErrorMode Indicates the actual error mode of the POC 00B ACTIVE green 01B P...

Page 1493: ... Counter Channel A vSlotCounter A Current slot counter value on channel A The value is incremented by the Communication Controller and reset at the start of a communication cycle Valid values are 0 to 2047 0H to 7FDH SCCB 26 16 rh Slot Counter Channel B vSlotCounter B Current slot counter value on channel B The value is incremented by the Communication Controller and reset at the start of a commun...

Page 1494: ...ield Bits Type Description MTV 13 0 rh Macrotick Value vMacrotick Current Macrotick value The value is incremented by the Communication Controller and reset at the start of a communication cycle Valid values are 0 to 16000 0H to 3E80H CCV 21 16 rh Cycle Counter Value vCycleCounter Current cycle counter value The value is incremented by the Communication Controller at the start of a communication c...

Page 1495: ...22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RCV r rh Field Bits Type Description RCV 11 0 rh Rate Correction Value vRateCorrection Rate correction value two s complement Calculated internal rate correction value before limitation If the RCV value exceeds the limits defined by GTUC10 MRC flag SFS RCLR is set to 1 0 31 12 r Reserved Returns 0 if read should be written with 0 ...

Page 1496: ...Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OCV r rh Field Bits Type Description OCV 18 0 rh Offset Correction Value vOffsetCorrection Offset correction value two s complement Calculated internal offset correction value before limitation If the OCV value exceeds the limits defined by GTUC10 MOC flag SFS OCLR is set to 1 0 31 19 r R...

Page 1497: ...eld is only valid if the channel A is assigned to the Communication Controller by SUCC1 CCHA VSAO 7 4 rh Valid SYNC Frames Channel A odd communication cycle Holds the number of valid SYNC Frames received on channel A in the odd communication cycle If transmission of SYNC Frames is enabled by SUCC1 TXSY the value is incremented by one The value is updated during the network idle time NIT of each od...

Page 1498: ...ction Limit Reached The Offset Correction Limit Reached flag signals to the Host that the offset correction value has exceeded its limit as defined by GTUC10 MOC The flag is updated by the Communication Controller at start of offset correction phase 0B Offset correction below limit 1B Offset correction limit reached MRCS 18 rh Missing Rate Correction Signal The Missing Rate Correction Flag signals...

Page 1499: ...D_MTS If both bits MTSA and MTSB are set to 1 an MTS symbol will be transmitted on both channels when requested by writing SUCC1 CMD 1000B SWNIT Symbol Window and Network Idle Time Status 0124H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SBN B SEN B SBN A SEN A MTS B MTS A TCS B SBS B SES B TCS A SBS A SES A r rh rh rh rh rh rh...

Page 1500: ...ConflictB 0B No transmission conflict detected 1B Transmission conflict in symbol window detected on channel B MTSA 6 rh MTS Received on Channel A vSS ValidMTSA 1 Media Access Test symbol received on channel A during the proceeding symbol window Updated by the Communication Controller for each channel at the end of the symbol window When this bit is set to 1 also interrupt flag SIR MTSA is set to ...

Page 1501: ...ted by the Communication Controller channel B at the end of the NIT 0B No syntax error detected 1B Syntax error during network idle time NIT detected on channel B SBNB 11 rh Slot Boundary Violation during network idle time NIT Channel B vSS BViolationB Updated by the Communication Controller channel B at the end of the NIT 0B No slot boundary violation detected 1B Slot boundary violation during ne...

Page 1502: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SBV B CIB CED B SED B VFR B 0 SBV A CIA CED A SED A VFR A r rwh rwh rwh rwh rwh r rwh rwh rwh rwh rwh Field Bits Type Description VFRA 0 rwh Valid Frame Received on Channel A vSS ValidFrameA One or more valid Frames were received on channel A in any static or dynamic slot during the observation period 0B No valid F...

Page 1503: ... or dynamic slots symbol window and network idle time NIT 0B No slot boundary violation observed 1B Slot boundary violation s observed on channel A VFRB 8 rwh Valid Frame Received on Channel B vSS ValidFrameB One or more valid Frames were received on channel B in any static or dynamic slot during the observation period 0B No valid Frame received 1B Valid Frame s received on channel B SEDB 9 rwh Sy...

Page 1504: ...slots that also contained any additional communication during the observation period i e one or more slots received a valid Frame AND had any combination of either syntax error OR content error OR slot boundary violation 0B No valid Frame s received in slots containing any additional communication 1B Valid Frame s received on channel B in slots containing any additional communication SBVB 12 rwh S...

Page 1505: ...11 10 9 8 7 6 5 4 3 2 1 0 RXE B RXE A 0 EID rh rh r rh Field Bits Type Description EID 9 0 rh Even Sync ID vsSyncIDListA B even SYNC Frame ID even communication cycle RXEA 14 rh Received Configured Even Sync ID on Channel A Signals that a SYNC Frame corresponding to the stored even sync ID was received on channel A or that the node is configured to be a sync node with key slot EID ESID1 only 0B SY...

Page 1506: ...TC1784 FlexRay Protocol Controller E Ray User s Manual 20 130 V1 1 2011 05 E Ray V3 13 0 13 10 31 16 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1507: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXO B RXO A 0 OID rh rh r rh Field Bits Type Description OID 9 0 rh Odd Sync ID vsSyncIDListA B odd SYNC Frame ID even communication cycle RXOA 14 rh Received Odd Sync ID on Channel A Signals that a SYNC Frame corresponding to the stored odd sync ID was received on channel A or that the node is configured to be a sync node with key slot OID OSID1 only 0B SYNC Frame ...

Page 1508: ...TC1784 FlexRay Protocol Controller E Ray User s Manual 20 132 V1 1 2011 05 E Ray V3 13 0 13 10 31 16 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1509: ...on cycle as long as the Communication Controller is either in NORMAL_ACTIVE or NORMAL_PASSIVE state NMVx bytes exceeding the configured Network Management NM vector length are not valid Table 20 5 below shows the assignment of the received payload s data byte to the Network Management vector NMVx x 1 3 Network Management Vector x 01ACH x 4 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20...

Page 1510: ... 23 22 21 20 19 18 17 16 0 SP LM SEC LCB r rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FFB FDB rw rw Field Bits Type Description FDB 7 0 rw First Dynamic Buffer May be modified in DEFAULT_CONFIG or CONFIG state only 00H No group of Message Buffers exclusively for the static segment configured 01H 7FH Message Buffers 0 to FDB 1 reserved for static segment 80H FFH No dynamic Message Buffers confi...

Page 1511: ...numbers FFB locked and transmission of Message Buffers for static segment with numbers FDB disabled 10B Reconfiguration of all Message Buffers locked 11B Reconfiguration of all Message Buffers locked and transmission of Message Buffers for static segment with numbers FDB disabled SPLM 26 rw SYNC Frame Payload Multiplex This bit is only evaluated if the node is configured as sync node SUCC1 TXSY 1 ...

Page 1512: ...is 254 byte The length of the Data Section may be configured differently for each Message Buffer For details see Message RAM on Page 20 244 In case two or more Message Buffers are assigned to slot 1 by use of cycle filtering all of them must be located either in the Static Buffers or at the beginning of the Static Dynamic Buffers section The payload length configured and the length of the Data Sec...

Page 1513: ...0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 RNF RSS CYF r rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FID CH r rw rw Field Bits Type Description CH 1 0 rw Channel Filter May be modified in DEFAULT_CONFIG or CONFIG state only 00B receive on both channels1 01B receive only on channel B 10B receive only on channel A 11B no reception FID 12 2 rw Frame ID Filter Determines the Frame ID...

Page 1514: ...Reject in Static Segment If this bit is set the FIFO is used only be used in dynamic segment May be modified in DEFAULT_CONFIG or CONFIG state only 0B FIFO also used in static segment 1B Reject messages for static segment RNF 24 rw Reject NULL Frames If this bit is set received NULL Frames are not stored in the FIFO May be modified in DEFAULT_CONFIG or CONFIG state only 0B NULL Frames are stored i...

Page 1515: ...jection filtering The FRFM register can be written during DEFAULT_CONFIG or CONFIG state only FRFM FIFO Rejection Filter Mask 0308H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MFID 0 r rw r Field Bits Type Description MFID 12 2 rw Mask Frame ID Filter May be modified in DEFAULT_CONFIG or CONFIG state only 0B Corresponding Frame ID ...

Page 1516: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CL r rw Field Bits Type Description CL 7 0 rw Critical Level When the receive FIFO fill level FSR RFFL is equal or greater than the critical level configured by CL the receive FIFO critical level flag FSR RFCL is set If CL is programmed to values 128 bit FSR RFCL is never set When FSR RFCL changes from 0 to 1 bit SIR RFCL is set to 1 and i...

Page 1517: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MBU 0 MBT r rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FMB CRA M MFM B FMB D ETB F2 ETB F1 EMR EOB F EIBF r rh rh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description EIBF 0 rwh ECC Error Input Buffer RAM 1 2 0B No error 1B Error occurred when reading Input Buffer RAM 1 or Input Buffer RAM 2 EOBF 1 rwh ECC Error Output Buffer RAM 1 2 0B No error 1...

Page 1518: ...data from Input Buffer or Transient Buffer A or Transient Buffer B to the Message Buffer referenced by MHDS FMB Value only valid when one of the flags MHDS EIBF MHDS EMR MHDS ETBF1 MHDS ETBF2 and flag MHDS FMBD is set Updated only after the Host has reset flag MHDS FMBD MBT 22 16 rh Message Buffer Transmitted Number of last successfully transmitted Message Buffer If the Message Buffer is configure...

Page 1519: ...TC1784 FlexRay Protocol Controller E Ray User s Manual 20 143 V1 1 2011 05 E Ray V3 13 0 15 23 31 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1520: ... 0 0 LDTB 0 LDTA r rh r rh Field Bits Type Description LDTA 10 0 rh Last Dynamic Transmission Channel A Value of vSlotCounter A at the time of the last Frame transmission on channel A in the dynamic segment of this node It is updated at the end of the dynamic segment and is reset to zero if no Frame was transmitted during the dynamic segment LDTB 26 16 rh Last Dynamic Transmission Channel B Value ...

Page 1521: ...oller when a received valid Frame data or NULL Frame depending on rejection mask was stored in the FIFO In addition service request flag SIR RFNE is set The bit is reset after the Host has read all message from the FIFO 0B Receive FIFO is empty 1B Receive FIFO is not empty RFCL 1 rh Receive FIFO Critical Level This flag is set when the receive FIFO fill level RFFL is equal or greater than the crit...

Page 1522: ...overwritten with the actual received message In addition service request flag EIR RFO is set The flag is cleared by the next FIFO read access issued by the Host 0B No receive FIFO overrun detected 1B A receive FIFO overrun has been detected RFFL 15 8 rh Receive FIFO Fill Level Number of FIFO buffers filled up with new data not yet read by the Host Maximum value is 128 0 7 3 31 16 r Reserved Return...

Page 1523: ...e 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WAH P TNS B TNS A TBF B TBF A FNF B FNF A SNU B SNU A r rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description SNUA 0 rwh Status Not Updated Channel A This flag is set by the Communication Controller when the Message Handler due to overload condition was not able to update a Message Bu...

Page 1524: ...cation Controller when a read or write access to Transient Buffer A requested by PRT A could not complete within the available time 0B No TBF A access failure 1B TBF A access failure TBFB 5 rwh Transient Buffer Access Failure B This flag is set by the Communication Controller when a read or write access to Transient Buffer B requested by PRT B could not complete within the available time 0B No Tra...

Page 1525: ...roller when the message handler tries to write message data into the Header Partition of the Message RAM due to faulty configuration of a Message Buffer The write attempt is not executed to protect the Header Partition from unintended write accesses 0B No write attempt to Header Partition 1B Write attempt to Header Partition 0 31 9 r Reserved Returns 0 if read should be written with 0 Field Bits T...

Page 1526: ... 23 22 21 20 19 18 17 16 TXR 31 TXR 30 TXR 29 TXR 28 TXR 27 TXR 26 TXR 25 TXR 24 TXR 23 TXR 22 TXR 21 TXR 20 TXR 19 TXR 18 TXR 17 TXR 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXR 15 TXR 14 TXR 13 TXR 12 TXR 11 TXR 10 TXR 9 TXR 8 TXR 7 TXR 6 TXR 5 TXR 4 TXR 3 TXR 2 TXR 1 TXR 0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description...

Page 1527: ... 22 21 20 19 18 17 16 TXR 63 TXR 62 TXR 61 TXR 60 TXR 59 TXR 58 TXR 57 TXR 56 TXR 55 TXR 54 TXR 53 TXR 52 TXR 51 TXR 50 TXR 49 TXR 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXR 47 TXR 46 TXR 45 TXR 44 TXR 43 TXR 42 TXR 41 TXR 40 TXR 39 TXR 38 TXR 37 TXR 36 TXR 35 TXR 34 TXR 33 TXR 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Desc...

Page 1528: ... 22 21 20 19 18 17 16 TXR 95 TXR 94 TXR 93 TXR 92 TXR 91 TXR 90 TXR 89 TXR 88 TXR 87 TXR 86 TXR 85 TXR 84 TXR 83 TXR 82 TXR 81 TXR 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXR 79 TXR 78 TXR 77 TXR 76 TXR 75 TXR 74 TXR 73 TXR 72 TXR 71 TXR 70 TXR 69 TXR 68 TXR 67 TXR 66 TXR 65 TXR 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Desc...

Page 1529: ...8 17 16 TXR 127 TXR 126 TXR 125 TXR 124 TXR 123 TXR 122 TXR 121 TXR 120 TXR 119 TXR 118 TXR 117 TXR 116 TXR 115 TXR 114 TXR 113 TXR 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXR 111 TXR 110 TXR 109 TXR 108 TXR 107 TXR 106 TXR 105 TXR 104 TXR 103 TXR 102 TXR 101 TXR 100 TXR 99 TXR 98 TXR 97 TXR 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field ...

Page 1530: ...25 ND 24 ND 23 ND 22 ND 21 ND 20 ND 19 ND 18 ND 17 ND 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND 15 ND 14 ND 13 ND 12 ND 11 ND 10 ND9 ND8 ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description NDn n 0 31 n rh New Data n n 0 31 The flags are set when a valid received Data Frame matches the Message ...

Page 1531: ...55 ND 54 ND 53 ND 52 ND 51 ND 50 ND 49 ND 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND 47 ND 46 ND 45 ND 44 ND 43 ND 42 ND 41 ND 40 ND 39 ND 38 ND 37 ND 36 ND 35 ND 34 ND 33 ND 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description NDn n 32 63 n 32 rh New Data n n 32 63 The flags are set when a valid received Data Frame matches...

Page 1532: ...87 ND 86 ND 85 ND 84 ND 83 ND 82 ND 81 ND 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND 79 ND 78 ND 77 ND 76 ND 75 ND 74 ND 73 ND 72 ND 71 ND 70 ND 69 ND 68 ND 67 ND 66 ND 65 ND 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description NDn n 64 95 n 64 rh New Data n n 64 95 The flags are set when a valid received Data Frame matches...

Page 1533: ... 118 ND 117 ND 116 ND 115 ND 114 ND 113 ND 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND 111 ND 110 ND 109 ND 108 ND 107 ND 106 ND 105 ND 104 ND 103 ND 102 ND 101 ND 100 ND 99 ND 98 ND 97 ND 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description NDn n 96 127 n 96 rh New Data n n 96 127 The flags are set when a valid received Da...

Page 1534: ...BC 23 MBC 22 MBC 21 MBC 20 MBC 19 MBC 18 MBC 17 MBC 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBC 15 MBC 14 MBC 13 MBC 12 MBC 11 MBC 10 MBC 9 MBC 8 MBC 7 MBC 6 MBC 5 MBC 4 MBC 3 MBC 2 MBC 1 MBC 0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description MBCn n 0 31 n rh Message Buffer Status Changed n n 0 31 An MBC flags is set whene...

Page 1535: ...C 54 MBC 53 MBC 52 MBC 51 MBC 50 MBC 49 MBC 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBC 47 MBC 46 MBC 45 MBC 44 MBC 43 MBC 42 MBC 41 MBC 40 MBC 39 MBC 38 MBC 37 MBC 36 MBC 35 MBC 34 MBC 33 MBC 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description MBCn n 32 63 n 32 rh Message Buffer Status Changed n n 32 63 An MBC flags is se...

Page 1536: ...C 86 MBC 85 MBC 84 MBC 83 MBC 82 MBC 81 MBC 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBC 79 MBC 78 MBC 77 MBC 76 MBC 75 MBC 74 MBC 73 MBC 72 MBC 71 MBC 70 MBC 69 MBC 68 MBC 67 MBC 66 MBC 65 MBC 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description MBCn n 64 95 n 64 rh Message Buffer Status Changed n n 64 95 An MBC flags is se...

Page 1537: ...MBC 117 MBC 116 MBC 115 MBC 114 MBC 113 MBC 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBC 111 MBC 110 MBC 109 MBC 108 MBC 107 MBC 106 MBC 105 MBC 104 MBC 103 MBC 102 MBC 101 MBC 100 MBC 99 MBC 98 MBC 97 MBC 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description MBCn n 96 127 n 96 rh Message Buffer Status Changed n n 96 127 An ...

Page 1538: ... DAY r r r r r Field Bits Type Description DAY 7 0 r Design Time Stamp Day Two digits BCD coded MON 15 8 r Design Time Stamp Month Two digits BCD coded YEAR 19 16 r Design Time Stamp Year One digit BCD coded SUBSTEP 23 20 r Sub Step of Core Release One digits BCD coded 0H Alpha pre Beta pre Beta update pre Beta2 pre Beta2 update Beta Beta2 Revision 1 0 0 1H Beta_ct Beta ct fix1 Revision 1 0 1 2H R...

Page 1539: ... Release Step Sub Step Name Release Date 0 1 0 Alpha 0 2 0 pre Beta 0 3 0 pre Beta update 0 4 0 pre Beta2 0 5 0 pre Beta2 update 0 6 0 Beta 0 6 1 Beta ct fix1 14 10 2005 0 6 2 Beta ct fix2 14 12 2005 0 7 0 Beta2 03 02 2006 0 7 1 Beta2ct 24 03 2006 0 7 2 Revision 1 0RC1 07 04 2006 1 0 0 Release 1 0 0 19 05 2006 1 0 1 Release 1 0 1 2006 1 0 2 Release 1 0 2 31 10 2007 Field Bits Type Description ...

Page 1540: ...Message RAM from the Input Buffer the Message Buffer Status as described in Message Buffer Status MBS on Page 20 182 is automatically reset to zero The Header Sections of Message Buffers belonging to the receive FIFO can only be re configured when the Communication Controller is in DEFAULT_CONFIG or CONFIG state For those Message Buffers only the payload length configured and the data pointer need...

Page 1541: ...ed up by one 32 bit access OR two consecutive 16 bit accesses OR four consecutive 8 bit accesses before the transfer from the Input Buffer to the Message RAM is started by writing the number of the target Message Buffer in the Message RAM to the Input Buffer Command Request register If a 32 bit word of the Input Buffer has been filled with less then two consecutive 16 bit accesses OR four consecut...

Page 1542: ...set used for cycle counter filtering For details about the configuration of the cycle code see Section 20 6 7 3 CHA 24 rw Channel Filter Control A The channel filtering field A associated with the buffer serves of channel A as a filter for receive buffers and as a control field for transmit buffers CHB 25 rw Channel Filter Control B The channel filtering field B associated with the buffer serves o...

Page 1543: ...ffer the first two byte of the Payload Segment may be used for message ID filtering by the receiver Message ID filtering of received FlexRay Frames is not supported by the E Ray module but can be done by the Host 0B Payload Preamble Indicator not set 1B Payload Preamble Indicator set TXM 28 rw Transmission Mode This bit is used to select the transmission mode see Transmit Buffers on Page 20 222 0B...

Page 1544: ...d from 11 1 If a Message Buffer is configured for the dynamic segment and both bits of the channel filtering field are set to 1 no Frames are transmitted resp received Frames are ignored same function as CHA CHB 0 11 Both Channels static segment only Channel A or B store first semantically valid Frame static segment only 1 0 Channel A Channel A 0 1 Channel B Channel B 0 0 No Transmission Ignore Fr...

Page 1545: ...he Header CRC the payload length of the Frame send on the bus has to be considered In static segment the payload length of all Frames is configured by MHDC SFDL PLC 22 16 rw Payload Length Configured Length of Data Section number of 2 byte words as configured by the Host During static segment the static Frame payload length as configured by MHDC SFDL in the MHD Configuration Register defines the p...

Page 1546: ...3 0508H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DP r rw Field Bits Type Description DP 10 0 rw Data Pointer Pointer to the first 32 bit word of the Data Section of the addressed Message Buffer in the Message RAM 0 31 11 r Reserved Returns 0 if read should be written with 0 ...

Page 1547: ...Field Bits Type Description LHSH 0 rwh Load Header Section Host 0B Header Section is not updated 1B Header Section selected for transfer from Input Buffer to the Message RAM LDSH 1 rwh Load Data Section Host 0B Data Section is not updated 1B Data Section selected for transfer from Input Buffer to the Message RAM STXRH 2 rwh Set Transmission Request Host If this bit is set to 1 the Transmission Req...

Page 1548: ...mission Request Shadow If this bit is set to 1 the Transmission Request flag TXRQ1 TXRn n 0 31 to TXRQ4 TXRn n 0 31 for the selected Message Buffer is set in the Transmission Request Registers to release the Message Buffer for transmission In single shot mode the flag is cleared by the Communication Controller after transmission has completed TXRQ1 TXRn n 0 31 to TXRQ4 TXRn n 0 31 are evaluated fo...

Page 1549: ...s completed the IBSYS bit is set back to 0 and the next transfer to the Message RAM may be started by the Host by writing the respective target Message Buffer number to IBRH If a write access to IBRH occurs while IBSYS is 1 IBSYH is set to 1 After completion of the ongoing data transfer from IBF Shadow to the Message RAM IBF Host and IBF Shadow are swapped IBSYH is reset to 0 IBSYS remains set to ...

Page 1550: ...w and Message RAM in progress IBRS 22 16 rh Input Buffer Request Shadow Number of the target Message Buffer actually updated lately updated Valid values are 00H to 7FH 0 127 IBSYS 31 rh Input Buffer Busy Shadow Set to 1 after writing IBRH When the transfer between IBF Shadow and the Message RAM has completed IBSYS is set back to 0 0B Transfer between IBF Shadow and Message RAM completed 1B Transfe...

Page 1551: ... RDDSnn nn 01 64 holds the data words read from the Data Section of the addressed Message Buffer The data words are read from the Message RAM in reception order from DW1 byte0 byte1 to DWPL PL number of data words as defined by the Payload Length Note DW127 is located on RDDS64 MDW In this case RDDS64 MDW is unused no valid data The Output Buffer RAMs are initialized to zero when leaving applicati...

Page 1552: ...on 1 0700H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MBI TXM PPIT CFG CHB CHA 0 CYC r rh rh rh rh rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FID r rh Field Bits Type Description FID 10 0 rh Frame ID CYC 22 16 rh Cycle Code CHA 24 rh Channel Filter Control A CHB 25 rh Channel Filter Control B CFG 26 rh Message Buffer Direction Configuration Bit PPIT 27 rh Payl...

Page 1553: ...d from 11 1 If a Message Buffer is configured for the dynamic segment and both bits of the channel filtering field are set to 1 no Frames are transmitted resp received Frames are ignored same function as CHA CHB 0 11 Both Channels static segment only Channel A or B store first semantically valid Frame static segment only 1 0 Channel A Channel A 0 1 Channel B Channel B 0 0 No Transmission Ignore Fr...

Page 1554: ...18 17 16 0 PLR 0 PLC r rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CRC r rh Field Bits Type Description CRC 10 0 rh Header CRC vRF Header HeaderCRC Receive Buffer Configuration not required Header CRC updated from receive Data Frames Transmit Buffer Header CRC calculated and configured by the Host PLC 22 16 rh Payload Length Configured Length of Data Section number of 2 byte words as configure...

Page 1555: ...IFO PLR is also updated from received NULL Frames When a message is stored into a Message Buffer the following behavior with respect to payload length received and payload length configured is implemented PLR PLC The payload data stored in the Message Buffer is truncated to the payload length configured for even PLC or else truncated to PLC 1 PLR PLC The received payload data is stored into the Me...

Page 1556: ... Channel Indicates the channel from which the received Data Frame was taken to update the respective receive buffer 0B Frame received on channel B 1B Frame received on channel A SFI 25 rh Startup Frame Indicator vRF Header SuFIndicator A Startup Frame is marked by the Startup Frame indicator 0B The received Frame is not a startup Frame 1B The received Frame is a startup Frame SYN 26 rh SYNC Frame ...

Page 1557: ...ayload Segment of the received Frame 0B The Payload Segment of the received Frame does not contain a Network Management vector nor a message ID 1B Static segment Network Management vector in the first part of the payload Dynamic segment Message ID in the first part of the payload RES 29 rh Reserved Bit vRF Header Reserved Reflects the state of the received reserved bit The reserved bit is transmit...

Page 1558: ...ails about receive transmit filtering see Filtering and Masking on Page 20 218 Transmit Process on Page 20 222 and Receive Process on Page 20 225 Whenever the Message Handler changes one of the flags VFRA VFRB SEOA SEOB CEOA CEOB SVOA SVOB TCIA TCIB ESA ESB MLST FTA FTB the respective Message Buffer s MBC flag in registers MBSC1 to MBSC4 is set MBS Message Buffer Status 070CH Reset Value 0000 0000...

Page 1559: ...bserved in the assigned slot on channel B 0B No content error observed on channel B 1B Content error observed on channel B SVOA 6 rh Slot Boundary Violation Observed on Channel A vSS BViolationA A slot boundary violation channel active at the start or at the end of the assigned slot was observed on channel A 0B No slot boundary violation observed on channel A 1B Slot boundary violation observed on...

Page 1560: ...ivity detected in the assigned slot on channel B MLST 12 rh Message Lost The flag is set in case the Host did not read the message before the Message Buffer was updated from a received Data Frame Not affected by reception of NULL Frames except for Message Buffers belonging to the receive FIFO The flag is reset by a Host write to the Message Buffer via IBF or when a new message is stored into the M...

Page 1561: ...IS is updated from both valid data and NULL Frames If no valid Frame was received the previous value is maintained For transmit buffers the flags have no meaning and should be ignored SFIS 25 rh Startup Frame Indicator Status vRF Header SuFIndicator A Startup Frame is marked by the Startup Frame indicator 0B No Startup Frame received 1B The received Frame is a startup Frame Note For receive buffer...

Page 1562: ...he received Frame does not contain a Network Management vector or a message ID 1B Network Management vector at the beginning of the payload Dynamic Segment 0B The Payload Segment of the received Frame does not contain a Network Management vector or a message ID 1B Message ID at the beginning of the payload Note For receive buffers CFG 0 the PPIS is updated from both valid data and NULL Frames If n...

Page 1563: ...0 19 18 17 16 0 RD SH RH SH r rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RD SS RH SS r rwh rwh Field Bits Type Description RHSS 0 rwh Read Header Section Shadow 0B Header Section is not read 1B Header Section selected for transfer from Message RAM to Output Buffer RDSS 1 rwh Read Data Section Shadow 0B Data Section is not read 1B Data Section selected for transfer from Message RAM to Output Buf...

Page 1564: ...d the Message Buffer status changed flag MBCn n 0 31 to MBCn n 96 127 of the selected Message Buffer in the Message Buffer Changed MBSC1 to MBSC4 registers is cleared After the transfer of the Data Section from the Message RAM to OBF Shadow has completed the New Data flag NDn n 0 31 to NDn n 96 127 of the selected Message Buffer in the New Data NDAT1 to NDAT4 registers is cleared ...

Page 1565: ...sfer between the Message RAM and OBF Shadow has completed this is signalled by clearing OBCR OBSYS By setting OBCR VIEW while OBCR OBSYS is 0 OBF Host and OBF Shadow are swapped When Output Buffer Host and Output Buffer Shadow are swapped also mask bits OBCM RDSH and OBCM RHSH are swapped with bits OBCM RDSS and OBCM RHSS to keep them attached to the respective Output Buffer transfer Now the Host ...

Page 1566: ...is register the Message Handler transfers the Message Buffer addressed by the GET Index Register GIDX FIFO Function on Page 20 226 to OBF Shadow VIEW 8 rw View Shadow Buffer Toggles between OBF Shadow and OBF Host Only writeable while OBCR OBSYS 0 0B No action 1B Swap OBF Shadow and OBF Host REQ 9 rw Request Message RAM Transfer Requests transfer of Message Buffer addressed by OBCR OBRS from Messa...

Page 1567: ...ssage Buffer currently accessible by the Host via RDHS1 to RDHS3 MBS and RDDSnn nn 01 64 By setting OBCR VIEW OBF Shadow and OBF Host are swapped and the transferred Message Buffer is accessible by the Host Valid values are 00H to 7FH 01 to 27 0 7 14 10 31 23 r Reserved Returns 0 if read should be written with 0 Field Bits Type Description ...

Page 1568: ...lements Static Segment Dynamic Segment Symbol Window Network Idle Time NIT Static segment dynamic segment and symbol window form the Network Communication Time NCT For each communication channel the slot counter starts at 1 and counts up until the end of the dynamic segment is reached Both channels share the same arbitration grid which means that they use the same synchronized Macrotick Figure 20 ...

Page 1569: ...ccess test symbol MTS may be transmitted per channel MTS symbols are send in NORMAL_ACTIVE state to test the bus guardian The symbol window is characterized by the following features Send single symbol Transmission of the MTS symbol starts at the symbol windows action point Parameters Symbol Window Action Point Offset GTUC09 APO same as for static slots Network Idle Time Start GTUC04 NIT 20 6 1 4 ...

Page 1570: ...SL and GTUC08 NMS The dynamic segment offset is If gdActionPointOffset gdMinislotActionPointOffset dynamic segment offset 0 MT Else if gdActionPointOffset gdMinislotActionPointOffset dynamic segment offset gdActionPointOffset gdMinislotActionPointOffset The network idle time NIT starts with Macrotick k 1 and ends with the last Macrotick of cycle m 1 It has to be configured by setting GTUC04 NIT k ...

Page 1571: ...g the timing of received SYNC Frames from other nodes 20 6 3 1 Global Time Activities in a FlexRay node including communication are based on the concept of a global time even though each individual node maintains its own view of it It is the clock synchronization mechanism that differentiates the FlexRay cluster from other node collections with independent clock mechanisms The global time is a vec...

Page 1572: ...valid on both channels two channel cluster is measured The calculation of correction terms is done during network idle time NIT offset every cycle rate odd cycle by using a FTA FTM algorithm For details see FlexRay protocol specification v2 1 chapter 8 Offset phase Correction Only deviation values measured and stored in the current cycle used For a two channel node the smaller value will be taken ...

Page 1573: ...one during network idle time NIT offset every cycle rate odd cycle by using a FTA FTM algorithm For details see FlexRay protocol specification v2 1 chapter 8 SYNC Frame Transmission SYNC Frame transmission is only possible from buffer 0 and 1 Message Buffer 1 may be used for SYNC Frame transmission in case that SYNC Frames should have different payloads on the two channels In this case bit MRC SPL...

Page 1574: ...ion Register 3 Table 20 10 Error Modes of the POC Degradation Model Error Mode Activity ACTIVE green Full operation State NORMAL_ACTIVE The Communication Controller is fully synchronized and supports the cluster wide clock synchronization The host is informed of any error condition s or status change by interrupt if enabled or by reading the error and status interrupt flags from registers EIR and ...

Page 1575: ...tion Controller enters READY state or when NORMAL_ACTIVE state is entered 20 6 4 2 Passive to Active Counter The passive to active counter controls the transition of the POC from NORMAL_PASSIVE to NORMAL_ACTIVE state SUCC1 PTA in the SUC Configuration Register 1 defines the number of consecutive even odd cycle pairs that must have valid clock correction terms before the Communication Controller is...

Page 1576: ... E Ray User s Manual 20 200 V1 1 2011 05 E Ray V3 13 command triggers the entry of the HALT state immediately regardless of the actual POC state The POC state from which the transition to HALT state took place can be read from CCSV PSL ...

Page 1577: ...and Vector SUCC1 CMD located in the SUC Configuration Register 1 Figure 20 6 Overall State Diagram of E Ray Communication Controller The Communication Controller exits from all states to HALT state after application of the FREEZE command SUCC1 CMD 0111B T1 T3 T4 T5 T8 T9 T6 T7 HW Reset Power On READY WAKEUP HALT MONITOR_ CONFIG NORMAL_ NORMAL_ STARTUP ACTIVE PASSIVE MODE T10 T11 T12 T13 T14 T15 T1...

Page 1578: ...SUCC1 CMD 0001B READY CONFIG 7 Command WAKEUP SUCC1 CMD 0011B READY WAKEUP 8 Complete non aborted transmission of wakeup pattern OR received WUP OR received Frame Header OR command READY SUCC1 CMD 0010B WAKEUP READY 9 Command RUN SUCC1 CMD 0100B READY STARTUP 10 Successful startup STARTUP NORMAL_ACTIVE 11 Clock Correction Failed counter reached Maximum Without Clock Correction Passive limit config...

Page 1579: ...ters are accessible and the pins to the physical layer are in their inactive state This state is used to initialize the Communication Controller configuration 14 Clock Correction Failed counter reached Maximum Without Clock Correction Fatal limit configured by WCF in SUC Configuration Register 3 AND bit HCSE in the SUC Configuration Register 1 set to 1 OR command HALT SUCC1 CMD 0110B NORMAL_ACTIVE...

Page 1580: ...essage RAM transfers have finished before turning off the clocks 20 6 5 3 MONITOR_MODE After unlocking CONFIG state and writing SUCC1 CMD 0011B the Communication Controller enters MONITOR_MODE In this mode the Communication Controller is able to receive FlexRay Frames and to detect wakeup pattern The temporal integrity of received Frames is not checked and therefore cycle counter filtering is not ...

Page 1581: ...OC from READY to STARTUP state 20 6 5 5 WAKEUP State The description below is intended to help configuring wakeup for the E Ray IP module A detailed description of the wakeup procedure together with the respective SDL diagrams can be found in the FlexRay protocol specification v2 1 section 7 1 The Communication Controller enters this state When exiting from READY state by writing SUCC1 CMD 0011B W...

Page 1582: ...e wakeup procedure enables single channel devices in a two channel system to trigger the wakeup by only transmitting the wakeup pattern on the single channel to which they are connected Any coldstart node that deems a system startup necessary will then wake the remaining channel before initiating communication startup The wakeup procedure tolerates any number of nodes simultaneously trying to wake...

Page 1583: ...and WAKEUP triggers wakeup FSM to transit to WAKEUP_LISTEN state WAKEUP_ STANDBY WAKEUP_ LISTEN 2 Received WUP on wakeup channel selected by flag SUCC1 WUCS in the SUC Configuration Register 1 OR Frame Header on either available channel WAKEUP_ LISTEN WAKEUP_ STANDBY 3 Timer event WAKEUP_ LISTEN WAKEUP_ SEND 4 Complete non aborted transmission of wakeup pattern WAKEUP_ SEND WAKEUP_ STANDBY Tenter ...

Page 1584: ...ster 2 Either the detection of a wakeup pattern indicating a wakeup attempt by another node or the reception of a Frame Header indication existing communication causes the direct transition to READY state Otherwise WAKEUP_DETECT is left after expiration of listen time out in this case the reason for wakeup collision is unknown The Host has to be aware of possible failures of the wakeup and act acc...

Page 1585: ...wakeup and configure themselves Coldstart node wait for WUP on the other channel In a dual channel cluster wait for WUP on the other channel Reset coldstart inhibit flag CCSV CSI by writing SUCC1 CMD 1001B ALLOW_COLDSTART command Reset Coldstart Inhibit flag CCSV CSI in the CCSV register by writing SUCC1 CMD 1001B ALLOW_COLDSTART command coldstart node only Command Communication Controller to ente...

Page 1586: ...n be found in the FlexRay protocol specification v2 1 section 7 2 Any node entering STARTUP state that has coldstart capability should assure that both channels attached have been awakened before initiating coldstart It cannot be assumed that all nodes and stars need the same amount of time to become completely awake and to be configured Since at least two nodes are necessary to start up the clust...

Page 1587: ...to be coldstart nodes In clusters consisting of two nodes both nodes must be coldstart nodes At least two fault free coldstart nodes are necessary for the cluster to startup Each Startup Frame must also be a SYNC Frame therefore each coldstart node will also be a sync node The number of coldstart attempts is configured by SUCC1 CSA in the SUC Configuration Register 1 A non coldstart node requires ...

Page 1588: ...ning cluster or to transmit startup Frames after another coldstart node started the initialization of the cluster communication The coldstart inhibit bit CCSV CSI is set whenever the POC enters READY state The bit has to be cleared under control of the Host by CHI command ALLOW_COLDSTART SUCC1 CMD 1001B ERAY_STARTUP READY STARTUP_ PREPARE ABORT_ STARTUP INTEGRATION_ LISTEN COLDSTART_ LISTEN COLDST...

Page 1589: ...er is configured by programming SUCC2 LT pdListenTimeout in the SUC Configuration Register 2 The startup timer is restarted upon Entering the COLDSTART_LISTEN state Both channels reaching idle state while in COLDSTART_LISTEN state The startup timer is stopped If communication channel activity is detected on one of the configured channels while the node is in the COLDSTART_LISTEN state When the COL...

Page 1590: ...cur that several nodes simultaneously transmit the CAS symbol and enter the coldstart path This situation is resolved during the first four cycles after CAS transmission As soon as a node that initiates a coldstart attempt receives a CAS symbol or a Frame Header during these four cycles it re enters the COLDSTART_LISTEN state Thereby only one node remains in this path In cycle four other coldstart...

Page 1591: ...their schedules agree to each other If for the following three cycles the clock correction does not signal errors and at least one other coldstart node is visible the node leaves COLDSTART_JOIN state and enters NORMAL_ACTIVE state Thereby it leaves STARTUP at least one cycle after the node that initiated the coldstart Path of Non coldstart Node When a non coldstart node enters the INTEGRATION_LIST...

Page 1592: ...es as well as the SYNC Frames Rate and offset measurement is started in all even cycles even odd cycle pairs required In NORMAL_ACTIVE state the Communication Controller supports regular communication functions The Communication Controller performs transmissions and reception on the FlexRay bus as configured Clock synchronization is running The Host interface is operational The Communication Contr...

Page 1593: ...y writing SUCC1 CMD 0110B HALT command while the Communication Controller is in NORMAL_ACTIVE or NORMAL_PASSIVE state By writing SUCC1 CMD 0111B FREEZE command from all states When exiting from NORMAL_ACTIVE state because the clock correction failed counter reached the maximum without clock correction fatal limit When exiting from NORMAL_PASSIVE state because the clock correction failed counter re...

Page 1594: ...WRHS1 PPIT In addition the Host has to write the Network Management NM information to the Data Section of the respective transmit buffer The evaluation of the Network Management NM vector has to be done by the application running on the Host Note In case a Message Buffer is configured for transmission reception of Network Management Frames the payload length configured in Header 2 of that Message ...

Page 1595: ...here the received Frame ID matches the configured Frame ID provided channel ID and cycle counter criteria are also met Transmit Buffers For transmit buffers the configured Frame ID is used to determine the appropriate slot for message transmission The Frame will be transmitted in the time slot corresponding to the configured Frame ID provided channel ID and cycle counter criteria are also met 20 6...

Page 1596: ... The content of the buffer is transmitted only on the channels specified in the channel filtering field when the Frame ID filtering and cycle counter filtering criteria are also met Only in static segment a transmit buffer may be setup for transmission on both channels CHA and CHB set After transmission has completed and if bit WRHS1 MBI in the Header Section of the respective Message Buffer is se...

Page 1597: ...on filter and one rejection filter mask available The FIFO rejection filter consists of 20 bits for Channel 2 bits Frame ID 11 bits and Cycle Code 7 bits Rejection filter and rejection filter mask can be configured in Table 20 14 Definition of Cycle Set Cycle Code Matching Cycle Counter Values 000000xB all Cycles 000001cB every second Cycle at Cycle Count mod2 c 00001ccB every fourth Cycle at Cycl...

Page 1598: ...e with the highest priority lowest Frame ID is selected next Only Frame ID s which are higher than the largest static Frame ID are allowed for the dynamic segment In the dynamic segment different slot counter sequences are possible concurrent sending of different Frame ID s on both channels Therefore pending messages are selected according to their Frame ID and their channel configuration bit The ...

Page 1599: ...he Data Section of the Message Buffer see Section 20 6 6 The payload length field configures the data payload length in 2 byte words If the configured payload length of a static transmit buffer is shorter than the payload length configured for the static segment by SFDL in the Message Handler Configuration Register 1 the Communication Controller generates padding byte to ensure that Frames have pr...

Page 1600: ...g the Transmission Request flag TXR again The Host can check the actual state of the TXR flags of all Message Buffers by reading the Transmission Request registers After successful transmission if bit WRHS1 MBI in the Header Section of the respective Message Buffer is set the transmit service request flag in the Status Service Request Register is set TXI 1 If enabled an service request is generate...

Page 1601: ... longer than the value programmed by PLC in the Header Section of the respective Message Buffer the data field stored in the Message Buffer is truncated to that length If no Frame a NULL Frame or a corrupted Frame is received in a slot the Data Section of the Message Buffer configured for this slot is not updated In this case only the flags in the Message Buffer Status register are updated to sign...

Page 1602: ...FIFO Message Buffer are overwritten with Frame ID payload length receive cycle count and the status from the received message and can be read by the Host for message identification Bit RFNE in the Status Service Request Register shows that the FIFO is not empty bit RFF in the Status Service Request Register is set when the last available Message Buffer belonging to the FIFO is written bit RFO in t...

Page 1603: ...tored in the FIFO The FIFO Rejection Filter Mask register FRFM specifies which bits of the Frame ID filter in the FIFO Rejection Filter register are marked don t care for rejection filtering 20 6 10 2 Configuration of the FIFO For all Message Buffers belonging to the FIFO the data pointer to the first 32 bit word of the Data Section of the respective Message Buffer in the Message RAM has to be con...

Page 1604: ...rnal RAM s are 32 bit accesses Access to the Message Buffers stored in the Message RAM is done under control of the Message Handler state machine This avoids conflicts between accesses of the two protocol controllers and the Host to the Message RAM Frame IDs of Message Buffers assigned to the static segment have to be in the range from 1 to NSS as configured in the GTU Configuration Register 7 Fra...

Page 1605: ...een IBF OBF and Message RAM Figure 20 11 Host Access to Message RAM Data Transfer from Input Buffer to Message RAM To configure update a Message Buffer in the Message RAM the Host has to write the data to WRDSnn nn 01 64 and the Header to WRHS1 WRHS2 WRHS3 Two sets of WRDSnn nn 01 64 are available in parallel and selected by CUST1 IBF1PAGand CUST1 IBF2PAG CUST1 IBFS shows which Input Buffer is cur...

Page 1606: ...ontents of IBF Shadow to the Message Buffer in the Message RAM selected by IBRS While the Message Handler transfers the data from IBF Shadow to the target Message Buffer in the Message RAM the Host may write the next message to IBF Host After the transfer between IBF Shadow and the Message RAM has completed the IBSYS bit is set back to 0 and the next transfer to the Message RAM may be started by t...

Page 1607: ... 01 64 RDHS1 RDHS2 RDHS2 and MBS Table 20 16 Assignment of Input Buffer Command Mask Bit Pos Access Bit Function 18 rh STXRS Set Transmission Request Shadow 17 rh LDSS Load Data Section Shadow 16 rh LHSS Load Header Section Shadow 2 rw STXRH Set Transmission Request Host 1 rw LDSH Load Data Section Host 0 rw LHSH Load Header Section Host Table 20 17 Assignment of Input Buffer Command Request Bit P...

Page 1608: ...rom the Message RAM to OBF Shadow is started After the transfer between the Message RAM and OBF Shadow has completed the OBCR OBSYS bit is set back to 0 Bits OBCR REQ and OBCR VIEW can only be set to 1 while OBCR OBSYS is 0 Figure 20 15 Swapping of OBCM and OBCR Bit OBF Host and OBF Shadow are swapped by setting bit OBCR VIEW to 1 while bit OBCR OBSYS is 0 see Figure 20 14 In addition bits OBCR OB...

Page 1609: ...n available for Host access 16 rh RHSH Header Section available for Host access 1 rw RDSS Read Data Section Shadow 0 rw RHSS Read Header Section Shadow Table 20 19 Assignment of Output Buffer Command Request Bit Pos Access Bit Function 22 16 rh OBRH OBF Request Host number of Message Buffer available for Host access 15 rh OBSYS OBF Busy Shadow signals ongoing transfer from Message RAM to OBF Shado...

Page 1610: ...pendent number of time steps to transfer the data section The internal data busses have a width of 32 bits Thereby it is possible to transfer two 2 byte words in one time step If the payload consists of an odd number of 2 byte words the last time step of the data section contains only 16 bit of valid data If the Payload Length PL is e g 7 the data section consists of 4 time steps The maximum lengt...

Page 1611: ...rch next TX RX Message Buffer CHB Thereby the time step length can vary between one and three fCLC_ERAYperiods Under certain conditions it is possible that a transfer is stopped or interrupted for a number of time steps until it is continued When a IB F MBF is started short after a TBF MBF or SS MBF the transfer from IBF has to wait until the setup time of the internal transfer has finished see Fi...

Page 1612: ...nternal transfer The number of 4 byte words varies from 4 Header Section only to 68 Header maximum Data Section plus a short setup time to start the first transfer while the number of concurrent task varies from one to three The 4 Header words have to be included in calculation even if only the Data Section is requested for transfer The following concurrent tasks are executed under control of the ...

Page 1613: ... is started at the begin of the next slot n 1 If the next slot is a dynamic slot without transmission reception minislot it may happen that the TBF MBF has not finished until begin of the next but one slot n 2 In this case the TBF MBF will be service requested break to start a transmission in the next but one slot MBF TBF and or to update the slot status SS MBF for the RX buffer corresponding with...

Page 1614: ...BF MBF OBF has to wait until the TBF MBF is continued see Figure 20 22 The relative time is measured in fCLC_ERAY cycles Absolute time depends on the actual fCLC_ERAY cycle period tbf_to_mbf_break timemax setup time mbf_to_tbf timemax setup time ss_to_mbf cyclesreq number of concurrent tasks setup time number of 4 byte words req tbf_to_mbf_break time setup time 2 fCLC_ERAY cycles slot counter n n ...

Page 1615: ...se scenario depends on the following parameters maximum payload length minimum minislot length number of configured Message Buffers excluding FIFO used channels single dual channel Figure 20 23 worst case scenario Max break time tbf_to_mbf_break timemax 2 68 4 1 75 Max number of fCLC_ERAY cycles cyclesreq 3 6 68 75 435 cyclestrans remaining cycles of transfer running cycles of second requested tra...

Page 1616: ...uested The length of a TBF MBF varies from 4 Header Section only to 68 Header maximum Data Section time step plus a setup time of 6 time steps A SS MBF has a fixed length of 1 time steps plus a setup time of 4 time steps The find sequence has a maximum length of 128 maximum number of buffers time steps plus a setup time of 2 time steps A minislot has a length of 2 to 63 Macrotick gdMinislot The mi...

Page 1617: ...um minislot length of 2µs a maximum of 128 configured Message Buffers dual channels in use Minimum fCLC_ERAY for various minimum minislot length Table 20 22 summarizes the minimum required fCLC_ERAY frequency for various minimum minislot length assuming time8minislots fCLC_ERAY period in µs fCLC_ERAY cyclest2m 7 fCLC_ERAY cyclesss2m fCLC_ERAY cyclesfind fCLC_ERAY period in ms minimum time8minislot...

Page 1618: ...or a typical configuration The minimum required fCLC_ERAY frequency for various assuming the following typical E Ray configuration a maximum payload length of 32 bytes 8 four byte words a minimum minislot length of 7 µs a maximum 128 configured Message Buffers dual channels in use The minimum fCLC_ERAY frequency for this typical example would be 10 MHz Table 20 22 Minimum fCLC_ERAY for different m...

Page 1619: ... the Message Handler If e g the Message Handler writes the next message to be send to Transient Buffer Tx the FlexRay Channel Protocol Controller can access Transient Buffer Rx to store the message it is actually receiving During transmission of the message stored in Transient Buffer Tx the Message Handler transfers the last received message stored in Transient Buffer Rx to the Message RAM if it p...

Page 1620: ...ssage Buffers depending on the configured payload length The Message RAM is organized 2048 x 32 To achieve the required flexibility with respect to different numbers of data byte per FlexRay Frame 0 to 254 the Message RAM has a structure as shown in Figure 20 25 The Data Partition is allowed to start at Message RAM word number MRC LCB 1 4 Address Decoder Transient Buffer Tx Transient Buffer Rx Shi...

Page 1621: ... bit pointer to the respective Data Section in the Data Partition Data Partition Flexible storage of Data Sections with different length Some maximum values are 30 Message Buffers with 254 byte Data Section each Or 56 Message Buffers with 128 byte Data Section each Or 128 Message Buffers with 48 byte Data Section each Restriction Header Partition Data Partition may not occupy more than 2048 32 bit...

Page 1622: ...he Message RAM For transmit buffers the Header CRC has to be calculated by the Host Payload Length Received PLR Receive Cycle Count RCC Received on Channel Indication RCI Startup Frame Indication bit SFI Sync bit SYN NULL Frame Indication bit NFI Payload Preamble Indication bit PPI and Reserved bit RES are only updated from received valid Frames including valid NULL Frames Header word 4 of each co...

Page 1623: ...Frame ID 2 Payload Length Received Payload Length Configured Tx Buffer Header CRC Configured Rx Buffer Header CRC Received 3 R E S P P I N F I S Y N S F I R C I Receive Cycle Count Data Pointer 4 R E S S P P I S N F I S S Y N S S F I S R C I S Cycle Count Status T F B F T Y M L S T E S B E S A T C I B T C I A S V O B S V O A C E O B C E O A S E O B S E O A V F R B V F R A Frame Configuration Filte...

Page 1624: ... Header CRC Transmit Buffer Configured by the Host calculated from Frame Header Segment Receive Buffer Updated from received Frame Payload Length Configured Length of Data Section 2 byte words as configured by the Host Payload Length Received Length of Payload Segment 2 byte words stored from received Frame Header 3 Write access via WRHS3 read access via RDHS3 Data Pointer Pointer to the beginning...

Page 1625: ...rame Indicator Status NFIS NULL Frame Indicator Status PPIS Payload Preamble Indicator Status RESS Reserved Bit Status 20 6 12 2 Data Partition The Data Partition of the Message RAM stores the Data Sections of the Message Buffers configured for reception transmission as defined in the Header Partition The number of data bytes for each Message Buffer can vary from 0 to 254 To optimize the data tran...

Page 1626: ...pective data word The ECC data is checked each time a data word is read from any of the RAM blocks If an ECC error is detected the respective error flag is set The ECC error flags MHDS EIBF MHDS EOBF MHDS EMR MHDS ETBF1 MHDS ETBF2 and the faulty Message Buffer indicators MHDS FMBD MHDS MFMB MHDS FMB are located in the Message Handler Status register These error flags control the error interrupt fl...

Page 1627: ...ll cases The respective ECC error flag in the Message Handler Status MHDS register is set The ECC error flag EIR EERR in the Error Service Request Register is set and if enabled a module service request to the Host will be generated EG EC EC EG EG EC ECC Generator ECC Checker EC EC Message RAM Transient Buffer RAM A Transient Buffer RAM B PRT A PRT B Output Buffer RAM 1 2 EG EG EC EG Input Buffer ...

Page 1628: ...is set 4 ECC error during scan of Header Sections in Message RAM a MHDS EMR bit is set b MHDS FMBD bit is set to indicate that MHDS FMB points to a faulty Message Buffer c MHDS FMB indicates the number of the faulty Message Buffer d Ignore Message Buffer Message Buffer is skipped 5 ECC error during data transfer from Message RAM Transient Buffer RAM A B a MHDS EMR bit is set b MHDS FMBD bit is set...

Page 1629: ...error occurs while the Message Handler reads a Frame with Network Management information PPI 1 from the Transient Buffer RAM A B the corresponding Network Management vector registers NMV1 to NMV3 are not updated from that Frame 20 6 13 Host Handling of Errors An ECC error caused by transient bit flips can be fixed by 20 6 13 1 Self Healing ECC errors located in Input Buffer RAM 1 2 Output Buffer R...

Page 1630: ...er number must be immediately preceded by the unlock sequence normally used to leave CONFIG state see Lock Register LCK on Page 20 35 For that single transfer the respective message buffer header is unlocked regardless whether it belongs to the FIFO or whether its locking is controlled by MRC SEC 1 0 and will be updated with new data ...

Page 1631: ...e application Therefore the Communication Controller supports disable enable controls for each individual service request source separately An service request may be triggered when An error was detected A status flag is set A timer reaches a preconfigured value A message transfer from Input Buffer to Message RAM or from Message RAM to Output Buffer has completed A stop watch event occurred Trackin...

Page 1632: ...uest 0 TI1 Timer Service Request 1 TIBC Transfer Input Buffer Completed TOBC Transfer Output Buffer Completed SWE Stop Watch Event SUCS Startup Completed Successfully MBSI Message Buffer Status Interrupt SDS Start of Dynamic Segment WUPA Wakeup Pattern Channel A MTSA MTS Received on Channel A WUPB Wakeup Pattern Channel B MTSB MTS Received on Channel B ILE EINT0 Enable Service Request Line 0 EINT1...

Page 1633: ...SRC SRE The two timer service requests generated by service request timer 0 and 1 are available on pins TINT0SR and TINT1SR They can be configured via the Timer 0 and Timer 1 Configuration register In addition each of the two interrupt lines can be enabled disabled separately by programming bit TINT0SRC SRE and TINT1SRC SRE A stop watch event may be triggered via input pin STPWn The status of the ...

Page 1634: ... 4 Header Section only to 68 Header maximum Data Section while the number of concurrent task varies from one to three The following concurrent tasks are executed under control of the Message Handler Data transfer between IBF or OBF and Message RAM Data transfer between TBF1 and Message RAM search next TX RX Message Buffer CHA Data transfer between TBF2 and Message RAM search next TX RX Message Buf...

Page 1635: ...equires two different clocks a sampling clock of the FlexRay bus fSCLK fSCLK has to be 8 times the baud rate of the FlexRay communication A second clock fCLC_ERAY is TXDB RXDB3 DMAx x 0 1 Eray_implementation_TC1784 28 vsd Address Decoder Interrupt Control ERAY Module Kernel RXDA1 TXDA INT0SRC TINT0SRC RXDA0 Channel A RXDA3 RXDA2 TXENA RXDB1 RXDB0 Channel B RXDB2 TXENB INT1SRC TINT1SRC Interrupt Se...

Page 1636: ... external registers Port control and connections I O port line assignment I O function selection Pad driver characteristics selection On chip connections SCU Connections DMA connections Module clock generation Interrupt registers E Ray address map 20 9 2 Port Control and Connections This section describes the I O connections of the E Ray module 20 9 2 1 Input Output Function Selection Table 20 27 ...

Page 1637: ... TXDA P0 10 not applicable P0_IOCR8 PC10 1X10B Output TXDA P5 8 not applicable P5_IOCR8 PC8 1X10B Output TXENA P0 12 not applicable P0_IOCR8PC12 1X10B Output TXENA P5 10 not applicable P5_IOCR8 PC10 1X10B Output B RXDB0 P0 9 ERAY_CUST1 RISB 00B P0_IOCR8 PC9 0XXXB Input RXDB1 P5 15 ERAY_CUST1 RISB 01B P5_IOCR12 PC15 0XXXB Input RXDB2 ERAY_CUST1 RISB 10B reserved Input RXDB3 ERAY_CUST1 RISB 11B rese...

Page 1638: ...T1SRC CH00_REGI11 CHCR00 PRSEL 1011B 00 IBUSY CH00_REGI12 CHCR00 PRSEL 1100B 01 TINT0SRC CH01_REGI11 CHCR01 PRSEL 1011B 02 NDAT1SRC CH02_REGI11 CHCR02 PRSEL 1011B 03 MBSC1SRC CH03_REGI11 CHCR03 PRSEL 1011B 04 INT1SRC CH04_REGI11 CHCR04 PRSEL 1011B 04 OBUSY CH04_REGI13 CHCR04 PRSEL 1101B 05 TINT1SRC CH05_REGI11 CHCR05 PRSEL 1011B 06 NDAT1SRC CH06_REGI11 CHCR06 PRSEL 1011B 07 MBSC1SRC CH07_REGI11 CH...

Page 1639: ...module of the TC1784 has one on chip interconnections to the External Clock Output Unit in the SCU to distribute externally as also internally the Macro Tick as time base for distributed system control e g to the GPTA as global system timer or external devices Table 20 32 shows this interconnection Table 20 29 External Stop Watch Request Assignment ERAY Input Signal ERU Request Output Line Selecte...

Page 1640: ...s are forced to their inactive state first before the module clock is switched off ERAY_CLC ERAY Clock Control Register 0000H Reset Value 0000 0100H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RMC 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw r rw w rw rw rh rw Field Bits Type Description DISR 0 rw E Ray Module Disable Request Bit Used for enable disabl...

Page 1641: ...de used for Message Buffer Status Changed Events The Interrupt Service Request Control Registers control the eight service request nodes FSOE 5 rw Fast Switch Off Enable Used for fast clock switch off in suspend mode RMC 10 8 rw Clock Divider in Run Mode 000B No clock signal fCLC_ERAY generated default after reset 001B Clock fCLC_ERAY fSYS selected 010B Clock fCLC_ERAY fSYS 2 selected 011B Clock f...

Page 1642: ... 27 NDIP 26 NDIP 25 NDIP 24 NDIP 23 NDIP 22 NDIP 21 NDIP 20 NDIP 19 NDIP 18 NDIP 17 NDIP 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDIP 15 NDIP 14 NDIP 13 NDIP 12 NDIP 11 NDIP 10 NDIP 9 NDIP 8 NDIP 7 NDIP 6 NDIP 5 NDIP 4 NDIP 3 NDIP 2 NDIP 1 NDIP 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NDIPn n 0 31 n rw New Data I...

Page 1643: ...P 58 NDIP 57 NDIP 56 NDIP 55 NDIP 54 NDIP 53 NDIP 52 NDIP 51 NDIP 50 NDIP 49 NDIP 48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDIP 47 NDIP 46 NDIP 45 NDIP 44 NDIP 43 NDIP 42 NDIP 41 NDIP 40 NDIP 39 NDIP 38 NDIP 37 NDIP 36 NDIP 35 NDIP 34 NDIP 33 NDIP 32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NDIPn n 32 63 n 32 rw New...

Page 1644: ...P 90 NDIP 89 NDIP 88 NDIP 87 NDIP 86 NDIP 85 NDIP 84 NDIP 83 NDIP 82 NDIP 81 NDIP 80 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDIP 79 NDIP 78 NDIP 77 NDIP 76 NDIP 75 NDIP 74 NDIP 73 NDIP 72 NDIP 71 NDIP 70 NDIP 69 NDIP 68 NDIP 67 NDIP 66 NDIP 65 NDIP 64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NDIPn n 64 95 n 64 rw New...

Page 1645: ...P 121 NDIP 120 NDIP 119 NDIP 118 NDIP 117 NDIP 116 NDIP 115 NDIP 114 NDIP 113 NDIP 112 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDIP 111 NDIP 110 NDIP 109 NDIP 108 NDIP 107 NDIP 106 NDIP 105 NDIP 104 NDIP 103 NDIP 102 NDIP 101 NDIP 100 NDIP 99 NDIP 98 NDIP 97 NDIP 96 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NDIPn n 96 ...

Page 1646: ... MSIP 25 MSIP 24 MSIP 23 MSIP 22 MSIP 21 MSIP 20 MSIP 19 MSIP 18 MSIP 17 MSIP 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSIP 15 MSIP 14 MSIP 13 MSIP 12 MSIP 11 MSIP 10 MSIP 9 MSIP 8 MSIP 7 MSIP 6 MSIP 5 MSIP 4 MSIP 3 MSIP 2 MSIP 1 MSIP 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MSIPn n 0 31 n rw Message Buffer Status...

Page 1647: ...7 MSIP 56 MSIP 55 MSIP 54 MSIP 53 MSIP 52 MSIP 51 MSIP 50 MSIP 49 MSIP 48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSIP 47 MSIP 46 MSIP 45 MSIP 44 MSIP 43 MSIP 42 MSIP 41 MSIP 40 MSIP 39 MSIP 38 MSIP 37 MSIP 36 MSIP 35 MSIP 34 MSIP 33 MSIP 32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MSIPn n 32 63 n 32 rh Message Buffer...

Page 1648: ...9 MSIP 88 MSIP 87 MSIP 86 MSIP 85 MSIP 84 MSIP 83 MSIP 82 MSIP 81 MSIP 80 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSIP 79 MSIP 78 MSIP 77 MSIP 76 MSIP 75 MSIP 74 MSIP 73 MSIP 72 MSIP 71 MSIP 70 MSIP 69 MSIP 68 MSIP 67 MSIP 66 MSIP 65 MSIP 64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MSIPn n 64 95 n 64 rw Message Buffer...

Page 1649: ...20 MSIP 119 MSIP 118 MSIP 117 MSIP 116 MSIP 115 MSIP 114 MSIP 113 MSIP 112 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSIP 111 MSIP 110 MSIP 109 MSIP 108 MSIP 107 MSIP 106 MSIP 105 MSIP 104 MSIP 103 MSIP 102 MSIP 101 MSIP 100 MSIP 99 MSIP 98 MSIP 97 MSIP 96 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MSIPn n 96 127 n 96 rw ...

Page 1650: ...y module kernels is able to generate an interrupt and is controlled by an interrupt service request control register INT0SRC INT1SRC TINT0SRC TINT1SRC NDAT0SRC NDAT1SRC MBSC0SRC MBSC1SRC OBUSYSRC and IBUSYSRC The service request OBUSYSRC and IBUSYSRC is generated when the Output Buffer or Input Buffer switches from busy state to the state being accessible by the host ...

Page 1651: ...equest Control Register 3DCH Reset Value 0000 0000H NDAT1SRC New Data 1 Service Request Control Register 3D8H Reset Value 0000 0000H MBSC0SRC Message Buffer Status Changed 0 Service Request Control Register 3D4H Reset Value 0000 0000H MBSC1SRC Message Buffer Status Changed 1 Service Request Control Register 3D0H Reset Value 0000 0000H OBUSYSRC Output Buffer Busy Service Request Control Register 3C...

Page 1652: ...re described in Chapter Interrupt System of the TC1784 User s Manual System Units part Volume 1 Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR 13 rh Service Request Flag CLRR 14 w Request Clear Bit SETR 15 w Request Set Bit 0 9 8 11 31 16 r Reserved Read as 0 should be written with 0 ...

Page 1653: ...ve been increased The GPTAv5 provides 16 such signals Each of the signals may be mapped to any output signal of a Local or Global Timer Cell Therefore it is not limited as before to a single group of Global or Local Timer Cells 25 of the GTC or LTC Limitation now is that no more than 4 different on chip trigger and gating signals may be mapped to one group of LTC or GTC Details concerning this new...

Page 1654: ...ing multiplexer and therefore fulfills this requirement already To be consistent to TC1797 the double connected input group of IOG3 is renamed to IOG6 and the Output Group OG1 7 are renamed to OG0 OG6 and the OG0 is renamed to IOG7 GPTAv4 Signal GPTA0_OUT17 is no longer available in GPTAv5 This signal was routed to the ERU to cover 50 of the GTC and LTC cells as input to Input channel 2 But Signal...

Page 1655: ...ls This new mechanism upgrades the older mechanism of global coherent update This older principle of global coherent is very useful to update a number of Local Timer Cells simultaneously This new features is upwards compatible to the GPTAv4 Four GPTA0 LTCA2 OUTs have been assigned to the new port P6 LVDS Port and four LTCA2 new inputs have been assigned to Port 6 The GPTA0 and LTCA2 OUTs are addit...

Page 1656: ...al motor control applications but can also be used to generate simple and complex signal waveforms required for other industrial applications Figure 21 1 General Block Diagram of the GPTA v5 units in the TC1784 Signal Generation Cells MCB05910_TC1767_LTC32 GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GTC31 Global Timer Cell Array GTC03 GTC30 Cl ...

Page 1657: ...GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform Local Timer Cells LTC operating in Timer Capture or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external or internal events On chip Trigger an...

Page 1658: ...A divided fGPTA clocks FPC1 FPC4 outputs DCM clock LTC prescaler clock Signal Generation Cells Global Timers GT Two independent cells Two operating modes Free Running Timer and Reload Timer 24 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency Global Timer Cell GTC 32 cells related to the Global Timers Two operating modes Capture Compare and Capture after Compare 24 bit...

Page 1659: ...Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external or internal events The following list summarizes the specific features of the LTCA cells Signal Generation Cells Local Timer Cell LTC 64 independent cells Three basic operating modes Timer Capt...

Page 1660: ...n be connected to port pins or other on chip logic modules see GPTA v5 Module Implementation on Page 21 269 for the TC1784 specific interconnections Further several clock input and output signals are provided Interrupt Control MCB05911_mod Clock Control Address Decoder fGPTA SR 37 00 GPTA Module Kernel Clock Generation Cells Filter Prescaler Cells Phase Discriminator Logic Duty Cycle Measurement C...

Page 1661: ...Distribution Cells CDC provide all LTCs and GTs with a variety of different clock signals It is equipped with GPTA v5 module clock prescalers and multiplexers supporting alternate clock sources The original signals and all outputs of the preprocessing cells are distributed to the Global Timers and LTCs via the clock bus The Signal Generation Cells see Page 21 38 provide a set of timers capture and...

Page 1662: ...the PDL phase encoding can be bypassed The Duty Cycle Measurement Cells DCM provide signal measurement capabilities timer plus capture register single and double capture on rising and falling edges or both as well as missing pulse detection reconstruction functions The Digital Phase Locked Loop PLL is intended to generate a higher resolution clock out of the values measured by DCM cells Any arbitr...

Page 1663: ...np Clock SOL1 SOT2 FPC2 Signal Inp Clock SOL2 SOT3 FPC3 Signal Inp Clock SOL3 SOT4 FPC4 Signal Inp Clock SOL4 SOT5 FPC5 Signal Inp Clock SOL5 M U X Control Logic M U X DCM0 DCM1 PDL0 F0 B0 M U X Control Logic M U X DCM2 DCM3 PDL1 F0 B0 PLL CDU GPTA Inputs GPTA Inputs GPTA Inputs GPTA Inputs GPTA Inputs Clock Bus 8 Ext PLL Clock Inputs CLK1 CLK2 CLK3 PDL0 PDL1 PDL2 PDL3 PDL Bus Int PLL Clock Output...

Page 1664: ...tive edges for the prescaler modes and detects glitches in all other modes Figure 21 4 Filter and Prescaler Cell Architecture FPC Registers The following registers are assigned to the filter and prescaler cells FPCk k 0 5 FPCSTAT Filter and Prescaler Cell Status Register see Page 21 167 FPCCTRk Filter and Prescaler Cell Control Register k see Page 21 168 FPCTIMk Filter and Prescaler Cell Timer Reg...

Page 1665: ...l input 1 SINk1 Signal input 2 SINk2 Signal input 3 SINk3 GPTA v5 module clock fGPTA SINk4 Preceding FPC level output signal SOLk 1 SIN05 is connected to SOL5 When the preceding FPC level output signal is selected as input two or more FPCs may be concatenated for example to combine a delayed debounce filter and an immediate debounce filter The maximum FPC input signal frequency must be less than o...

Page 1666: ...ple Therefore CIN clock rates above fGPTA will lead to non deterministic behavior Output Signal Splitting Two output lines are provided by each FPC cell as follows An trigger output signal SOTk reporting a falling or rising signal edge on the FPC input by a single fGPTA clock pulse A level output signal SOLk indicating the direction of the detected signal transition This signal splitting scheme pa...

Page 1667: ... idle state again see Figure 21 7 A rising or falling edge occurring on the signal input line SIN when the timer is greater than zero but less than the compare value sets the corresponding glitch flag FPCSTAT REG on rising edge glitch or FPCSTAT FEG on falling edge glitch When the timer matches the 16 bit compare value stored in FPCCTRk CMP timer threshold the level output signal line SOLk is inve...

Page 1668: ...rogrammed compare register value the number of high frequency pulses glitches during the filter operating time and the timer behavior in case of a glitch decrement or reset The FPC Delayed Debounce Filter Mode is selected by FPCCTRk MOD 000B MCT05916 Total Signal Delay Timer Threshold must be cleared by software Signal Input SIN Timer Value FPCCTRk TIM Level Output SOLk FPCSTAT FEGk FPCSTAT REGk T...

Page 1669: ...ue FPCCTRk CMP is not zero the timer is enabled to be incremented by the selected clock and the copy mechanism is disabled When the timer value FPCTIMk TIM matches the compare value FPCCTRk CMP the timer is reset and the copy mechanism is enabled again A rising or falling edge occurring on SIN while the timer is greater than zero but less than the compare value sets the corresponding glitch flag F...

Page 1670: ...tely after the timer threshold of the filtered edge is reached without re starting the timer see Figure 21 9 Figure 21 9 FPC Immediate Debounce Filter Algorithm on Rising Edge only The FPC Immediate Debounce Filter Modes are selected by FPCCTRk MOD 001B Immediate Debounce Filter Mode on both edges FPCCTRk MOD 010B Immediate Debounce Filter Mode on rising edge only no filtering on falling edge FPCC...

Page 1671: ... Figure 21 10 demonstrating Delayed Debounce Mode with Timer Decrement on Rising Edge and Immediate Debounce of on Falling Edge Figure 21 10 FPC Mixed Filter Algorithm The FPC Mixed Filter Modes are selected by FPCCTRk MOD 100B Delayed Debounce Filter Mode on rising edge Immediate Debounce Filter Mode on falling edge FPCCTRk MOD 101B Immediate Debounce Filter Mode on rising edge Delayed Debounce F...

Page 1672: ...er FPCTIMk TIM is reset to 0000H Figure 21 11 shows a divide by 6 operation using the FPC in Prescaler Mode with trigger on rising edge selected Figure 21 11 FPC Prescaler Mode For a divide by n operation the compare value FPCCTRk CMP must be set to n 1 The FPC Prescaler Modes are selected by FPCCTRk MOD 110B Prescaler Mode triggered by edge detection circuitry on rising edge FPCCTRk MOD 111B Pres...

Page 1673: ...or PDL1 The PDL processes the output signal of a 2 sensor or 3 sensor positioning system With bit PDLCTR TSEx 1 a 3 sensor system execution is selected providing the DCM1 and or DCM3 cell with information concerning erroneous states in the signal input When PDLCTR TSEx 0 a 2 sensor system is selected and DCM1 and or DCM3 are supplied with the input event and level information from the driving FPC2...

Page 1674: ...or positioning system To ensure that a transition of any input signal is correctly recognized its level should be held high or low for at least twofGPTA cycles before it changes three fGPTA cycles for a 3 sensor positioning system Figure 21 12 Block Diagram of Phase Discrimination Logic Cells MCB05921 2 FPC0 Phase Discrimation Logic PDL0 F0 B0 DCM0 2 2 2 FPC1 FPC2 DCM1 2 PDL0 PDL1 PDL2 PDL3 PDL Bu...

Page 1675: ...e position with a resolution of 90 No error conditions can be detected Figure 21 13 Interface Signals of a PDL in a 2 Sensor Positioning System Figure 21 14 illustrates how the output signals of a 2 sensor system superimposed with noise are processed by the PDL cell Jitter pulses are completely compensated if they do not occur on both signal lines simultaneously Means not Re Means rising edge Fe M...

Page 1676: ... or all inputs high cause the following to occur An error signal is generated driving the Duty Cycle Measurement cells DCM1 and or DCM3 The error flag PDLCTR ERRx is set No forward or backward pulses are generated When the error disappears the error signal will be cleared The error flag PDLCTR ERRx must be reset by software Means not Re Means rising edge Fe Means falling edge Forward ReS1 S2 S3 Fe...

Page 1677: ...e Signals of a PDL in a 3 Sensor Positioning System Jitter pulses are completely compensated as illustrated in Figure 21 14 MCT05924 1 2 3 4 5 6 1 2 S1 S2 S3 Forward Backward 1 6 5 4 3 2 1 6 S1 S2 S3 Forward Backward S2 S3 S1 Forward_Counter Backward_Counter 1 3 2 4 5 6 1 2 3 4 5 6 00 01 11 10 00 01 11 10 0 1 S3 ...

Page 1678: ...a 24 bit timer a 24 bit capture register a 24 bit capture compare register a 24 bit comparator and a DCM control circuitry Figure 21 16 The following registers are assigned to the DCM cells DCMCTRk Duty Cycle Measurement Control Register k see Page 21 173 DCMTIMk Duty Cycle Measurement Timer Register k see Page 21 174 DCMCAVk Duty Cycle Measurement Capture Register k see Page 21 175 DCMCOVk Duty C...

Page 1679: ...m its lower limit 000000H to its upper limit FFFFFFH Capture The current timer value is stored in the capture register DCMCAV on the rising edge DCMCTR RCA 1 or falling edge DCMCTRk RCA 0 of the signal input line The current timer value is stored in the capture compare register DCMCOV on the opposite signal edge as selected by DCMCTRk RCA and if enabled by bit DCMCTRk OCA 1 With DCMCTRk OCA 0 the ...

Page 1680: ...stored in capture compare register the service request flag SRS0 DCM0xC is set If the compare service request is enabled control register bit DCMCTRk CRE 1 an interrupt request is generated Software Generated Output Pulse If the software intends to compensate an input pulse backlog bit DCMCTRk QCK should be set to 1 This immediately triggers a single clock pulse generation on the DCM output signal...

Page 1681: ...ed by the corresponding enable bit Further details on service request and interrupt handling are provided in section Interrupt Sharing Block IS on Page 21 123 Figure 21 17 DCMk Service Request Generation MCA05926_mod RRE DCMCTRk DCM0kR DCM0kR DCM0kR SRSS0 read SRSR0 read Set SRSS0 write SRSC0 write Set Reset FRE DCMCTRk DCM0kF DCM0kF DCM0kF SRSS0 read SRSR0 read Set SRSS0 write SRSC0 write Set Res...

Page 1682: ...PLLSTP Phase Locked Loop Step Register see Page 21 177 PLLREV Phase Locked Loop Reload Register see Page 21 178 PLLDTR Phase Locked Loop Delta Register see Page 21 179 SRSC0 Service Request State Clear Register 0 see Page 21 219 SRSS0 Service Request State Set Register 0 see Page 21 221 Three output signals are available on the PLL cell PLL signal output line Uncompensated PLL signal output line S...

Page 1683: ...it is enabled by the enable bit PLLCTR REN Additional information about service request and interrupt handling are given in section Interrupt Sharing Block IS on Page 21 123 Figure 21 19 PLL Service Request Generation MCB05927 Input MUX 16 MTI Microtick Value PLLMTI CNT Microtick Counter PLLCNT REV Reload Value PLLREV STP Step Value PLLSTP 2 Complement MUX DTR Delta Value PLLDTR Sign Bit ADD Unit ...

Page 1684: ... with a negative value 2 complement data format When the PLLDTR register has been decremented to a negative value the reload register contents are added to Delta register s current contents A rising edge detected on the selected input signal triggers the counter register PLLCNT to load the number of requested output pulses from PLLMTI When a negative content of the PLLDTR register is detected the ...

Page 1685: ...paring the current period length measured in the associated DCM cell with the expected period length used as calculation base for the PLLREV register contents Compensation of input signal deceleration Compensation by PLL Automatic End Mode If Automatic End Mode is enabled PLLCTR AEN 1 the PLL stops at the calculated end of the current input signal period Due to the deceleration the rising edge of ...

Page 1686: ...signal arrives while the counter has not been decremented to zero The PLL performs all remaining output signal pulses at full speed fGPTA when control register bit AEN is set to 1 Afterwards counter and Delta register are reloaded with their calculated values and the PLL operates at normal speed see Figure 21 23 Compensation by Software After disabling the Automatic End Mode the PLL generates fewe...

Page 1687: ...ovides an uncompensated output signal This signal has no gaps or acceleration bursts However the number of microticks during one signal period may be incorrect 21 3 2 5 Clock Distribution Cell CDC The Clock Distribution Cells CDC provides all Local and Global Timer Cells with a clock bus containing eight different clock output signals CLK 7 0 and a special LTC prescaler clock LTCPRE These nine clo...

Page 1688: ... 14 selects an alternate source For clock bus line CLK3 the 2 bit wide bit field DFA03 of control register CKBCTR selects one of the four available clocks The LTC prescaler clock LTCPRE is generated by dividing the fGPTA module clock by a factor defined by the 3 bit wide bit field DFALTC of control register CKBCTR Note that the LTCPRE clock is not a part of the clock bus but a clock signal that is...

Page 1689: ...05933 14 0 13 15 0 14 DFA02 CKBCTR 15 CLK0 DFA04 CKBCTR 15 0 14 DFA06 CKBCTR 15 0 14 DFA07 CKBCTR 1 0 DFA03 CKBCTR 2 3 ext PLLCLK PLLCLK fGPTA PLLCLK uncomp ext PLLCLK uncomp FPC1 SOT1 FPC4 SOT4 DCM0 DCM1 DCM3 DCM2 PLL Clock Bus CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 0 7 DFALTC CKBCTR LTCPRE 2DFA02 2DFA04 2DFA06 2DFA07 2DFALTC 4 2 14 4 15 15 15 8 4 4 3 ...

Page 1690: ... reload register and a 24 bit greater equal comparator see Figure 21 25 Note Index variable k 0 1 determines the number of the Global Timer Figure 21 25 Block Diagram of Global Timer GT The following registers are assigned to the Global Timers GTk k 0 1 GTCTRk Global Timer Control Register k see Page 21 180 GTREVk Global Timer Reload Value Register k see Page 21 181 GTTIMk Global Timer Register k ...

Page 1691: ...oftware into the GTTIMk register The 24 bit Global Timer value GTTIMk TIM is incremented by each rising edge of clock input signal TEVk that is selected from the 8 bit clock bus via bit field GTCTRk MUX On a Global Timer overflow transition of FFFFFFH to 000000H the following events occur The 24 bit reload value GTREVk REV is copied into GTTIMk TIM Bit SRSC0 GT0k is set The service request output ...

Page 1692: ...Both Global Timers GT0 and GT1 can be enabled and disabled individually Each GT has its own run signal GTkRUN that is generated outside the GPTA v5 kernel see also Page 21 8 Signal GTkRUN is generated in a GPTA v5 clock control circuitry This external control capability allows the run signals GTkRUN to be controlled in a way that all Global Timers of one ore more GPTA v5 units can be enabled disab...

Page 1693: ...imer is running and a new threshold value T is set The different points Px represent different cases of present time When at P1 or P2 the moment represented by T lies in the future and no action is yet required When at P3 or P4 the moment represented by T lies in the past and an action is required immediately So the problem is to determine if the threshold T has been passed or not Considering an i...

Page 1694: ... Before window refers to a prediction range and the After window refers to the history buffer From a practical point of view once the value T is determined it is necessary to calculate the observation window position and width Before updating the value T the application must assure that the observation window was entered but has not yet been left The width of the observation window cannot exceed t...

Page 1695: ...on window This is illustrated in Figure 21 29 Using a signed compare in order to take into account the timer overflow the comparator window is introduced The comparator window is centered to the point T and its width can be selected by the user Figure 21 29 Unsigned Versus Signed Compare When the timer range is a multiple of 2 and because the comparator is scalable the observation window and the c...

Page 1696: ... period This will impact the observation window as described in the following paragraph Observation window for reloaded timers period is not a power of 2 In that case the comparator window must exceed the timer period The user must find the comparator window by selecting the scale factor k which fits best the timer period The following equation must apply 2k Period 2 2k 21 1 Figure 21 31 and Figur...

Page 1697: ...re 21 32 Observation Window when Threshold T is Low MCT05940 Observation performed by G E compare Before After T Before Comparator Window 2 2k Observation Window Period Should be After Core Observation Window MCT05941 Observation performed by G E compare Before Comparator Window Observation Window Should be Before Core Observation Window After After T ...

Page 1698: ...sing the core observation window the size of the core observation window varies depending on two static values the timer period and the comparator window s sizes In particular the core observation window reduces as the value of the timer period is just after a power of 2 This is shown in Figure 21 34 For any timer period whatever the range and any threshold position a symmetrical core observation ...

Page 1699: ...5 bits is explained later Figure 21 35 Comparator Implemented by a Subtraction Circuitry The interpretation of the selected result bit is provided in the following simple example For a 4 bit timer the subtraction of the threshold T from the timer value leads to a 4 bit signed result as illustrated in Figure 21 36 This example is selected for simplicity although 4 bit periods are not covered by the...

Page 1700: ...sult and Observation for a 4 Bit Timer MCA04616 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Result in 2s Complement Aft...

Page 1701: ...valuation of S Evaluation of R3 S 1 S 0 R3 1 R3 0 T Evaluation of Result Timer T N3 N2 N1 N0 T3 T2 T1 T0 R3R2R1R0 S Timer Value Threshold Value Result Value with Sign Bit S Example for 4 Bit Timer n 4 Unsigned Compare The Bit Evaluated is S Signed Compare on Bit 3 The Bit Evaluated is R3 MCT05947 4 15 Evaluation of R3 R3 1 R3 0 T Evaluation of Result Timer T N3N2N1N0 T3 T2 T1 T0 R3R2R1R0 S Timer V...

Page 1702: ...rator window be equal to or greater than twice the period k represents the Result bit to select How to Proceed Unsigned greater equal compare SCO bit field 0FH 15d Thereby the sign bit of the result is selected to drive TGE flag This setting is valid for all possible periods The observation window always matches the period Signed greater equal compare Depending on the period the appropriate k is s...

Page 1703: ...s for a timer period equal to M m 1 In the following figures the X axis indicates the timer value elapsing time and the Y axis indicates the threshold value T The 45 line starting at m m represents the position in time of T The graphic shows the observation performed by the hardware for all cases of T m T M Table 21 1 Period Range Depending on Selected k 2k Period 2 2k k SCO Bit Field decimal 0 pe...

Page 1704: ...llustrates the Signed compare where the period equals a multiple of 2 that means M m 1 2 2k In this case for a higher value of T the observation indicates After at the beginning of the period not yet inside the observation window When entering the observation window Before is indicated until the timer reaches the value T Thereafter the observation switches to After and remains there until the time...

Page 1705: ...epresentation of the Signed compare shows a discontinuity in the Before and After ranges Indeed the widths of the Before and After windows are not constant as they depend on the value T As a consequence the observation window is not centered on T The result is that the position of the observation window would have to be re evaluated for each value T i e determining the widths of the After and the ...

Page 1706: ... T It also shows the core observation window that is always centered on T and which has a constant width Figure 21 42 Core Observation Window in the Graphic Before MCT05950 After Before Before Timer M m m Threshold M Value of T T point in time 2 2 k Period Comparator Window Period After After Before Before MCT05951 Timer M m m Threshold M Point T1 Observation Window Core Observation Window Point T...

Page 1707: ...et toggle the output signal Capture after compare match the value of the selected Global Timer or the opposite Global Timer One Shot Mode allows the selected capture or compare mode to be stopped after the first event Flexible mechanism to link pin actions and allow complex combination of cells A cell has the ability to propagate actions over adjacent cells with higher number in order to perform c...

Page 1708: ...ta output GTCkOUT that can be connected to External port lines Inputs of an MSC module Outputs and or inputs of Local Timer Cell inputs Two action mode outputs M0O M1O going to the adjacent GTC with higher order number One service request line SQSk triggered by a capture compare event Figure 21 43 Architecture of Global Timer Cells MCA05952 GTCk Control Logic M1O GTCkIN X 24 Bit Value GTV1 GTCXRk ...

Page 1709: ...e Cascading of GTCs is limited TC1784 specific details are given on Page 21 293 MCA05953 From GTC29 Global Timer Cell GTC00 M1I M0I M1O M0O GTC00IN GTC00OUT SQS00 GTV1 Bus TGE1 TEV1 GTV0 Bus TGE0 TEV0 Global Timer GT0 Global Timer Cell GTC01 M1I M0I M1O M0O GTC01IN GTC01OUT SQS01 Global Timer Cell GTC30 M1I M0I M1O M0O GTC30IN GTC30OUT SQS30 Global Timer Cell GTC31 M1I M0I GTC31IN GTC31OUT SQS31 T...

Page 1710: ...tored in register GTCXR With GTCCTRk GES 0 an Equal Compare match is selected while GTCCTRk GES 1 selects a Greater Equal Compare match On the requested event the GTC Sets the GTCk service request flag in register SRSS1 SRSC1 Activates service request output SQSk if control register bit GTCCTRk REN 1 Performs an GTCkOUT output signal line manipulation set reset toggle unchanged as defined by bit f...

Page 1711: ...ted when the compare value is reached and released after a read access of register GTCXRk occurred Data Output Line Control The data output GTCkOUT can be controlled by the GTCk itself and by adjacent GTCs with a lower order number For this purpose two communication signals between GTCs are available connecting all GTCs via their M1I M0I inputs and their M1O M0O outputs respectively see Figure 21 ...

Page 1712: ... to output ports on chip peripheral inputs and or LTC inputs via the I O Line Sharing Block see Page 21 98 GTCkOUT can be updated directly by software setting bit GTCCTRk OIA 1 or upon a timer capture or compare event within the local GTCk or a preceding GTC The current state of the data output line can be evaluated by reading status flag GTCCTRk OUT Table 21 2 Selection of GTC Output Operations a...

Page 1713: ... When a preceding GTC generates and communicates an event or OIA via its communication link M1O M0O at least one of the M1I M0I input lines changes its state to 1 This condition clears bit GTCCTRk EOA of the disabled GTC via the OR gate as shown in Figure 21 45 Now GTCCTRk CEN is set and the cell is enabled for local events It is also possible to enable the following GTC via the communication link...

Page 1714: ...ister of the third cell is loaded with another compare value by the interrupt service routine related to the second GTC the output port line may be reset by the next compare event within GTC3 This logical operating cell provides an output signal with programmable pulse width and configurable delay with minimal software overhead GTC Service Request The service request output SQSk of a Global Timer ...

Page 1715: ...l from a GTC input multiplexer group becomes analyzed from a timing reference point for three consecutive signal transitions This common input signal e g a port line is selected by a GTC input multiplexer group GIMG common for GTC01 GTC02 and GTC03 see also Page 21 111 The GTCs are configured in the following way GT0 operates as free running up counting 24 bit timer with reload to GTREV0 REV on ov...

Page 1716: ...e at its data input it captures the current GT0 value into its GTCXR02 register enables GTC03 and becomes disabled afterwards because it was operating in One Shot Mode When GTC03 detects a rising edge at its data input it captures the current GT0 value into its GTCXR03 register and becomes disabled afterwards because it was operating in One Shot Mode Optionally the capture event at GTC03 may gener...

Page 1717: ...es in Compare Mode with timer GT0 with enable on action set EOA set and One Shot Mode enabled OSM set Furthermore the output GTC03OUT becomes reset on a local event OCM 110B GTC02 operates in Compare Mode with timer GT0 with enable on action set EOA set and One Shot Mode enabled OSM set Furthermore the output GTC03OUT becomes set on a local event OCM 111B GTC03 operates in Compare Mode with timer ...

Page 1718: ...output signal GTC03OUT is set GTC03 becomes enabled and GTC02 becomes disabled because it was operating in One Shot Mode When the GTC03 compare event occurs the output signal GTC03OUT is reset and GTC02 becomes disabled because it was operating in One Shot Mode The capture event at GTC03 should generate a service request to indicate that the three compare events have occurred and that GTC01 can be...

Page 1719: ...mpare of the corresponding Reset Timer LTC with following actions Service request generation Output signal transition generation set reset toggle the output signal Timer Mode incremented on hardware signal with following actions Event generation at overflow Service request generation Output signal transition generation set reset toggle the output signal Reset Timer Mode allows the selected LTC to ...

Page 1720: ...nal port lines GTC00 to GTC31 outputs Clock bus signals PDL0 or PDL1 outputs Internal GPTA v5 kernel input signals INTx x 0 3 Figure 21 50 Architecture of Local Timer Cells Each LTC provides the following input output signals One data output line LTCkOUT that can be connected to External port lines Inputs of an MSC module Outputs and or inputs of Global Timer Cell inputs One LTC prescaler clock in...

Page 1721: ...Cs LTC63 is a Local Timer Cell that differs from all other LTCs LTC00 to LTC62 LTC63 is described in detail on Page 21 79 Figure 21 51 Interconnections between the LTCs Note Cascading of LTCs is limited TC1784 specific details are given on Page 21 293 From LTC60 Local Timer Cell LTC00 M3I M2I LTC00IN LTC00OUT SQT00 To LTC02 TI EO SI M3O M2O TI EI SO 0000H YI YO Local Timer Cell LTC01 M3I M2I TI EO...

Page 1722: ...it field LTCCTRk OCM an action request generated by an LTCk internal event or received on the M1I M0I input lines is transferred via the M1O M0O output lines to the LTC with higher order number LTCk 1 The event output line EO is also activated set to high by a software reset when writing FFFFH to register LTCXRk Reset Timer Mode An LTC that is configured in Reset Timer Mode provides the same funct...

Page 1723: ... LTCk service request flag is set The service request line SQTk is activated if LTCCTRk REN is set to 1 The LTCkOUT output line state is changed set reset toggle unchanged depending on bit field LTCCTRk OCM An action request is generated and or passed via the M1O M0O output lines to the LTC with higher order number LTCk 1 The event output EO is set to high level for one fGPTA clock cycle Note To e...

Page 1724: ...al signal operates as gating signal for the cell The active input level can be selected with control register bit AIL Additionally the LTC prescaler mode can be enabled with LTCCTRk PEN to reduce the timer frequency The programmed function of the LTC is performed with the GPTA v5 module clock frequency or with the programmed prescaler clock LTCPRE see Page 21 37 The programmed function of the LTC ...

Page 1725: ...uts respectively Figure 21 52 Figure 21 52 LTC Output Operation and Action Transfer GTC output The GTC output signal operates as gating signal for the cell The active input level can be selected with bit LTCCTRk AIL Additionally the LTC prescaler clock LTCPRE can be enabled with bit LTCCTRk PEN to reduce the timer frequency The programmed function of the LTC cell is performed on selected edge s Ta...

Page 1726: ...CTRk GBYP is cleared the action requests received via M1I M0I input lines if enabled by bit LTCCTRk OCM2 are forwarded to the subsequent LTCk 1 via the M3O M2O output lines If LTCCTRk GBYP is set to 1 the action requests received via M3I M2I input lines are forwarded to the subsequent LTCk 1 via the M3O M2O output lines Therefore the M3I M2I may be used to pass the action requests of a reseted tim...

Page 1727: ...request then locally generated within the group or local bypassed cell Within a group complex signals may be generated or two cells used for local coherent update double action principle Table 21 4 Selection of LTC Output Operations and Action Transfer Modes Bit Field OCM 2 0 Local Event M1O M0O State of Local Data Output Line BYP 0 BYP 1 GBYP 0 GBYP 1 GBYP 0 GBYP 1 0 0 0 No Yes 0 0 0 0 0 0 0 0 0 ...

Page 1728: ... some after the to be moved Local Timer Group Because the Local Time Bus YI and YO is driven by every LTC configured as timer regardless of the chosen bypass mechanism special care has to be taken An example is sketched in Figure 21 54 Three Local Timer for an edge aligned PWM using the same time base as the local Timer Cell Group1 but different offsets not edge aligned is inserted into another gr...

Page 1729: ...st be temporary disabled by setting LTCCTRk EOA Enable Of Action to 1 Because bit EOA is hardware protected intrinsic read modify write assembler operations2 only disables the LTC if bit EOA is modified from 0 to 1 Both operations will clear LTCCTRk CEN and now a local event cannot affect the LTC When a preceding LTC generates and communicates an event or OIA via the communication link M1O M0O at ...

Page 1730: ...ition selected by the LTCCTRk bits SOH SOL Additional LTCs of the same logical cell can operate in Capture Mode triggered by a rising edge falling edge or both edges of a GPTA v5 input line or a clock line of the clock bus On the generated event these LTCs capture the current contents of the timer cell can generate a service request can perform a manipulation of a GPTA v5 output line set reset or ...

Page 1731: ...nal transition generation set reset toggle the output signal Bit Reversal Mode Timer can be selected to enable a special PWM Mode called pulse count modulation PCM Compare Value Switching can be triggered by a hardware signal This function can generate a service request One Shot Mode makes it possible to stop the function after the first event Architecture LTC63 is locally equipped with a 16 bit c...

Page 1732: ...LTCXR63 X is greater than the timer value provided at YI the comparator output signal is 1 The timer value at YI comes from the LTC62 either in original or in reversed order Bit0 Bit15 Bit1 Bit14 etc The greater comparator output is connected directly to the output line LTC63OUT The 16 bit compare value LTCXR63 X is never greater than the LTC timer value FFFFH coming from YI and which is used on L...

Page 1733: ...n arbitrary time the actual duty cycle for the current period will reflect the old duty cycle the new one or a mixture of both A duty cycle of 100 will be generated if the compare register is set to FFFFH Pulse Count Modulation Mode PCM With a period of 100 clocks and a duty cycle of 64 standard PWM will produce an output signal that is ON for 64 clock cycles and OFF for the remaining 36 clock cyc...

Page 1734: ...rst case error If the duty cycle is changed at an arbitrary time the actual duty cycle for the entire current period will reflect the old duty cycle the new one or a mixture of both Table 21 5 Implicit PCM Rounding Desired Duty Cycle Expected ON Pulses Actual ON Pulses 0 000 0000 0 0 0 100 199AH 10 11 0 500 8000H 50 50 0 800 CCCDH 80 82 0 900 E666H 90 90 0 999 FFBEH 100 99 1 000 FFFFH 100 100 MCT0...

Page 1735: ... directly For compare value switching triggered by hardware the shadow register LTCXR63 XS 16 bit high part of LTCXR63 is pre loaded with the desired duty cycle On an LTC input signal selected via the LTC input multiplexer The shadow register content LTCXR63 XS is copied to the compare register LTCXR63 X The LTC63 service request flag is set An interrupt request will be activated if enabled by bit...

Page 1736: ... signal for the cell If the input is high the copy function of the LTC cell is performed with each rising edge of the GPTA v5 module clock fGPTA The copy function of the LTC cell is performed on selected edge s Internal Clock Bus Line or PDL output or INT input The copy function is performed with the internal clock or PDL INT signal The copy function of the LTC cell is performed on selected edge s...

Page 1737: ...y cycle if using Local Timer Cells Both mechanism grant a coherent update only if a single update within a group of Local Timer Cells using a common Local Timer is performed within a timer period So coherent update can only be granted if between coherent updating routine exit and coherent updating routine entry a time period of more then a period is maintained If updating more frequently software ...

Page 1738: ...ation with 5 LTCs global coherent update As shown in Figure 21 59 a logical cell of five LTCs can be used to generate a PWM signal with a programmable duty cycle period length and fully global coherent update of the period and duty cycle In this example LTC00 up to LTC04 are used to generate a PWM signal at the output of LTC04 To reduce complexity of this example only a single duty cycle pair is d...

Page 1739: ...imer Cell LTC00 M1I M0I TI EO SI M1O TI EI SO YI YO Local Timer Cell LTC01 M1I M0I LTC00IN TI EO SI M1O TO EI SO YI YO MCA05967 LTC04OUT Reset Timer Period Compare Local Timer Cell LTC02 M1I M0I TI EO SI M1O TO EI SO YI YO Duty Cycle Compare Local Timer Cell LTC03 M1I M0I TI EO SI M1O TO EI SO YI YO Period Compare Local Timer Cell LTC04 M1I M0I TI EO SI M1O TO EI SO YI YO Duty Cycle Compare M0O M0...

Page 1740: ...nt update feature the local coherent update mechanism double action principle is preferable Mixing both principle so updating the period using the coherent update and updating one or more duty cycle using local coherent update double action principle may result under specific condition in distorted signals new duty cycle old period or old duty cycle and new period Therefore within a period either ...

Page 1741: ...d compare value 3E7H 999D GPTA0_LTCCTR01 0001 5C11H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC01 continuously enabled SOH 0 SOL 1 compare enabled by low level at SI BYP 0 local bypass in LTC01 is disabled GBYP 1 global bypass in LTC01 is disabled EOA 0 LTC02 enabled for local events OCM 011B set LTC01OUT by a local event only OIA 1 output action defined by OCM must be performed immediately...

Page 1742: ...al event or copy the previous cell action OIA 1 output action defined by OCM must be performed immediately LTC04 Configuration Setup GPTA0_LTCXR04 0000 05DBH Load compare value 5DBH 1499D GPTA0_LTCCTR04 0001 3421H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC04 continuously enabled SOH 1 SOL 0 compare enabled by high level at SI BYP 0 local bypass in LTC04 is disabled GBYP 1 global bypass in ...

Page 1743: ... and the other being inactive LTCCTRk SOH 0 LTCCTRk SOL 0 LTCCTRk CEN 0 This pair of Local Timer Cells are configured to generate both action requests for a single output signal e g pin A Local Timer Cell being inactive may be configured programmed with a new value without distortion of the output signal because of being inactive By activating the newly configured Local Timer Cell LTCCTRk SOH 1 LT...

Page 1744: ...are Mode It is always active and responsible for the LTC03OUT signal generation in Phase 1 With the programmed value from Table 21 8 the LTC03OUT signal of Phase 1 has a period of 1000D 3E8H clocks of the LTC00IN clock signal and a duty cycle of 20 200D or C8H LTC01 is configured in such a way LTCCTR01 OCM 011B that its output LTC01OUT is set to 1 whenever the LTC00 timer value LTCXR00 X is equal ...

Page 1745: ... coherent updating the period of a Timer in Reset Timer Mode is required the global coherent update mechanism must be used Note Global bypass may be used to route e g period action request edge aligned PWM around the pair of locally coherent updated Local Timer Cells to following Local Timer Cells But special care has to be taken because the timer bus is not routed over a LTC configured as timer N...

Page 1746: ...d by the dominating duty compare cell resetting the same data output line and therefore not passing the MI0 and MI1 signal from the timer to the data output line This result in a data output line remaining continuously low Note To generate an output signal having 100 duty cycle continuously high the duty cycle threshold must be set above the period threshold value Therefore no reset event for the ...

Page 1747: ... rising edge one clock bus signal is selected via the LTC input multiplexer SLO 0 state of select line output SO is 0 CEN 0 enable LTC00 for local events OCM 000B hold LTC00OUT state LTC01 Configuration Setup GPTA0_LTCXR01 0000 03E7H Load compare value 3E7H 999D GPTA0_LTCCTR01 0000 5C11H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC01 continuously enabled SOH 1 SOL 1 enabled by both level at ...

Page 1748: ...2OUT by a local event or copy the previous cell action OIA 0 no immediate output action required LTC03 Configuration Setup GPTA0_LTCXR03 0000 0301H Load compare value 301H 769D GPTA0_LTCCTR03 0001 3401H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC03 continuously enabled SOH 0 SOL 0 compare disabled by low and high level at SI BYP 1 local bypass in LTC03 is disabled GBYP 1 end of global bypas...

Page 1749: ...ORE SWAP or CLEAR_BIT assembler instructions Set LTCCTR02 OSM 1 of LTC02 Use LOAD MODIFY STORE SWAP or CLEAR_BIT assembler instructions Read LTCXR02 Read LTCXR00 If LTCXR00 Read_LTCXR02 then Clear LTCCTR02 SOL LTCCTR02 SOH 0 of LTC02 End If Else Write New_Value into LTCXR02 of LTC02 Set LTCCTR02 OSM 0 and LTCCTR02 SOL LTCCTR02 SOH 1 for LTC02 Do not use LOAD MODIFY STORE SWAP or CLEAR_BIT assemble...

Page 1750: ...2 output lines assigned to seven I O groups IOG 6 0 two on chip trigger and gating signal groups OTG 1 0 and seven output groups OG 6 0 Figure 21 64 Input Output Line Sharing Block Overview MCA05969_mod INT 3 0 Output Multiplexer OUT 55 00 GTC Input Multiplexer PDL 3 0 INT 3 0 CLK 7 0 LTC Input Multiplexer IN 55 00 OUT 111 56 GPTA Module Kernel OG0 Output Groups OG1 OG2 OG3 56 32 32 64 56 8 8 24 4...

Page 1751: ... an LTC Group LTCG3 LTC24 LTC25 LTC26 LTC27 LTC28 LTC29 LTC30 LTC31 LTC24OUT LTC25OUT LTC26OUT LTC27OUT LTC28OUT LTC29OUT LTC30OUT LTC31OUT GTC08IN GTC09IN GTC10IN GTC11IN GTC12IN GTC13IN GTC14IN GTC15IN GTC08 GTC09 GTC10 GTC11 GTC12 GTC13 GTC14 GTC15 GTC08OUT GTC09OUT GTC10OUT GTC11OUT GTC12OUT GTC13OUT GTC14OUT GTC15OUT Pin IO40 Pin IO41 Pin IO42 Pin IO43 Pin IO44 Pin IO45 Pin IO46 Pin IO47 OUT4...

Page 1752: ...als SOL 5 0 of the FPCs with two external input lines INT 1 0 of the GPTA v5 unit The PDL INT group is a group that combines the four PDL output lines of the PDL bus with four external input lines INT 3 0 of the GPTA v5 unit An On chip trigger and gating signal group combines eight GPTA v5 output lines connected to on chip peripherals This results in two on chip trigger and gating signal groups OT...

Page 1753: ...40 IOG6 IN 55 48 OUT 55 48 Output Groups OG0 OUT 63 56 OG1 OUT 71 64 OG2 OUT 79 72 OG3 OUT 87 80 OG4 OUT 95 88 OG5 OUT 103 96 OG6 OUT 111 104 On Chip Trigger and Gating Signals Groups OTG0 OTGS 07 00 OTG1 OTGS 15 08 Clock Group CLK 7 0 FPC INT Groups FPC 5 0 SOL 5 0 External Input 1 0 INT 1 0 PDL INT Groups PDL 1 0 PDL Bus PDL 3 0 External Input 3 0 INT 3 0 Table 21 9 Group to I O Line Cell Assign...

Page 1754: ...O groups are connected not programmable with the FPCk inputs The FPCk input line selection is controlled by the FPCCTRk IPS bit fields Table 21 10 shows the FPC input line connections Table 21 10 FPC Input Line Assignments FPC Control Register Bit Field IPS Selected Input Signal FPCCTR0 000B IN0 001B IN12 010B IN24 011B IN36 FPCCTR1 000B IN2 001B IN14 010B IN26 011B IN38 FPCCTR2 000B IN4 001B IN16...

Page 1755: ...ame way I O groups and output groups are grouped into 14 groups seven I O groups and seven output groups with 8 lines each IOG0 and OG0 share the same physical pins similarly for IOG1 and OG1 IOG2 and OG2 IOG3 and IOG6 share the same physical pins for inputs as also outputs LTC Groups GTC Groups I O Groups Output Groups MCA05971 IOG0 IOG1 IOG2 IOG3 IOG4 IOG5 IOG6 8 GTCG0 GTC 07 00 GTCG1 GTC 15 08 ...

Page 1756: ... the outputs OUT0 to OUT7 are wired via OMG03 to input lines 0 to 7 of I O group 3 IOG3 One input of an I O or output group can be connected to the output of only one timer cell This is guaranteed by the OMG control register layout Otherwise short circuits and unpredictable behavior would occur On the other hand it is permissible for the output of a GTC or LTC to be connected to more than one inpu...

Page 1757: ...y bit field OMLn Bit field OMGn controls the 2 level multiplexer and connects one of the 1 level multiplexer outputs to output n The output of the 2 level multiplexer is connected only to the input of an I O group or output group if bit MRACTL MAEN is set multiplexer array enabled and no reserved bit combination of OMGn is selected If one of these conditions is not true the corresponding OMG outpu...

Page 1758: ...IN 19 16 OUT 19 16 OMCRL2 GTCG2 LTCG2 LTCG6 IN 23 20 OUT 23 20 OMCRH2 IOG3 IN 27 24 OUT 27 24 OMCRL3 GTCG3 LTCG3 LTCG7 IN 31 28 OUT 31 28 OMCRH3 IOG4 IN 35 32 OUT 35 32 OMCRL4 GTCG0 LTCG0 LTCG4 IN 39 36 OUT 39 36 OMCRH4 IOG5 IN 43 40 OUT 43 40 OMCRL5 GTCG1 LTCG1 LTCG5 IN 47 44 OUT 47 44 OMCRH5 IOG6 IN 51 48 OUT 51 48 OMCRL6 GTCG2 LTCG2 LTCG6 IN 55 52 OUT 55 52 OMCRH6 OG0 OUT 59 56 OMCRL7 GTCG3 LTC...

Page 1759: ...21 107 V1 1 2011 05 GPTA v5 V1 14 OG6 OUT 107 104 OMCRL13 GTCG1 LTCG1 LTCG5 OUT 111 108 OMCRH13 Table 21 11 Output Multiplexer Control Register Assignments cont d I O Group or Output Group Controlled by Multiplexer Control Register Selectable Groups via OMGng ...

Page 1760: ... low pin count packages not all I O groups may be routed to a pin Figure 21 69 On Chip Trigger and Gating Signal Multiplexer LTC Groups GTC Groups I O Groups OTMG3 IOG0 IOG1 IOG2 IOG3 8 GTCG0 GTC 07 00 GTCG1 GTC 15 08 GTCG2 GTC 23 16 GTCG3 GTC 31 24 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 OMG 00 OMG 02 OMG 03 OMG 10 OMG 11 OMG...

Page 1761: ...le behavior would occur On the other hand it is permissible for the output of a I O Group to be connected to more than one on chip trigger and gating signal TRIG The on chip trigger and gating multiplexer group configuration is based on the following principles Each OTMG is referenced with a single index variables g OTMGg Index g indicates the number of an On Chip Trigger and Gating Signal multipl...

Page 1762: ...ions within the on chip gating and trigger signal multiplexer of the GPTA0 unit Further sixteen on chip trigger and gating signals are assigned to the GPTA1 Therefore a total of 2 registers control the connections within the on chip gating and trigger signal multiplexer of the GPTA1 unit The OTMCR0 register control the OTMG output lines TRIG00 to TRIG07 The OTMCR1 register control the OTMG output ...

Page 1763: ...x 0 7 Selectable Groups via OMGng IOG0 OUT00 IN00 OTMCR0 TRIG0x GTCG0 LTCG0 LTCG4 IOG0 OUT02 IN01 OTMCR0 TRIG0x GTCG0 LTCG0 LTCG4 IOG1 OUT08 IN02 OTMCR0 TRIG0x GTCG1 LTCG1 LTCG5 IOG1 OUT10 IN03 OTMCR0 TRIG0x GTCG1 LTCG1 LTCG5 IOG2 OUT16 IN04 OTMCR0 TRIG0x GTCG2 LTCG2 LTCG6 IOG2 OUT19 IN05 OTMCR0 TRIG0x GTCG2 LTCG2 LTCG6 IOG3 OUT24 IN06 OTMCR0 TRIG0x GTCG3 LTCG3 LTCG7 IOG3 OUT27 IN07 OTMCR0 TRIG0x ...

Page 1764: ...lls each One special FPC INT group with eight outputs is established that combines the six FPC outputs and two internal input lines INT 1 0 as a group of GIMGs inputs LTC Input Multiplexer LTC Groups I O Groups MCA05974 GTC Groups 8 IOG0 IOG1 IOG2 IOG3 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 GIMG 00 GIMG 02 GIMG 03 GIMG 10 GIM...

Page 1765: ...to the GTC inputs with ascending index Example for GIMG23 see Figure 21 72 the outputs OUT0 to OUT7 are wired to the inputs of GTC16 to GTC23 A GTC input can be connected either to an I O group output or to an LTC output or to an FPC INT output This is guaranteed by the GIMG control register layout Otherwise short circuits and unpredictable behavior would occur In contrast it is permissible for an...

Page 1766: ...4 with the eight outputs of two I O group IOG2 and IOG6 two LTC groups LTCG2 and LTCG6 and the FPC INT group Figure 21 74 GTC Input Multiplexer Group Programmer s View The 1 level multiplexer is built up by five 8 1 multiplexers that are controlled in parallel by bit field GIMLn Bit field GIMGn controls the 2 level multiplexer and connects one of the 1 level multiplexer outputs to one of the GIMGn...

Page 1767: ...GIMG output lines 0 to 3 and the GIMCRH registers control the GIMG output lines 4 to 7 Table 21 13 lists all of the GTC Input Multiplexer Control Registers with its control functions Please note that all GTC Input Multiplexer Control Registers are not directly accessible but must be written or read using a FIFO array structure as described on Page 21 121 Table 21 13 GTC Input Multiplexer Control R...

Page 1768: ...ut Multiplexer I O Groups GTC Groups MCA05977 LTC Groups 8 IOG0 IOG1 IOG2 IOG3 LIMG 00 LIMG 02 LIMG 03 LIMG 10 LIMG 11 LIMG 12 LIMG 20 LIMG 21 LIMG 22 LIMG 01 8 IOG6 IOG5 IOG4 PDL 3 0 INT 3 0 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 LTCG4 LTC 39 32 LIMG 04 LIMG 06 LIMG 07 LIMG 05 LIMG 14 LIMG 15 LIMG 16 GTCG0 GTC 07 00 GTCG1 GT...

Page 1769: ... Multiplexer Group LIMG Within a I O group or GTC group the line or the output of the cell with the lowest index number is connected to LIMG input line IN0 The remaining lines cells or lines of a group are connected to LIMG input lines IN1 to IN7 with ascending index numbers At the clock group CLK0 is connected to IN0 and the remaining clock lines are connected to LIMG input lines IN1 to IN7 with ...

Page 1770: ... n and g LIMGng Index n is a group number I O groups IOG 3 0 have group number 0 I O groups IOG 6 4 have group number 1 Global Timer Cell Groups GTCG 3 0 have group number 2 clock bus lines CLK 7 0 have group number 3 and the PDL INT group has group number 4 Index g indicates the number of the LTC group g g 0 7 to which the outputs of the input multiplexer group LIMGng are connected The LTC input ...

Page 1771: ... Input Multiplexer Control Registers LIMCRL and LIMCRH see also Page 21 215 are assigned to each of the LTC groups Therefore in total sixteen registers control the connections within the LTC input multiplexer of the GPTA v5 module The LIMCRL registers control the LIMG output lines 0 to 3 and the GIMCRH registers control the LIMG output lines 4 to 7 Table 21 14 lists all LTC Input Multiplexer Contr...

Page 1772: ...H0 LTCG1 LTC 11 08 LIMCRL1 IOG1 IOG5 GTCG1 CLOCK PDL INT LTC 15 12 LIMCRH1 LTCG2 LTC 19 16 LIMCRL2 IOG2 IOG6 GTCG2 CLOCK PDL INT LTC 23 20 LIMCRH2 LTCG3 LTC 27 24 LIMCRL3 IOG3 GTCG3 CLOCK PDL INT LTC 31 28 LIMCRH3 LTCG4 LTC 35 32 LIMCRL4 IOG0 IOG4 GTCG0 CLOCK PDL INT LTC 39 36 LIMCRH4 LTCG5 LTC 43 40 LIMCRL5 IOG1 IOG5 GTCG1 CLOCK PDL INT LTC 47 44 LIMCRH5 LTCG6 LTC 51 48 LIMCRL6 IOG2 IOG6 GTCG2 CL...

Page 1773: ...eset the write cycle counter to 0 by writing MRACTL WCRES 1 3 Write sequentially the multiplexer control register contents one after the other 54 values into MRADIN starting with the register values for OTMCR1 OTMCR0 up to GIMCRH0 GIMCRL0 see Figure 21 78 After the first MRADIN write operation the contents for OTMCR1 is at FIFO position 1 With each following MRADIN write operation it becomes shift...

Page 1774: ...s will be forced to 0 When the array is disabled MRACTL MAEN 0 all cell inputs and outputs are disconnected from the GPIO lines and are driven with 0 Figure 21 78 GPTA v5 Multiplexer Array Control Register FIFO Structure Multiplexer Register Array FIFO MCA05980_mod OTMCR0 31 OTMCR1 OMCRL0 OMCRH0 MRADOUT 0 LIMCRL7 LIMCRH7 LIMCRL0 LIMCRH0 Output Multiplexer Control Registers LTC Input Multiplexer Co...

Page 1775: ...e Registers SRSSx and SRSCx are service request status flags that are set by hardware type h when the related event occurs Each GPTA v5 service request source has its own service request flag This flag is normally set by hardware but can be set and reset by software Each service request status flag can be read twice at the same bit location in the SRSCx register and in the SRSSx register and clear...

Page 1776: ...be enabled by the enable flag that is located in SRC register y Table 21 16 lists all of the service requests groups with its request sources Note that service requests of GTCs with an odd index number k can be individually redirected via register SRNR to a service request group that is assigned mainly to four LTCs Table 21 16 GPTA v5 Service Request Groups Service Request Group Number y Request S...

Page 1777: ...C28 LTC29 LTC30 LTC31 GTC152 30 LTC32 LTC33 LTC34 LTC35 GTC172 31 LTC36 LTC37 LTC38 LTC39 GTC192 32 LTC40 LTC41 LTC42 LTC43 GTC212 33 LTC44 LTC45 LTC46 LTC47 GTC232 34 LTC48 LTC49 LTC50 LTC51 GTC252 35 LTC52 LTC53 LTC54 LTC55 GTC272 36 LTC56 LTC57 LTC58 LTC59 GTC292 37 LTC60 LTC61 LTC62 LTC63 GTC312 1 Redirection bit SRNR GTCkR 0 k 01 03 05 27 29 31 2 Redirection bit SRNR GTCkR 1 k 01 03 05 27 29 ...

Page 1778: ...k Mode case PRESCALER_RISING if FPCk Rising_Edge then Prescaler endif break case PRESCALER_FALLING if FPCk Falling_Edge then Prescaler endif break case DELAYED_FILTER_BOTH Delayed_Filter break case IMMEDIATE_FILTER_BOTH case IMMEDIATE_FILTER_RISING case IMMEDIATE_FILTER_FALLING Immediate_Filter break case MIXED_FILTER_RISING_DELAYED if FPCk Signal_Filtered 0 then Delayed_Filter else Immediate_Filt...

Page 1779: ...nerate pulse on FPCk Signal_Output Transition FPCk Signal_Output Level FPCk Signal_Output Level FPCk Signal_Filtered FPCk Signal_Output Level endif FPCk Timer 0 else if FPCk Timer 0 then delay time is running if FPCk Rising_Edge is detected then edge detection done at clock input FPCk Rising_Edge_Glitch 1 else if FPCk Falling_Edge is detected then edge detection done at clock input FPCk Falling_Ed...

Page 1780: ...Ck Signal_Output Transition FPCk Signal_Output Level FPCk Signal_Input m if FPCk Compare_Value 0 or FPCk Mode IMMEDIATE_FILTER_RISING and FPCk Signal_Input m or FPCk Mode IMMEDIATE_FILTER_FALLING and FPCk Signal_Input m then by pass FPCk Signal_Filtered FPCk Signal_Output Level else start delay time FPCk Timer endif endif else if FPCk Timer FPCk Compare_Value then delay time is over FPCk Timer 0 F...

Page 1781: ... m SINm I Signal input selected by FPCk Input_Source FPCk Filter_Clock n CINn I Filter Clock selected by FPCk Clock_Source FPCk Rising_Edge RE L Signal coming from the edge detect FPCk Falling_Edge FE L Signal coming from the edge detect FPCk Signal_Filtered SF L Filtered output signal after delay time initialized to 0 at reset FPCk Signal_Output Transition FPCk Signal_Output Level SOTk SOLk O Tra...

Page 1782: ...XED_FILTER_RISING_DELAYED MIXED_FILTER_RISING_IMMEDIATE PRESCALER_RISING PRESCALER_FALLING FPCk Input_Source IPSk 3 Selects input signal FPCk Clock_Source CLKk 2 Selects FPC clock FPCk Rising_Edge_Glitch REGk 1 Bit is set when rising edge glitch occurs during filtering FPCk Falling_Edge_Glitch FEGk 1 Bit is set when falling edge glitch occurs during filtering FPCk Timer TIMk 16 Timer value FPCk Re...

Page 1783: ...tput Transition else x 1 S1 Level FPC3 Signal_Output Level S1 Transition FPC3 Signal_Output Transition S2 Level FPC4 Signal_Output Level S2 Transition FPC4 Signal_Output Transition S3 Level FPC5 Signal_Output Level S3 Transition FPC5 Signal_Output Transition endif if PDLx Three_Sensors_Enable then Three_Sensors else Two_Sensors endif if PDLx Mux then PDLx Signal_Output1 Level 1 if PDLx Signal_Forw...

Page 1784: ...and S1 Transition or S1 Level and S2 Level and S2 Transition then generate pulse on PDLx Signal_Forward else if S1 Level and S2 Level and S1 Transition or S1 Level and S2 Level and S2 Transition or S1 Level and S2 Level and S1 Transition or S1 Level and S2 Level and S2 Transition then generate pulse on PDLx Signal_Backward endif endif PDLx Signal_Output2 Level S3 Level PDLx Signal_Output2 Transiti...

Page 1785: ...l and S3 Level and S1 Transition or S1 Level and S2 Level and S3 Level and S3 Transition or S1 Level and S2 Level and S3 Level and S2 Transition or S1 Level and S2 Level and S3 Level and S1 Transition or S1 Level and S2 Level and S3 Level and S3 Transition or S1 Level and S2 Level and S3 Level and S2 Transition then generate pulse on PDLx Signal_Backward endif endif if S1 Level S2 Level and S1 Lev...

Page 1786: ...ansition PDLx Signal_Output1 Level SIT0 SIL0 SIT2 SIL2 O Transition Level of Output 1 signal going to DCM0 DCM2 PDLx Signal_Output2 Transition PDLx Signal_Output2 Level SIT1 SIL1 SIT3 SIL3 O Transition Level of Output 2 signal going to DCM1 DCM3 PDLx Signal_Forward F0 F1 O Forward signals to be counted by LTC PDLx Signal_Backward B0 B1 O Backward signals to be counted by LTC Name x 0 1 for PDL Sho...

Page 1787: ... 14 21 3 6 3 DCM Algorithm DCMk_Control_Logic to be performed every GPTA v5 clock Compare Add_Clock Compare Add_Clock Check_Input if DCMk Timer DCMk Capcom_Value then trig DCMk Service_Request_Compare endif if DCMk Clock_Request then Generate DCMk Signal_Output DCMk Clock_Request 0 endif ...

Page 1788: ...DCMk Timer endif endif if DCMk Clear_On_Rising_Edge then DCMk Timer 0 else DCMk Timer endif if DCMk Clock_On_Rising_Edge then Generate pulse on DCMk Signal_Output endif else falling edge trig DCMk Service_Request_Falling if DCMk Capture_On_Rising_Edge then DCMk Capture_Value DCMk Timer else if DCMk Capcom_Opposite then DCMk Capcom_Value DCMk Timer endif endif if DCMk Clear_On_Falling_Edge then DCM...

Page 1789: ...re_On_Rising_Edge RCAk 1 Capture into Capture_Value on rising edge DCMk Capcom_Opposite OCAk 1 Capture into Capcom_Value on opposite edge defined by RCAk DCMk Clear_On_Rising_Edge RZEk 1 Clear Timer on rising edge DCMk Clear_On_Falling_Edge FZEk 1 Clear Timer on falling edge DCMk Clock_On_Rising_Edge RCKk 1 Generate a single clock pulse on rising edge DCMk Clock_On_Falling_Edge FCKk 1 Generate a s...

Page 1790: ... then compensation finished or no automatic compensation Pll Counter_Mtick Pll Number_Mtick Pll Perfom_End 0 endif if Pll Counter_Mtick 0 and Pll Perform_End or Bit 24 of Pll Delta then output pulse is necessary generate pulse on Pll Signal_Output Pll Counter_Mtick if Pll Counter_Mtick 0 then trig Pll Service_Request_Trigger endif endif if Bit 24 of Pll Delta then delta is 0 Pll Delta Pll Delta Pl...

Page 1791: ... O Service request when Counter reaches zero Name Short Name PLL Size bits Function Pll Mux MUX 2 Selects the signal input for PLL Pll Automatic_End AEN 1 Performs the acceleration deceleration correction Pll Perform_End PEN 1 Makes it possible to decrement the Counter at full speed Pll Request_Enable REN 1 Allows a request when microtick counter reaches zero Pll Number_Mtick MTI 16 Number of micr...

Page 1792: ...if endif Name m 0 1 for GT p 0 to 7 for Clock Bus Short Name GT Used ILO Comment GTm Clock_In p CINmp I Input coming from clock bus GTm Timer_Greater_Equal_Comp TGEm O Timer is greater or equal GTm Timer_Event TEVm O Signal for timer change GTm Service_Request_Trigger SQTm O Service request line Name m 0 1 for GT Short Name GT Size bits Function GTm Run RUNm 1 Enables timer GTm Scale_Compare SCOm ...

Page 1793: ...f GTCk Cell_Enable then switch GTCk Mode case CAPTURE_T0 Capture 0 break case CAPTURE_T1 Capture 1 break case COMPARE_T0 Compare 0 break case COMPARE_T1 Compare 1 endswitch if GTCk One_Shot_Mode and GTCk Event then GTCk Cell_Enable 0 endif endif Manage_Mux if GTCk Signal_Input then trig GTCk Service_Request_Trigger GTCk X GTm Timer GTCk Event 1 else GTCk Event 0 endif Ck Event 0 ...

Page 1794: ...s and GTm Timer_Greater_Equal_Comp then if GTCk Capture_After_Compare then if GTCk Capture_Alternate_Timer then GTCk X GT m Timer else GTCk X GTm Timer endif endif trig GTCk Service_Request_Trigger GTCk Event 1 else GTCk Event 0 endif switch mode case 00B no change break case 01B toggle GTCk Data_Out GTCk Data_Out break case 10B clear GTCk Data_Out 0 break case 11B set GTCk Data_Out 1 break endswi...

Page 1795: ...trol_Mode 2 then bypass input link enabled GTCk Output_Mode_Out GTCk Output_Mode_In else bypass input link disabled GTCk Output_Mode_Out 00B endif endif else no local event if GTCk Output_Control_Mode 2 then input link enabled Set_Data_Out GTCk Output_Mode_In GTCk Output_Mode_Out GTCk Output_Mode_In else input link disabled Set_Data_Out 00B GTCk Output_Mode_Out 00B endif endif if GTCk Enable_Of_Ac...

Page 1796: ...t TEVm I Signal for timer change GTm Timer TIMm I Timer value GTCk Data_In DINk I Data input from input multiplexer GTCk Output_Mode_In M1Ik M0Ik I Link signals from preceding cell GTCk X_Write_Access XWA L Indicates that GTCk X was modified GTCk Event EVE L Local event GTCk Signal_Input INS L Qualified input signal GTCk Service_Request_Trigger SQSk O Service request line GTCk Data_Out DOUk O Data...

Page 1797: ...input pin Selects Compare Mode GTCk Input_Falling_Edge_Select Capture Mode GTCk Capture_After_Compare Compare Mode FEDk CACk 1 1 Selects falling edge of input pin Selects capture after compare GTCk Capture_Alternate_Timer Compare Mode CATk 1 Capture alternate global timer after compare GTCk Bypass BYPk 1 Local events bypassed for output link GTCk Enable_Of_Action EOAk 1 Enables cell on action comm...

Page 1798: ...e performed every GPTA v5 clock if LTCk Cell_Enable then switch LTCk Mode case TIMER_FREE_RUN LTCk Reset_Timer_Bit 0 Timer break case TIMER_RESET if LTCk Event_In then LTCk Reset_Timer_Bit 1 endif Timer break case CAPTURE Capture break case COMPARE Compare break endswitch if LTCk One_Shot_Mode and LTCk Event then LTCk Cell_Enable 0 endif endif Manage_Mux ...

Page 1799: ...w or software reset trig LTCk Service_Request_Trigger LTCk Event 1 else LTCk Event 0 endif if LTCk Signal_Input then if LTCk Reset_Timer_Bit then timer must be reset LTCk Reset_Timer_Bit 0 LTCk X 0xFFFF if LTCk Coherent_Update_Enable then LTCk Select_Line_Value LTCk Select_Line_Value LTCk Coherent_Update_Enable 0 endif else timer runs normally LTCk X endif endif LTCk Event_Out LTCk Event ...

Page 1800: ... else LTCk Event 0 endif LTCk Event_Out LTCk Event if LTCk Select_In and LTCk Select_On_High_Level or LTCk Select_In and LTCk Select_On_Low_Level then cell is active if LTCk X LTCk Y_In and LTCk X_Write_Access or LTCk Timer_Event_In then event trig LTCk Service_Request_Trigger LTCk Event 1 else LTCk Event 0 endif LTCk Event_Out LTCk Event else cell is inactive LTCk Event_Out LTCk Event_In endif ...

Page 1801: ... Y_Out LTCk Y_In LTCk Timer_Event_Out LTCk Timer_Event_In LTCk Select_Line_Value LTCk Select_In LTCk Select_Out LTCk Select_In endif if LTCk Event then local event Set_Data_Out LTCk Output_Control_Mode 1 0 if LTCk Bypass then no bypass LTCk Output_Mode_Out LTCk Output_Control_Mode 1 0 endif else no local event if LTCk Output_Control_Mode 2 input link enabled Set_Data_Out LTCk Output_Mode_In if LTC...

Page 1802: ...te_In endif else if LTCk Output_Control_Mode 2 then bypass input link enabled LTCk Output_Mode_Alternate_Out LTCk Output_Mode_In if LTCk Bypass then bypass LTCk Output_Mode_Out LTCk Output_Mode_In endif else bypass input link disabled LTCk Output_Mode_Alternate_Out 00B if LTCk Bypass then bypass LTCk Output_Mode_Out 00B endif endif endif if LTCk Enable_Of_Action and LTCk Output_Mode_In 1 or LTCk O...

Page 1803: ...al 21 151 V1 1 2011 05 GPTA v5 V1 14 Set_Data_Out mode switch mode case 00B no change break case 01B toggle LTCk Data_Out LTCk Data_Out break case 10B clear LTCk Data_Out 0 break case 11B set LTCk Data_Out 1 break endswitch LTCk Output_State LTCk Data_Out ...

Page 1804: ...Select signal from preceding cell LTCk X_Write_Access XWA L Indicates that LTCk X was modified LTCk Select_Line_Value SLV L Internal value for select line reset value 0 LTCk Signal_Input INS L Qualified input signal for Timer Mode and Capture Mode LTCk Reset_Timer_Bit RTM L Flip flop to reset timer on next clock LTCk Event EVE L Local event LTCk Data_Out DOUk O Data output for output multiplexer L...

Page 1805: ...k SOHk 1 1 Selects falling edge of input pin Enables compare on high level of select line LTCk Bypass Capture Mode Compare Mode BYPk 1 Local events bypassed for output link LTCk GlobalBypass GBYPk 1 Alternative output links forwarded to alternative output link LTCk Enable_Of_Action Capture Mode Compare Mode EOAk 1 Enables cell on action communicated via link LTCk Input_Line_Mode ILMk 1 Selects edg...

Page 1806: ... 14 21 3 6 8 LTC Algorithm for Cell 63 LTC63_Control_Logic to be performed every GPTA v5 clock Copy Copy Compare if LTC63 Cell_Enable then if LTC63 Signal_Input then LTC63 X LTC63 X_Shadow trig LTC63 Service_Request_Trigger if LTC63 One_Shot_Mode then LTC63 Cell_Enable 0 endif endif endif ...

Page 1807: ...hen LTC63 Y_Comp LTC63 Y_Rev else LTC63 Y_Comp LTC63 Y_In endif if LTC63 X LTC63 Y_Comp or LTC63 X FFFFH then output must be 1 LTC63 Data_Out 1 LTC63 Event_Out 0 else output must be 0 if LTC63 Data_Out 1 then falling edge on output trig LTC63 Service_Request_Trigger LTC63 Event_Out 1 else LTC63 Event_Out 0 endif LTC63 Data_Out 0 endif LTC63 Output_State LTC63 Data_Out endif ...

Page 1808: ...receding cell LTC63 Timer_Event_In TI63 I Signal for timer change from preceding cell LTC63 Y_Rev YR L Timer coming from preceding cell bit reversed LTC63 Y_Comp YC L Timer actually used for compare LTC63 X_Write_Access XWA L Indicates that LTC63 X was modified LTC63 Signal_Input INS L Qualified input signal LTC63 Data_Out DOU63 O Data output for output multiplexer LTC63 Service_Request_Trigger SQ...

Page 1809: ...TC63 Request_Enable REN63 2 Allows a request on compare or copy LTC63 Input_Rising_Edge_Select RED63 1 Selects rising edge of input pin LTC63 Input_Falling_Edge_Select FED63 1 Selects falling edge of input pin LTC63 Input_Line_Mode ILM63 1 Selects edge input line mode LTC63 Cell_Enable CEN63 1 Cell enable state for copy LTC63 Output_State OUT63 1 Read value of Data_Out LTC63 X X63 16 Compare value...

Page 1810: ...lemented for getting a GPTA v5 unit into operation Table 21 17 Software Tasks Controlling a GPTA v5 Unit GPTA v5 Shell Initialization GPTA v5 Module Clock Enable Fractional Divider Setting Unit Enable Configuration of Interrupt Handling GPTA v5 Kernel Initialization FPC PDL Selection of Operating Mode Prescaler Filter or Feed Through Selection of Operating Mode Phase Discriminator or Feed Through ...

Page 1811: ...n of Operating Mode Timer Capture or Compare Configuration of the Multiplexer Array to link GTC and LTC data outputs inputs to external Port Pins or other cells by writing the Multiplexer Register Array FIFO Configuration of the On chip Trigger and Gating Signal Multiplexer Array to link GTC and LTC data outputs to on chip modules by writing the Multiplexer Register Array FIFO Selection of Trigger...

Page 1812: ...PTA0 F000 1800H F000 1FFFH LTCA2 F000 2800H F000 2FFFH 1 k 0 5 2 k 0 3 3 k 0 1 4 k 00 31 5 k 00 63 6 n 0 3 7 g 0 1 8 g 0 13 9 g 0 7 10 g 0 3 MCA05982_mod2 FPCTIMk Control Registers Interrupt IOLS Registers Data Registers DCMTIMk DCMCAVk SRSCn DCMCOVk PLLMTI PLLSTP PLLCNT PLLREV PLLDTR GTTIMk GTREVk GTCXRk LTCXRk SRSSn FPCSTAT FPCCTRk PDLCTR DCMCTRk PLLCTR CKBCTR GTCTRk GTCCTRk LTCCTRk SRNR MRACTL ...

Page 1813: ...quest State Set Register 0 014H U SV U SV 3 Page 21 221 SRSC1 Service Request State Clear Register 1 018H U SV U SV 3 Page 21 222 SRSS1 Service Request State Set Register 1 01CH U SV U SV 3 Page 21 223 SRSC2 Service Request State Clear Register 2 020H U SV U SV 3 Page 21 224 SRSS2 Service Request State Set Register 2 024H U SV U SV 3 Page 21 225 SRSC3 Service Request State Clear Register 3 028H U ...

Page 1814: ...Register k k 0 3 0084H k 16 U SV U SV 3 Page 21 174 DCMCAVk Duty Cycle Measurement Capture Register k k 0 3 0088H k 16 U SV U SV 3 Page 21 175 DCMCOVk Duty Cycle Measurement Capture Compare Register k k 0 3 008CH k 16 U SV U SV 3 Page 21 175 PLLCTR Phase Locked Loop Control Register 00C0H U SV U SV 3 Page 21 176 PLLMTI Phase Locked Loop Micro Tick Register 00C4H U SV U SV 3 Page 21 177 PLLCNT Phas...

Page 1815: ...31 0100H k 8 U SV U SV 3 Page 21 184 Page 21 186 GTCXRk Global Timer Cell X Register k k 00 31 0104H k 8 U SV U SV 3 Page 21 188 LTCCTRk Local Timer Cell Control Register k k 00 62 0200H k 8 U SV U SV 3 Page 21 189 Page 21 194 Page 21 197 LTCXRk Local Timer Cell X Register k k 00 62 0204H k 8 U SV U SV 3 Page 21 201 LTCCTR63 Local Timer Cell Control Register 63 03F8H U SV U SV 3 Page 21 200 LTCXR6...

Page 1816: ...Group g g 0 13 n a n a 3 Page 21 208 GIMCRLg Input Multiplexer Control Register for Lower Half of GTC Group g g 0 3 n a n a 3 Page 21 211 GIMCRHg Input Multiplexer Control Register for Lower Half of GTC Group g g 0 3 n a n a 3 Page 21 213 LIMCRLg Input Multiplexer Control Register for Upper Half of LTC Group g g 0 7 not directly address able see Page 21 121 n a n a 3 Page 21 215 LIMCRLg Input Mult...

Page 1817: ... sets a request state bit between the read and the write of the read modify write sequence For bit protected bits it is guaranteed that a hardware setting operation always has priority Thus no hardware triggered events are lost Bits with bit protection are marked in the corresponding bit descriptions ...

Page 1818: ...cation Register 08H Reset Value 002A C0XXH 31 16 15 8 7 0 MOD_NUMBER MOD_TYPE MOD_REV r r r Field Bits Type Description MOD_REV 7 0 r Module Revision Number MOD_REV defines the Module revision number The value of a module revision starts with 01H first revision GPTAv5 will start with module revision 05H MOD_TYPE 15 8 r Module Number Value This bit field defines the module as a 32 bit module C0H MO...

Page 1819: ...REG 1 REG 0 r rwh rwh rwh rwh rwh rwh r rwh rwh rwh rwh rwh rwh Field Bits Type Description REGk k 0 5 k rwh Rising Edge Glitch Flag for FPCk 0B No rising edge of glitch detected during filtering 1B Rising edge of glitch detected during filtering Bits REGk are bit protected see Section 21 4 2 FEGk k 0 5 k 8 rwh Falling Edge Glitch Flag for FPCk 0B No falling edge of glitch detected during filterin...

Page 1820: ...hold value that is compared with the 16 bit timer value FPCTIMk TIM MOD 18 16 rw Operation Mode Selection for FPCk 000B Delayed Debounce Filter Mode on both edges 001B Immediate Debounce Filter Mode on both edges 010B Rising edge Immediate Debounce Filter Mode falling edge no filtering 011B Rising edge no filtering falling edge Immediate Debounce Filter Mode 100B Rising edge Delayed Debounce Filte...

Page 1821: ...w Clock Selection for FPCk CLK selects the clock signal used for edge detection 00B CIock input line 0 selected GPTA v5 module clock fGPTA 01B Clock bus line 1 selected local PLL clock 10B Clock bus line 2 selected prescaled GPTA v5 module clock fGPTA or PLL clock from other unit or DCM 3 clock 11B Clock bus line 3 selected DCM 2 clock or PLL clock of other unit or uncompensated PLL clock or uncom...

Page 1822: ...GPTA v5 V1 14 GPTA0_FPCTIMk k 0 5 GPTA0 Filter and Prescaler Cell Timer Register k 048H k 8H 4H Reset Value 0000 0000H 31 16 15 0 0 TIM r rwh Field Bits Type Description TIM 15 0 rwh Timer Value of Filter and Prescaler Cell k 0 31 16 r Reserved Read as 0 should be written with 0 ...

Page 1823: ...r PDL0 0B PDL0 operates in 2 Sensor Mode and DCM1 cell input is driven by fed through FPC2 output lines 1B PDL0 operates in 3 Sensor Mode and DCM1 cell input is provided with PDL0 error information ERR0 2 rwh Error Flag for PDL0 0B No error has occurred 1B Error detected in 3 Sensor Mode all PDL0 input signals are simultaneously provided with high or low level Bit ERR0 is bit protected see Page 21...

Page 1824: ...4 ERR1 6 rwh Error Flag for PDL1 0B No error has occurred 1B Error detected in 3 Sensor Mode all PDL1 input signals are simultaneously provided with high or low level Bit ERR1 is bit protected see Page 21 167 0 3 31 7 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1825: ...e register on a falling input signal edge 1B Timer contents are copied to capture register on a rising input signal edge OCA 1 rw Trigger Source for Capture Compare Register Update 0B Capture Compare register DCMCOVk is not affected 1B Timer contents are copied to DCMCOVk capture compare register on the opposite edge selected by RCAk RZE 2 rw Timer Reset on Rising Edge 0B Timer is not affected 1B ...

Page 1826: ... is not affected 1B Interrupt request is set on rising input signal edge FRE 8 rw Interrupt Request on Falling Edge 0B Interrupt request is not affected 1B Interrupt request is set on falling input signal edge CRE 9 rw Interrupt Request on Compare Event 0B Interrupt request is not affected 1B Interrupt request is set when the timer matches capture compare register DCMCOVk 0 31 10 r Reserved Read a...

Page 1827: ...23 0 0 CAV r rwh Field Bits Type Description CAV 23 0 rwh Capture Value of DCMk 0 31 24 r Reserved Read as 0 should be written with 0 GPTA0_DCMCOVk k 0 3 GPTA0 Duty Cycle Measurement Capture Compare Register k 08CH k 10H Reset Value 0000 0000H 31 24 23 0 0 COV r rwh Field Bits Type Description COV 23 0 rwh Capture Compare Register Value of DCMk 0 31 24 r Reserved Read as 0 should be written with 0...

Page 1828: ...put AEN 2 rw Automatic End Mode Enable With the Automatic End Mode compensation of input signal s period length variation acceleration deceleration is requested 0B Automatic End Mode is disabled 1B Automatic End Mode is enabled PEN 3 rwh Unexpected Period End Behavior 0B Counter decrements with constant frequency 1B Counter is allowed to decrement with fGPTA frequency in case of an input signal pe...

Page 1829: ...TI 15 0 rw Microtick Value Number of output pulses to be generated within one input signal period 0 31 16 r Reserved Read as 0 should be written with 0 GPTA0_PLLSTP GPTA0 Phase Locked Loop Step Register 0CCH Reset Value 0000 0000H 31 16 15 0 0 STP r rw Field Bits Type Description STP 15 0 rw Step Value Number of output pulses to be generated within one input signal period 2 complement data format ...

Page 1830: ...put pulses to be generated 0 31 16 r Reserved Read as 0 should be written with 0 GPTA0_PLLREV GPTA0 Phase Locked Loop Reload Register 0D0H Reset Value 0000 0000H 31 24 23 0 0 REV r rw Field Bits Type Description REV 23 0 rw Reload Value Reload value calculated by a subtraction of the number of output pulses to be generated within one input signal period from the input signal s period length measur...

Page 1831: ...ed Loop Delta Register 0D4H Reset Value 0000 0000H 31 25 24 0 0 DTR r rwh Field Bits Type Description DTR 24 0 rwh Delta Register Value Internal register used to store intermediate results for output pulse generation Do not write to this register while PLL is running 0 31 25 r Reserved Read as 0 should be written with 0 ...

Page 1832: ...e which is used as TGE flag 0000B 10th bit is used as TGE flag 0001B 11th bit is used as TGE flag B 1110B 24th bit is used as TGE flag 1111B 25th bit is used as TGE flag MUX 6 4 rw Timer Clock Selection One of eight available clock bus lines is selected as the timer GTk clock 000B Clock bus line CLK0 selected 001B Clock bus line CLK1 selected 010B Clock bus line CLK2 selected 011B Clock bus line C...

Page 1833: ... rwh Field Bits Type Description TIM 23 0 rwh Timer Value of Global Timer k 0 31 24 r Reserved Read as 0 should be written with 0 GPTA0_GTREVk k 0 1 GPTA0 Global Timer Reload Value Register k 0E4H k 10H Reset Value 0000 0000H 31 24 23 0 0 REV r rwh Field Bits Type Description REV 23 0 rw Reload Value of Global Timer k Reload value for timer GTk after an overflow 0 31 24 r Reserved Read as 0 should...

Page 1834: ...D CLK2 is provided with the GPTA v5 module clock fGPTA divided by 2DFA02 1D CLK2 is provided with the GPTA v5 module clock fGPTA divided by 2DFA02 13D CLK2 is provided with the GPTA v5 module clock fGPTA divided by 2DFA02 14D CLK2 is driven by PLL clock of other GPTA v5 unit 15D CLK2 is driven by DCM3 output DFA04 7 4 rw Clock Line 4 Driving Source Selection 0D CLK4 is provided with the GPTA v5 mo...

Page 1835: ...ivided by 2DFA07 14D CLK7 is provided with the GPTA v5 module clock fGPTA divided by 2DFA07 15D CLK7 is driven by FPC4 output DFA03 17 16 rw Clock Line 3 Driving Source Selection 0D CLK3 is driven by DCM2 output 1D CLK3 is driven by PLL clock of other GPTA v5 unit 2D CLK3 is driven by uncompensated PLL clock 3D CLK3 is driven by uncompensated PLL clock of other GPTA v5 unit DFALTC 20 18 rw Dividin...

Page 1836: ...erates in Capture Mode hooked to GT1 10B GTCk operates in Compare Mode hooked to GT0 11B GTCk operates in Compare Mode hooked to GT1 OSM 2 rw One Shot Mode Enable 0B GTCk is continuously enabled 1B GTCk is enabled for one event only REN 3 rw Interrupt Request Enable 0B Service request is disabled 1B Service request line SQSk is activated when a capture or compare event has occurred RED 4 rw Input ...

Page 1837: ...is currently enabled for local events OCM 13 11 rw Output Control Mode Select 000B Current state of GTCkOUT output line is hold 001B Current state of GTCkOUT output line is toggled by an internal GTCk event otherwise hold 010B GTCkOUT output line is forced to 0 by an internal GTCk event otherwise hold 011B GTCkOUT output line is forced to 1 by an internal GTCk event otherwise hold 1XXB GTCkOUT out...

Page 1838: ...10B GTCk operates in Compare Mode hooked to GT0 11B GTCk operates in Compare Mode hooked to GT1 OSM 2 rw One Shot Mode Enable 0B GTCk is continuously enabled 1B GTCk is enabled for one event only REN 3 rw Interrupt Request Enable 0B Service request is disabled 1B Service request line SQSk is activated when a capture or compare event has occurred GES 4 rw Greater Equal Select 0B An equal compare is...

Page 1839: ...ode is switched to Timer Mode CEN 10 rh Cell Enable 0B GTCk is currently disabled for local events 1B GTCk is currently enabled for local events OCM 13 11 rw Output Control Mode Select 000B Current state of GTCkOUT output line is hold 001B Current state of GTCkOUT output line is toggled by an internal GTCk event otherwise hold 010B GTCkOUT output line is forced to 0 by an internal GTCk event other...

Page 1840: ...T timer matches and or exceeds the capture compare register contents Write protection is released after a software access to register GTCXRk 0 9 31 16 r Reserved Read as 0 should be written with 0 GPTA0_GTCXRk k 00 31 GPTA0 Global Timer Cell X Register k 104H k 8H Reset Value 0000 0000H 31 24 23 0 0 X r rwh Field Bits Type Description X 23 0 rwh Capture Compare Register Contents of GTCk 0 31 24 r ...

Page 1841: ...ion MOD 1 0 rw Mode Control Bits 00B LTCk operates in Capture Mode 01B LTCk operates in Compare Mode 10B LTCk operates in Free Running Timer Mode 11B LTCk operates in reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has...

Page 1842: ... GPTA v5 module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event CUD 9 rwh Coherent Update Enable 0B Select output SO is not toggled on timer reset overflow 1B Select output SO is toggled on next timer reset overflow When CUD is set by software it remains set until the next timer reset overflow LTCk reset event occ...

Page 1843: ...d by M1I M0I interface lines OIA 14 rw Output Immediate Action 0B No immediate action required 1B Action defined by bit field OCM must be performed immediately OIA is always read as 0 OUT 15 rh Output State 0B LTCkOUT output line is 0 1B LTCkOUT output line is 1 GBYP 16 rw Global Bypass 0B M3O M2O lines are affected by M1I M0I lines 1B M3O M2O lines are affected by M3I M2I lines 0 31 17 r Reserved...

Page 1844: ... capture event has occurred compare event has occurred timer overflow has happened depending on the operation mode selected by bit field MOD PEN 4 rw LTC Prescaler Enable 0B LTC Prescaler Mode is disabled 1B LTC Prescaler Mode with LTC prescaler clock LTCPRE is enabled AIL 5 rw Active Input Level Select 0B Input signal is active high 1B Input signal is active low SLO 6 rwh Select Line Output 0B St...

Page 1845: ...nd when mode is switched to another mode than Reset Timer Mode This bit can only be set in Reset Timer Mode If bits CUD and CUDCLR are both written with 1 bit CUD will be set CUDCLR is always read as 0 CEN 10 rh Cell Enable 0B LTCk is currently disabled for local events 1B LTCk is currently enabled for local events OCM 13 11 rw Output Control Mode Select 000B Current state of LTCkOUT output line i...

Page 1846: ...ontrol Register k Capture Mode 200H k 8H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 G BYP r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUT OIA OCM CEN SLL ILM EOA BYP FED RED REN OSM MOD rh rw rw rh rh rw rwh rw rw rw rw rw rw Field Bits Type Description MOD 1 0 rw Mode Control Bits 00B LTCk operates in Capture Mode 01B LTCk operates in Compare Mode 10B LTCk operates in...

Page 1847: ...B M1O M0O lines are affected only by M1I M0I GBYP 0 or M2I M2I GBYP 1 lines This bit is cleared if mode is switched to Timer Mode OCM2 must be set in any case to enable reaction on M1I M0I change EOA 7 rwh Enable On Action 0B LTCk is enabled for local events 1B LTCk is disabled for local events On an event on the communication link via M0I M1I lines EOA will be cleared and local events will be ena...

Page 1848: ...1B LTCkOUT output line is forced to 1 by an internal LTCk event otherwise hold 1XXB LTCkOUT output line state is affected by an internal LTCk event and or by an operation occurred in an adjacent LTCk cell reported by M1I M0I interface lines OIA 14 rw Output Immediate Action 0B No immediate action required 1B Action defined by bit field OCM must be performed immediately OIA is always read as 0 OUT ...

Page 1849: ...B LTCk operates in Free Running Timer Mode 11B LTCk operates in reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has occurred compare event has occurred timer overflow has happened depending on the operation mode select...

Page 1850: ... in Level Sensitive Mode In case of full speed GPTA v5 module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event SLL 9 rh Select Line Level 0B Current state of select input SI is 0 1B Current state of select input SI is 1 CEN 10 rh Cell Enable 0B LTCk is currently disabled for local events 1B LTCk is currently enable...

Page 1851: ...e performed immediately OIA is always read as 0 OUT 15 rh Output State 0B LTCkOUT output line is 0 1B LTCkOUT output line is 1 GBYP 16 rw Global Bypass 0B M3O M2O lines are affected by M1I M0I lines 1B M3O M2O lines are affected by M3I M2I lines 0 31 17 r Reserved Read as 0 should be written with 0 1 To enable Compare Mode in all cases SOL and SOH bits must be set to 1 Field Bits Type Description ...

Page 1852: ...Copy 0B Shadow register copy is continuously enabled 1B Shadow register copy is enabled for one event only REN 3 2 rw Request Enable 00B Service request SQT63 is disabled 01B Service request SQT63 is generated when a compare event has occurred 10B Service request SQT63 is generated when a shadow register copy event has occurred 11B Reserved RED 4 rw Rising Edge Select for Shadow Register Copy 0B S...

Page 1853: ...ister copy is currently disabled 1B Shadow register copy is currently enabled OUT 15 rh Output State 0B LTC63OUT output line is 0 1B LTC63OUT output line is 1 0 7 6 9 14 11 31 16 r Reserved Read as 0 should be written with 0 GPTA0_LTCXRk k 00 62 GPTA0 Local Timer Cell X Register k 204H k 8H Reset Value 0000 0000H 31 16 15 0 0 X r rwh Field Bits Type Description X 15 0 rwh Local Timer Data Register...

Page 1854: ... v5 V1 14 GPTA0_LTCXR63 GPTA0 Local Timer Cell X Register 63 3FCH Reset Value 0000 0000H 31 16 15 0 XS X rw rwh Field Bits Type Description X 15 0 rwh Compare Register Value Software write operations has priority above a simultaneous hardware update XS 31 16 rw Shadow Register Value ...

Page 1855: ...he Multiplexer Register Array Control register controls the operation of the Multiplexer Register Array FIFO GPTA0_MRACTL GPTA0 Multiplexer Register Array Control Register 038H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FIFOFILLCNT 0 FIFO FUL L WCR ES MA EN r r r r w rw Field Bits Type Description MAEN 0 rw Multiplexer Array E...

Page 1856: ...IFOFULL 2 r FIFO Full Status 0B FIFO not completely written write access to MRADIN allowed 1B FIFO completely written write access to MRADIN ignored Must be re enabled via WCRES before array can be re initialized FIFOFILLCNT 13 8 r FIFO Fill Count This bit field shows the current contents of the write cycle counter 0 7 3 31 14 r Reserved Read as 0 should be written with 0 GPTA0_MRADIN GPTA0 Multip...

Page 1857: ...32 bit wide 8 bit and 16 bit accesses are ignored without any bus error GPTA0_MRADOUT GPTA0 Multiplexer Register Array Data Out Register 040H Reset Value 0000 0000H 31 0 DATAOUT rh Field Bits Type Description DATAOUT 31 0 rh FIFO Read Data This register contains the FIFO read data as assigned for the Output Multiplexer Control Registers and the Input Multiplexer Control Registers ...

Page 1858: ...d to IOG 6 0 and OMCRL 13 7 OMCRH 13 7 are assigned to OG 6 0 OMCRL controls the connections of group pins 0 to 3 OMCRH controls the connections of group pins 4 to 7 GPTA0_OMCRLg g 0 13 GPTA0 Output Multiplexer Control Register for Lower Half of Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 OMG3 0 OML3 0 OMG2 0 OML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5...

Page 1859: ...lected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG0 OMG1 OMG2 OMG3 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is connected to input n of I O Group g or Output group g 7 X00B OMG0g selected X01B OMG1g selected X10B OMG2g selected All other combinations are reserved If a reserved combination of OMGn value...

Page 1860: ...be selected by bit field OMGn for OMG output n 000B OMG input IN0 selected 001B OMG input IN1 selected 010B OMG input IN2 selected 011B OMG input IN3 selected 100B OMG input IN4 selected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG4 OMG5 OMG6 OMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is connected t...

Page 1861: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 209 V1 1 2011 05 GPTA v5 V1 14 0 3 7 11 15 19 23 27 31 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1862: ... OTM7 0 OTM6 0 OTM5 0 OTM4 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OTM3 0 OTM2 0 OTM1 0 OTM0 r rw r rw r rw r rw Field Bits Type Description OTMn n 0 7 4 x n 4 4 x n rw Multiplexer Line Selection This bit field selects the input line of a OMG that can be selected by bit field OMGn for OMG output n 000B OTMG input IN0 selected 001B OTMG input IN1 selected 010B OTMG input IN2 sel...

Page 1863: ...egister for Lower Half of GTC Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GIM EN3 GIMG3 0 GIML3 GIM EN2 GIMG2 0 GIML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIM EN1 GIMG1 0 GIML1 GIM EN0 GIMG0 0 GIML0 rw rw r rw rw rw r rw Field Bits Type Description GIML0 GIML1 GIML2 GIML3 2 0 10 8 18 16 26 24 rw Multiplexer Line Selection This bit field selec...

Page 1864: ... of GTC group g 000B GIMG0g selected 001B GIMG1g selected reserved for g 3 010B GIMG2g selected 011B GIMG3g selected 100B GIMG4g selected All other combinations are reserved GIMEN0 GIMEN1 GIMEN2 GIMEN3 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by GIMLn and GIMGn 0 3 11 19 27 r Reserved Read as 0 should be written...

Page 1865: ...can be selected by bit field GIMGn for GIMG output n 000B GIMG input IN0 selected 001B GIMG input IN1 selected 010B GIMG input IN2 selected 011B GIMG input IN3 selected 100B GIMG input IN4 selected 101B GIMG input IN5 selected 110B GIMG input IN6 selected 111B GIMG input IN7 selected GIMG4 GIMG5 GIMG6 GIMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the GIMGng w...

Page 1866: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 214 V1 1 2011 05 GPTA v5 V1 14 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1867: ...ntrol Register for Lower Half of LTC Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LIM EN3 LIMG3 0 LIML3 LIM EN2 LIMG2 0 LIML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIM EN1 LIMG1 0 LIML1 LIM EN0 LIMG0 0 LIML0 r rw r rw r rw r rw Field Bits Type Description LIML0 LIML1 LIML2 LIML3 2 0 10 8 18 16 26 24 rw Multiplexer Line Selection This bit field ...

Page 1868: ... of LTC group g 000B LIMG0g selected 001B LIMG1g selected reserved for g 3 010B LIMG2g selected 011B LIMG3g selected 100B LIMG4g selected All other combinations are reserved LIMEN0 LIMEN1 LIMEN2 LIMEN3 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3 11 19 27 r Reserved Read as 0 should be written...

Page 1869: ...can be selected by bit field LIMGn for LIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected LIMG4 LIMG5 LIMG6 LIMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the LIMGng w...

Page 1870: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 218 V1 1 2011 05 GPTA v5 V1 14 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1871: ...a 1 to the corresponding bit location in the SRSSx registers Writing a 0 has no effect GPTA0_SRSC0 GPTA0 Service Request State Clear Register 0 010H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GT 01 GT 00 PLL DCM 03C DCM 03F DCM 03R DCM 02C DCM 02F DCM 02R DCM 01C DCM 01F DCM 01R DCM 00C DCM 00F DCM 00R r rwh rwh rwh rwh rwh rw...

Page 1872: ...rvice is requested 1B Service is requested due to a GT0 timer overflow GT01 14 rwh1 GT1 Timer Service Request State 0B No service is requested 1B Service is requested due to a GT1 timer overflow 0 31 15 r Reserved Read as 0 should be written with 0 1 Writing an one to a set bit clears the bit All other write operations have no effect 2 k 0 3 k 0 refers to DCM00R DCM00F or DCM00C k 1 refers to DCM0...

Page 1873: ...cted on DCMk input signal line DCM00F DCM01F DCM02F DCM03F 1 4 7 10 rwh1 DCMk2 Falling Edge Event Service Request State 0B No service is requested 1B Service is requested due to a falling edge detected on DCMk input signal line DCM00C DCM01C DCM02C DCM03C 2 5 8 11 rwh1 DCMk2 Compare Event Service Request State 0B No service is requested 1B Service is requested due to a compare event occurred in DC...

Page 1874: ...20 19 18 17 16 GTC 31 GTC 30 GTC 29 GTC 28 GTC 27 GTC 26 GTC 25 GTC 24 GTC 23 GTC 22 GTC 21 GTC 20 GTC 19 GTC 18 GTC 17 GTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 15 GTC 14 GTC 13 GTC 12 GTC 11 GTC 10 GTC 09 GTC 08 GTC 07 GTC 06 GTC 05 GTC 04 GTC 03 GTC 02 GTC 01 GTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh...

Page 1875: ... rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 15 GTC 14 GTC 13 GTC 12 GTC 11 GTC 10 GTC 09 GTC 08 GTC 07 GTC 06 GTC 05 GTC 04 GTC 03 GTC 02 GTC 01 GTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description GTCk k 00 31 k rwh1 1 Writing a one to a cleared bit sets the bit All other write operations have no effe...

Page 1876: ...TC 18 LTC 17 LTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 15 LTC 14 LTC 13 LTC 12 LTC 11 LTC 10 LTC 09 LTC 08 LTC 07 LTC 06 LTC 05 LTC 04 LTC 03 LTC 02 LTC 01 LTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 00 31 k rwh1 1 Writing an one to a set bit clears the bit All other...

Page 1877: ...18 LTC 17 LTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 15 LTC 14 LTC 13 LTC 12 LTC 11 LTC 10 LTC 09 LTC 08 LTC 07 LTC 06 LTC 05 LTC 04 LTC 03 LTC 02 LTC 01 LTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 00 31 k rwh1 1 Writing a one to a cleared bit sets the bit All other w...

Page 1878: ... 50 LTC 49 LTC 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 47 LTC 46 LTC 45 LTC 44 LTC 43 LTC 42 LTC 41 LTC 40 LTC 39 LTC 38 LTC 37 LTC 36 LTC 35 LTC 34 LTC 33 LTC 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 32 63 k 32 rwh1 1 Writing an one to a set bit clears the bit All othe...

Page 1879: ...0 LTC 49 LTC 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 47 LTC 46 LTC 45 LTC 44 LTC 43 LTC 42 LTC 41 LTC 40 LTC 39 LTC 38 LTC 37 LTC 36 LTC 35 LTC 34 LTC 33 LTC 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 32 63 k 32 rwh1 1 Writing a one to a cleared bit sets the bit All other...

Page 1880: ...0 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 31R GTC 29R GTC 27R GTC 25R GTC 23R GTC 21R GTC 19R GTC 17R GTC 15R GTC 13R GTC 11R GTC 09R GTC 07R GTC 05R GTC 03R GTC 01R rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description GTC01R GTC03R GTC05R GTC07R GTC09R GTC11R GTC13R GTC15R GTC17R GTC19R GTC21R GTC23R GTC25R GTC27R ...

Page 1881: ... an I O Line Sharing Block that controls the LTC connections to the I O lines and output lines I O lines are supposed to be connected to I O port lines while the output lines are typically connected to a MSC interface that is especially able to control external power devices via a serial connection The LTCs can be further connected to input signals of an external clock bus and input lines coming e...

Page 1882: ...nputs and other on chip peripherals The LTCA unit provides a total of 32 input lines and 64 output lines that are connected to four I O groups IOG 3 0 and four output groups OG 6 3 Figure 21 82 Input Output Line Sharing Block Overview The LTCA I O Line Sharing Block makes the following two selections LTC output multiplexer selection LTC input multiplexer selection To choose these selection the inp...

Page 1883: ... PDL 3 0 together with the inputs INT 3 0 The clock group is a logical group that combines the eight LTCA unit clock inputs CLK 7 0 MCA05985_TC1767 PDL0 PDL1 PDL2 PDL3 INT0 INT1 INT2 INT3 PDL INT Group INT2 INT3 INT0 INT1 PDL2 PDL3 PDL0 PDL1 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 Clock Group CLK6 CLK7 CLK4 CLK5 CLK2 CLK3 CLK0 CLK1 LTC24IN LTC25IN LTC26IN LTC27IN LTC28IN LTC29IN LTC30IN LTC31IN Ex...

Page 1884: ...ne Cell Assignment Group Unit Cell Line Input Output LTC Groups LTCG0 LTC 07 00 LTC 07 00 IN LTC 07 00 OUT LTCG1 LTC 15 08 LTC 15 08 IN LTC 15 08 OUT LTCG2 LTC 23 16 LTC 23 16 IN LTC 23 16 OUT LTCG3 LTC 31 24 LTC 31 24 IN LTC 31 24 OUT I O Groups IOG0 IN 07 00 OUT 07 00 IOG1 IN 15 08 OUT 15 08 IOG2 IN 23 16 OUT 23 16 IOG3 IN 31 24 OUT 31 24 Output Groups OG3 OUT 87 80 OG4 OUT 95 88 OG5 OUT 103 96 ...

Page 1885: ...put groups The LTCs are grouped into four LTC groups LTCG 3 0 with 8 cells each In the same way I O groups and output groups are grouped into 8 groups four I O groups and four output groups with 8 lines each LTC Grou ps MCA05986_TC1767 I O Groups IOG0 IOG1 IOG2 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 OMG 10 OMG 11 OMG 12 Output Groups IOG3 OG31 OG4 OG5 OMG 1A OMG 1B OMG 1C ...

Page 1886: ... of an LTC cell to be connected to more than one input of an I O or output group The output multiplexer group configuration is based on the following principles Each OMG is referenced with two index variables n and g OMGng Index n is a group number Local Timer Cell Groups LTCG 3 0 have the group number 1 Index g indicates the number of an I O or output group g g 0 7D to which the outputs of the ou...

Page 1887: ...sponding OMG output will be held at a low level Two Output Multiplexer Control Registers OMCRL and OMCRH see also Page 21 206 are assigned to each of the I O or output groups Therefore in total 16 registers control the connections within the output multiplexer of the LTCA unit The OMCRL registers control the OMG output lines 0 to 3 and the OMCRH registers control the OMG output lines 4 to 7 Table ...

Page 1888: ...CRL0 LTCG0 IN 07 04 OUT 07 04 OMCRH0 IOG1 IN 11 08 OUT 11 08 OMCRL1 LTCG1 IN 15 12 OUT 15 12 OMCRH1 IOG2 IN 19 16 OUT 19 16 OMCRL2 LTCG2 IN 23 20 OUT 23 20 OMCRH2 IOG3 IN 27 24 OUT 27 24 OMCRL3 LTCG3 IN 31 28 OUT 31 28 OMCRH3 OG3 OUT 83 80 1 2 1 OUT 79 32 is not available 2 OG0 OG2 is not available OMCRL10 LTCG2 OUT 87 84 OMCRH10 OG4 OUT 91 88 OMCRL11 LTCG3 OUT 95 92 OMCRH11 OG5 OUT 99 96 OMCRL12 ...

Page 1889: ...put lines or the four PDL input lines PDL 3 0 and the four internal input lines INT 3 0 with the 64 4 8 LTC inputs organized in four LTC groups Figure 21 87 LTC Input Multiplexer of LTCA LTC Input Multiplexer I O Grou ps MCA05989_TC1767 LTC Groups 8 IOG0 IOG1 IOG2 IOG3 LIMG 00 LIMG 02 LIMG 03 LIMG 01 PDL 3 0 INT 3 0 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 CLK 7 0 LIMG 40 LI...

Page 1890: ...ut lines IN1 to IN7 with ascending index numbers At the clock group CLK0 is connected to IN0 and the remaining clock lines are connected to LIMG input lines IN1 to IN7 with ascending index numbers At the PDL INT group PDL 3 0 see Page 21 22 are connected to IN 3 0 and INT 3 0 are connected to IN 7 4 Example for LIMG04 see Figure 21 87 the I O lines of IOG0 IN00 up to IN07 are wired to its input li...

Page 1891: ... or PDL INT group are always combined to one output line that leads to an LTC input of LTC group g For example when looking at Figure 21 87 each of the eight LTC input multiplexer output lines to LTC group LTCG2 is connected via three LIMGn2 n 0 3 4 to the eight outputs of I O group IOG2 the clock group and the PDL INT group Figure 21 89 LTC Input Multiplexer Programmer s View The 1 level multiple...

Page 1892: ...tially Therefore the control registers values cannot be accessed directly but must be accessed in a specific sequential order Three registers are available for controlling the Multiplexer Register Array Multiplexer Register Array Control Register MRACTL Multiplexer Register Array Data Out Register MRADOUT Multiplexer Register Array Data In Register MRADIN Figure 21 90 shows the structure of the mu...

Page 1893: ...h a 0 4 Enable the multiplexer array by writing MRACTL MAEN 1 This establishes and enables all programmed interconnections To check the FIFO contents the FIFO can be written a second time At this check MRADIN is written before MRADOUT is read This will return the FIFO contents of the first write sequence in the order of OMCRH10 OMCRL10 LIMCRL0 Before disabling the multiplexer array FIFO LTCA outpu...

Page 1894: ...tiplexer Array Control Register FIFO Structure Multiplexer Register Array FIFO MCA05992_LTC32 VSD OMCRL13 23 24 31 OMCRH13 OMCRL0 9 10 OMCRH0 MRADOUT 0 Output Multiplexer Control Registers LIMCRL3 7 8 LIMCRH3 LIMCRL0 1 2 LIMCRH0 LTC Input Multiplexer Control Registers MRADIN MRACTL OMCRH3 OMCRL10 16 17 31 0 31 0 ...

Page 1895: ...g This flag is normally set by hardware but can be set and reset by software Each service request status flag can be read twice at the same bit location in SRSCx register and in SRSSx register and cleared or set by software when writing to the corresponding request bit in SRSCx or SRSSx When writing to SRSCx or SRSSx several flags can be cleared at once by one write operation Flags written with 0 ...

Page 1896: ...CA Service Request Groups Service Request Group Number Source 1 Source 2 Source 3 Source 4 00 LTC00 LTC01 LTC02 LTC03 01 LTC04 LTC05 LTC06 LTC07 02 LTC08 LTC09 LTC10 LTC11 03 LTC12 LTC13 LTC14 LTC15 04 LTC16 LTC17 LTC18 LTC19 05 LTC20 LTC21 LTC22 LTC23 06 LTC24 LTC25 LTC26 LTC27 07 LTC28 LTC29 LTC30 LTC31 ...

Page 1897: ...0008H U SV nBE 1 Page 21 166 SRSC2 Service Request State Clear Register 2 0020H U SV SV E 3 Page 21 224 SRSS2 Service Request State Set Register 2 0024H U SV SV E 3 Page 21 225 MRACTL Multiplexer Register Array Control Register 0038H U SV U SV 3 Page 21 259 MRADIN Multiplexer Register Array Data In Register 003CH U SV 32 U SV 32 3 Page 21 261 MRADOUT Multiplexer Register Array Data Out Register 00...

Page 1898: ...62 0204H k 8 U SV U SV 3 Page 21 258 LTCCTR63 Local Timer Cell Control Register 63 0200H 63 8 U SV U SV 3 Page 21 256 LTCXR63 Local Timer Cell X Register 63 0204H 63 8 U SV U SV 3 Page 21 258 OMCRLg Output Multiplexer Control Register for Lower Half of Group g g 0 3 10 13 not directly address able see Page 21 240 n a n a 3 Page 21 263 OMCRHg Output Multiplexer Control Register for Upper Half of Gr...

Page 1899: ...n MOD 1 0 rw Mode Control Bits 00B LTCk operates in Capture Mode 01B LTCk operates in Compare Mode 10B LTCk operates in Free Running Timer Mode 11B LTCk operates in reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has o...

Page 1900: ...UD and CUDCLR are both written with 1 bit CUD will be set CUDCLR is always read as 0 ILM 8 rw Input Line Mode 0B Input line is operating in Edge Sensitive Mode 1B Input line is operating in Level Sensitive Mode In case of full speed GPTA v5 module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event CUD 9 rwh Coherent ...

Page 1901: ...event otherwise hold 1XXB LTCkOUT output line state is affected by an internal LTCk event and or by an operation occurred in an adjacent LTCk cell reported by M1I M0I interface lines OIA 14 rw Output Immediate Action 0B No immediate action required 1B Action defined by bit field OCM must be performed immediately OIA is always read as 0 OUT 15 rh Output State 0B LTCkOUT output line is 0 1B LTCkOUT ...

Page 1902: ...ates in Free Running Timer Mode 11B LTCk operates in reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has occurred compare event has occurred timer overflow has happened depending on the operation mode selected by bit f...

Page 1903: ...ating in Level Sensitive Mode In case of full speed GPTA v5 module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event SLL 9 rh Capture Compare Mode Select Line Level 0B Current state of select input SI is 0 1B Current state of select input SI is 1 CEN 10 rh Cell Enable 0B LTCk is currently disabled for local events 1...

Page 1904: ...tion defined by bit field OCM must be performed immediately OIA is always read as 0 OUT 15 rh Output State 0B LTCkOUT output line is 0 1B LTCkOUT output line is 1 GBYP 16 rw Global Bypass 0B M3O M2O lines are affected by M1I M0I lines 1B M3O M2O lines are affected by M3I M2I lines 0 31 17 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1905: ...TCk operates in Free Running Timer Mode 11B LTCk operates in reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has occurred compare event has occurred timer overflow has happened depending on the operation mode selected ...

Page 1906: ... in Level Sensitive Mode In case of full speed GPTA v5 module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event SLL 9 rh Select Line Level 0B Current state of select input SI is 0 1B Current state of select input SI is 1 CEN 10 rh Cell Enable 0B LTCk is currently disabled for local events 1B LTCk is currently enable...

Page 1907: ...e performed immediately OIA is always read as 0 OUT 15 rh Output State 0B LTCkOUT output line is 0 1B LTCkOUT output line is 1 GBYP 16 rw Global Bypass 0B M3O M2O lines are affected by M1I M0I lines 1B M3O M2O lines are affected by M3I M2I lines 0 31 17 r Reserved Read as 0 should be written with 0 1 To enable Compare Mode in all cases SOL and SOH bits must be set to 1 Field Bits Type Description ...

Page 1908: ...y 0B Shadow register copy is continuously enabled 1B Shadow register copy is enabled for one event only REN 3 2 rw Request Enable 00B Service request SQT63 is disabled 01B Service request SQT63 is generated when a compare event has occurred 10B Service request SQT63 is generated when a shadow register copy event has occurred 11B Reserved RED 4 rw Rising Edge Select for Shadow Register Copy 0B Shad...

Page 1909: ...Sensitive Mode 1B LTC63IN is operating in Level Sensitive Mode CEN 10 rh Enable for Shadow Register Copy 0B Shadow register copy is currently disabled 1B Shadow register copy is currently enabled OUT 15 rh Output State 0B LTC63OUT output line is 0 1B LTC63OUT output line is 1 0 7 6 9 14 11 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1910: ...ck see Input Output Line Sharing Block IOLS on Page 21 98 LTCA2_LTCXRk k 00 62 Local Timer Cell X Register k 204H k 8H Reset Value 0000 0000H 31 16 15 0 0 X r rwh Field Bits Type Description X 15 0 rwh Local Timer Data Register Value 0 31 16 r Reserved Read as 0 should be written with 0 LTCA2_LTCXR63 Local Timer Cell X Register 63 3FCH Reset Value 0000 0000H 31 16 15 0 XS X rw rwh Field Bits Type ...

Page 1911: ...ming and the interconnections of the multiplexer array 0B Multiplexer array is disabled all cell inputs are driven with 0 LTCA I O lines pins are disconnected and FIFO writing is enabled 1B Multiplexer array is enabled all cell and I O line interconnections are established as previously programmed and FIFO writing is disabled WCRES 1 w Write Count Reset Writing WCRES with 1 while the array is disa...

Page 1912: ... v5 User s Manual 21 260 V1 1 2011 05 GPTA v5 V1 14 FIFOFILLCNT 13 8 r FIFO Fill Count This bit field shows the current contents of the write cycle counter 0 7 3 31 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1913: ...ored without any bus error LTCA2_MRADIN Multiplexer Register Array Data In Register 03CH Reset Value 0000 0000H 31 0 DATAIN w Field Bits Type Description DATAIN 31 0 w FIFO Write Data This register contains the FIFO write data as defined for the LTC Output Multiplexer Control Registers and the LTC Input Multiplexer Control Registers LTCA2_MRADOUT Multiplexer Register Array Data Out Register 040H R...

Page 1914: ...nly via the multiplexer register array FIFO see Page 21 121 21 6 5 1 Output Multiplexer Control Registers Two registers OMCRL and OMCRH are assigned to each I O Group IOG 3 0 and each Output Group OG 3 0 OMCRL 3 0 OMCRH 3 0 are assigned to IOG 3 0 and OMCRL 13 10 OMCRH 13 10 are assigned to OG 6 3 OMCRL controls the connections of group pins 0 to 3 OMCRH controls the connections of group pins 4 to...

Page 1915: ...by bit field OMGn for OMG output n 000B OMG input IN0 selected 001B OMG input IN1 selected 010B OMG input IN2 selected 011B OMG input IN3 selected 100B OMG input IN4 selected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG0 OMG1 OMG2 OMG3 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is connected to input n of...

Page 1916: ...t can be selected by bit field OMGn for OMG output n 000B OMG input IN0 selected 001B OMG input IN1 selected 010B OMG input IN2 selected 011B OMG input IN3 selected 100B OMG input IN4 selected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG4 OMG5 OMG6 OMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is conne...

Page 1917: ...2011 05 GPTA v5 V1 14 21 6 5 2 LTC Input Multiplexer Control Registers Two registers LIMCRL and LIMCRH are assigned to each LTC group LIMCRL controls the connections of LTC group cells with index 0 to 3 LIMCRH controls the connections of LTC group cells with index 4 to 7 ...

Page 1918: ...IMGn for LIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected LIMG0 LIMG1 LIMG2 LIMG3 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the LIMGng which is connected to input n o...

Page 1919: ...exer Line Selection This bit field selects the input line of a LIMG that can be selected by bit field LIMGn for LIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected LIMG4 LIMG5 LIMG6 LIMG7 6 4 14 12 22 20 30...

Page 1920: ...5 GPTA v5 V1 14 LIMEN4 LIMEN5 LIMEN6 LIMEN7 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1921: ...el external registers Port control and connections I O port line assignment I O function selection Pad driver characteristics selection Emergency control of GPTA v5 outputs On chip connections Clock bus connections MSC controller connections FADC connections MultiCAN SCU and DMA connections SCU connections ADC DMA Module clock generation Interrupt registers GPTA v5 address map Figure 21 93 shows t...

Page 1922: ...2 vsd fCLC P0 1 P0 15 P1 0 P 14 P2 0 P2 13 P4 0 P4 3 P5 0 P5 15 MSC0 FADC MultiCAN ADC0 ADC1 DMA IN 55 0 OUT 55 0 SR 37 00 54 IN 31 0 OUT 31 0 OUT 111 80 SR 07 00 GT0xRUN fLTCA2 OUT 111 56 INT 3 0 INT 3 0 INT 3 1 INT0 8 CLK 7 0 SR15 2 56 32 3 16 15 14 4 16 8 16 16 TRIG 15 0 SCU Ext Request Unit 9 9 16 4 P6 0 P6 3 4 32 56 GPTA0 32 32 Port Control IO Groups IOG 6 0 IOG 3 0 Output Groups OG 6 0 OG 3 ...

Page 1923: ...p and one 1 bit port group as shown in Figure 21 95 Within an 8 bit or 4 bit I O group the IN OUT line with lowest index number is assigned to the port line with the lowest index number The remaining lines are assigned linearly with increasing index numbers For example P0 13 is assigned to IN13 OUT13 In the TC1784 the four I O groups and four output groups of LTCA2 with 1 k 0 4 8 12 2 k 0 3 k 0 4 ...

Page 1924: ... IOCR registers Mca05997_TC1784 vsd 8 IOG0 OG 0 IOG 0 IOG 0 IOG 0 Port Control 7 0 63 56 7 0 IOG1 OG 1 IOG 1 IOG 1 IOG 1 15 8 65 64 15 8 15 8 IOG2 OG 2 IOG 2 IOG 2 IOG 2 23 16 79 72 23 16 23 16 IOG 4 OG 6 IOG 3 IOG 4 39 32 111 110 31 28 39 32 IN 31 0 to LTCA2 P0 7 0 P0 15 8 P1 7 0 P2 7 0 8 8 7 8 OUT 55 0 from GPTA0 OUT 111 56 from GPTA0 OUT 31 0 from LTCA2 OUT 111 80 from LTCA2 IN 55 0 to GPTA0 7 ...

Page 1925: ...Pad driver characteristics selection for outputs PDR registers 21 7 3 2 Input Output Function Selection Table 21 26 shows the GPTA0 LTCA2 I O lines mapping to the ports Note that GPTA0 LTCA2 input P0 0 IN0 see Page 21 284 and GPTA0 LTCA2 input P0 1 IN1 see Page 21 285 has special connections ...

Page 1926: ... P0_IOCR8 P0 15 12 IN 15 12 OUT 15 12 OUT 15 12 P0_IOCR12 Port 1 P1 3 0 IN 19 16 OUT 19 16 OUT 75 72 IN 19 3 OUT 19 16 P1_IOCR0 P1 7 4 IN 23 20 OUT 23 20 OUT 79 76 IN 23 20 OUT 23 20 P1_IOCR4 P1 11 8 IN 27 24 IN 51 48 OUT 27 24 OUT 51 48 P1_IOCR8 P1 14 12 IN 18 16 OUT 18 16 P1_IOCR12 Port 2 P2 3 0 IN 35 32 OUT 35 32 OUT 30 28 4 P2_IOCR0 P2 7 4 IN 39 36 OUT 39 36 OUT 31 OUT 111 110 5 P2_IOCR4 P2 11...

Page 1927: ... provided on the related GPTA0 LTCA2 unit output line All GPTA v5 pins at Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 and Port 6 Port 7 are connected to one common emergency stop signal that is generated in the System Control Unit of the TC1784 More details about the generation of this emergency stop signal are described in the System Control Unit chapter of the TC1784 System Units User s Manual Por...

Page 1928: ... affected by the emergency stop signal when bit Px_OUT Py is reset emergency disabled When the emergency stop signal is released Pin x y is switched back to the previously selected GPTA v5 output function without reprogramming the related port registers Table 21 27 Emergency Control for GPTA v5 Port Output Lines Port ESR Register ESR Enable Bits GPTA v5 Output Lines LTCA Output Lines Port 0 P0_ESR...

Page 1929: ...nits are capable to use the PLL clocks from each other Figure 21 96 Clock Bus Connections of GPTA0 LTCA2 21 7 4 2 MSC Controller Connections The MSC interfaces MSC0 provide a serial communication link typically used to connect power switches or other peripheral devices Each output multiplexers of GPTA0 generate 7 8 56 output lines OUT 111 56 grouped into seven output groups Each output multiplexer...

Page 1930: ...MSC0 Input Line Assigned GPTA0 LTCA2 Output Line MSC0 Input Line Assigned GPTA0 LTCA2 Output Line ALTINL 0 OUT80 OG3 0 ALTINH 0 OUT96 OG5 0 ALTINL 1 OUT81 OG3 1 ALTINH 1 OUT97 OG5 1 ALTINL 2 OUT82 OG3 2 ALTINH 2 OUT98 OG5 2 ALTINL 3 OUT83 OG3 3 ALTINH 3 OUT99 OG5 3 ALTINL 4 OUT84 OG3 4 ALTINH 4 OUT100 OG5 4 ALTINL 5 OUT85 OG3 5 ALTINH 5 OUT101 OG5 5 ALTINL 6 OUT86 OG3 6 ALTINH 6 OUT102 OG5 6 ALTIN...

Page 1931: ...MSC1 ALTINH 7 0 inputs For each of the ALTINL ALTINH inputs of the MSC the 2 bit bit fields in these registers determine which unit output is selected ALTINL 9 OUT89 OG4 1 ALTINH 9 OUT105 OG6 1 ALTINL 10 OUT90 OG4 2 ALTINH 10 OUT106 OG6 2 ALTINL 11 OUT91 OG4 3 ALTINH 11 OUT107 OG6 3 ALTINL 12 OUT92 OG4 4 ALTINH 12 OUT108 OG6 4 ALTINL 13 OUT93 OG4 5 ALTINH 13 OUT109 OG6 5 ALTINL 14 OUT94 OG4 6 ALTI...

Page 1932: ...utput OUT 80 n selected and connected to MSC0 ALTINL n 01B Reserved 10B LTCA2 output OUT 80 n selected and connected to MSC0 ALTINL n 11B Reserved GPTA0_MMXCTR01 GPTA to MSC Multiplexer Control Register 01 704H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUX 15 MUX 14 MUX 13 MUX 12 MUX 11 MUX 10 MUX 9 MUX 8 MUX 7 MUX 6 MUX 5 MUX 4 MU...

Page 1933: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUX 15 MUX 14 MUX 13 MUX 12 MUX 11 MUX 10 MUX 9 MUX 8 MUX 7 MUX 6 MUX 5 MUX 4 MUX 3 MUX 2 MUX 1 MUX 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MUXn n 0 15 2 n 1 2 n rw Multiplexer Control for MSC1 Inputs ALTINL n 00B GPTA0 output OUT 56 n selected and connected to MSC1 ALTINL n 01B 10B LTCA2 output OUT 80 n selected and connecte...

Page 1934: ... 10 9 8 7 6 5 4 3 2 1 0 0 MUX 7 MUX 6 MUX 5 MUX 4 MUX 3 MUX 2 MUX 1 MUX 0 r rw rw rw rw rw rw rw rw Field Bits Type Description MUXn n 0 7 2 n 1 2 n rw Multiplexer Control for MSC1 Inputs ALTINH n 00B GPTA0 output OUT 72 n selected and connected to MSC0 ALTINH n 01B 10B LTCA2 output OUT 96 n selected and connected to MSC1 ALTINH n 11B Reserved 0 31 15 r Reserved Read as 0 should be written with 0 ...

Page 1935: ...0 TRIG15 TRIG17 TRIG00 TRIG02 TRIG04 TRIG06 TRIG11 TRIG13 IN02 IN12 IN22 IN32 GSG GSH TSE TSF TSG TSH GSE GSF DMA TRIG0k k 7 0 CH0kREQI09 TRIG1k k 7 0 CH0kREQI10 TRIG0k k 7 0 CH1kREQI09 TRIG1k k 7 0 CH1kREQI10 TRIG10 REQGTk_0 k 4 0 TRIG12 REQGTk_1 k 4 0 TRIG14 REQGTk_2 k 4 0 TRIG05 TRIG16 TRIG00 REQTR1_0 REQTRk_2 k 3 1 REQTR0_0 ADC0 REQGTk_0 k 4 0 REQGTk_1 k 4 0 REQGTk_2 k 4 0 REQTRk_2 k 3 1 REQTR...

Page 1936: ...ggered by a request coming from a port pin or from the MSC clock ADC Connections As shown in Figure 21 98 for each ADC nine GPTA0 on chip trigger and gating output lines are connected as trigger input signals or gating input signals to the channel trigger logic of the ADC Thus dedicated GPTA0 outputs can generate trigger events or act as gating signals for ADC channels Furthermore the external req...

Page 1937: ...trol the clock frequency adjustment and the debug clock control The circuitry includes the following registers Clock Control Register GPTA0_CLC see Page 21 288 responsible for the generation of the control clock fCLCthat is used by each of the units Fractional Divider Register GPTA0_FDR see Page 21 289 responsible for the frequency control of the module timer clock fGPTA Clock Enable Disable Contr...

Page 1938: ...Clock Generation Unit for GPTA Modules Clock Enable Disable Control Register GPTA0_EDCTR fGPTA fGPTA0 fLTCA2 GPTA0 Kernel fSYS LTCA2 Kernel GT00RUN GT01RUN used for control tasks and register accesses Debug Clock Control Register GPTA0_DBGCTR MultiCAN Module SR15 ECEN INT0 INT0 MCA05603 fFPI Clock Control Register Module Clock Sleep Mode Request Suspend Request Fast Shut off Request fCLC Fractiona...

Page 1939: ...ivider mode of the fractional divider GPTA0_FDR DM 01B The lower formula applies to fractional divider mode GPTA0_FDR DM 10B The debug clock control register additionally makes it possible to control the timer clocks fGPTA0 fLTCA2 for debug purposes on basis of a clock counter If the debug clock feature is enabled GPTA0_DBGCTR DBGCEN 1 and bit GPTA0_DBGCTR DBGCST is set the timer clocks fGPTA0 fLT...

Page 1940: ...ontrol Register 000H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw GPTA v5 Module Disable Request Bit Used for enable disable control of the GPTA v5 module DISS 1 r GPTA v5 Module Disable Status Bit Bit indicates the current status of the ...

Page 1941: ...of fGPTA0 fLTCA2 is identical to the one of fGPTA GPTA0_FDR GPTA Fractional Divider Register 00CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mo...

Page 1942: ... rh Suspend Mode Request Indicates state of SPND signal ENHW 30 rw Enable Hardware Clock Control Controls operation of ECEN input and DISCLK bit DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1943: ...11 10 9 8 7 6 5 4 3 2 1 0 0 L2 EN 0 G0 EN 0 GT 01 RUN GT 00 RUN r rw r rw r rw rw Field Bits Type Description GT00RUN 0 rw GPTA0 Global Timer 0 Run Control 0B GPTA0 Global Timer 0 clock is stopped 1B GPTA0 Global Timer 0 clock is started running GT01RUN 1 rw GPTA0 Global Timer 1 Run Control 0B GPTA0 Global Timer 1 clock is stopped 1B GPTA0 Global Timer 1 clock is started running G0EN 8 rw GPTA0 Ti...

Page 1944: ...8 7 6 5 4 3 2 1 0 CLKCNT rwh Field Bits Type Description CLKCNT 15 0 rwh Debug Clock Count This bit field determines the number of clock pulses to be issued when the debug clock feature is enabled DBGCEN 1 CLKCNT counts down to 0000H and stops when the debug clock feature is enabled DBGCEN 31 rw Debug Clock Enable 0B The debug clock feature is disabled The GPTA v5 unit clocks are always enabled 1B...

Page 1945: ...v5 unit clock fGPTA is reduced the number of LTCs that can be cascaded increases accordingly Only the integer part of the divider ratio as selected by the GPTA0_FDR fractional divider register determines the maximum number of cascaded GTCs and LTCs Table 21 31 Limits of Cascading GTCs and LTCs fFPI Selected Clock Divider Ratio1 1 Selected by the GPTA0_FDR fractional divider register Max Number of ...

Page 1946: ...bed in the Interrupt chapter of the TC1784 User s Manual System Units part Volume 1 GPTA0_SRCk k 00 37 GPTA0 Interrupt Service Request Control Register k 7FCH k 4H Reset Value 0000 0000H LTCA2_SRCk k 00 07 LTCA2 Interrupt Service Request Control Register k 7FCH k 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE ...

Page 1947: ...CTR PLLMTI PLLCNT PLLSTP PLLREV PLLDTR CKBCTR 1 These registers are only available in GPTA0 700H 768H 400H General Module Control Input Output Line Sharing Unit Interrupt Control Global Timer Reserved Clock Generation Unit Local Timer Cells Interrupt Service Request Control Registers Global Timer Cells Reserved GPTA to MSC Multiplexer Control General Module Control MRADOUT MRADIN MRACTL GTCTRk GTR...

Page 1948: ... Register Map Reserved Reserved MCA06003_LTC32 020H k 00 31 038H 044H 200H 7FFH 7E0H MRADOUT MRADIN MRACTL LTCXRk LTCCTRk SRCk SRSS2 SRSC2 k 00 07 2FFH Local Timer Cells Interrupt Service Request Control Registers Input Output Line Sharing Unit Interrupt Control 000H General Module Control Reserved Reserved ID ...

Page 1949: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 297 V1 1 2011 05 GPTA v5 V1 14 ...

Page 1950: ...scription of the MLI see Page 22 2 Module kernel description see Page 22 27 Operation the MLI module see Page 22 70 MLI kernel register descriptions see Page 22 78 Device implementation specific descriptions and details see Page 22 130 Note The MLI kernel register names described in Section 22 3 are referenced in the TC1784 User s Manual by the module name prefix MLI0_ for the MLI0 interface and M...

Page 1951: ...ng conventions see Page 22 4 A description of the MLI communication principles see Page 22 6 22 1 1 1 MLI Overview The Micro Link Interface MLI is a fast synchronous serial interface to exchange data between microcontrollers or other devices such as stand alone peripheral components Figure 22 1 shows how two microcontrollers are typically connected together via their MLI interfaces Figure 22 1 Typ...

Page 1952: ...een a transmitter and a receiver Fully transparent read write access supported remote programming Complete address range of target device available Specific frame protocol to transfer commands addresses and data Error detection by parity bit 32 bit 16 bit or 8 bit data transfers supported Programmable baud rates MLI transmitter baud rate max fMLI 2 MLI receiver baud rate max fMLI Address range pro...

Page 1953: ...r are referring to the direction of the information flow These terms are independent from the terms Local and Remote For example the initialization of a bidirectional MLI connection between two controllers or between a controller and a stand alone device is always controlled and initiated by one controller named Local although during this phase both MLI participants can transmit and receive frames...

Page 1954: ...n a Transfer Window in the transmitting controller and the associated Remote Window in the receiving controller The MLI protocol supports four independent pipes Frame A frame is a contiguous set of bits forming a message sent by an MLI transmitter to an MLI receiver A Normal Frame is a frame used for data exchange between a transmitting and a receiving controller read request and write data from a...

Page 1955: ... to the Transfer Window together with the write offset to the MLI of the receiving controller The receiving controller stores the data internally and can also automatically place the data in the Remote Window of the receiving controller at the address location defined by the write offset plus the base address Read Access from a Transfer Window A read access from a location of a Transfer Window in ...

Page 1956: ... from a LTW or from a STW although each Transfer Window can be accessed at both address locations its LTW and its STW Figure 22 3 Transfer Remote Window Assignment Example During initialization of the pipes base addresses and sizes of the Remote Windows are transmitted from the Local Controller to the Remote Controller In the example of Figure 22 3 pipe 1 and pipe 2 cover the full range of their T...

Page 1957: ...Remote Window address ranges with fixed base address part and additional variable address part The variable address part is determined by the available address area for each Remote Window also named buffer size value of BSx buffer size for Remote Window x indicates how many address bits are variable defining the available address range Figure 22 4 Base Address Definition of Remote Windows MLI_Rwin...

Page 1958: ...s lower address bits of the target address the upper address bits are given by the Remote Window s base address Figure 22 5 Remote Window Address Generation without Address Prediction Figure 22 6 Remote Window Address Generation with Address Prediction MLI_Rwindow_offs Transfer Window Pipe x Base Address x 0 0 BSx 31 0 Remote Window Pipe x BSx 1 0 MLI Transmitter Base Address x Offset BSx 31 0 Off...

Page 1959: ... Optimized Read Frame to transmit the read request without read offset in case of an address prediction match see Page 22 16 Command Frame to transmit a command e g setup information or MLI service request generation see Page 22 17 Answer Frame to transmit the data previously requested by a Read Frame see Page 22 18 The local remote structure of an MLI connection between two microcontrollers requi...

Page 1960: ...ontent the value of PN is defined as 00B for pipe 0 01B for pipe 1 10B for pipe 2 and 11B for pipe 3 The FC parameter is coded according to Table 22 1 If more than one frame type is defined with the same frame code value see FC 01H 10H or 11H the width of the received frame defines the type The value given by m in the table below represents the number of address bits transferred as offset defined ...

Page 1961: ...ant bits of the 32 bit base address bits can be programmed by the transmitting controller the 4 LSBs are considered as 0 The base address of a Remote Window has to be aligned to its size e g a window of 1 Kbyte has to start at 1Kbyte address boundaries Remote Window size The size is defined by the 4 bit coded buffer size BS The maximum size is 64 Kbytes Parity bit P Figure 22 9 Copy Base Address F...

Page 1962: ...that has been the target of the write operation m Bits of write offset These bits define the write offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Write data field The write data field can be 8 bit 16 bit or 32 bit wide depending on the data width of the write access to the Transfer Window Parity bit P Figure 22 10 Write Offset and Data ...

Page 1963: ...rite Offset and Data Frames because they are shorter An optimized frame is only possible if the predicted address matches with the actually written one The Optimized Write Frame contains the following parts Header The header starts with frame code FC 11B followed by the pipe number PN of the Transfer Window that has been the target of the write operation Write data field The write data field can b...

Page 1964: ...of the read operation m Bits of write offset These bits define the read offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Data Width DW The data width DW indicates if the read from the Transfer Window was a 8 bit 16 bit or 32 bit read action It defines how many bytes have to be delivered to the Local Controller by the Answer Frame Parity b...

Page 1965: ...lowing parts Header The header starts with frame code FC 11B followed by the pipe number PN of the Transfer Window that has been the target of the read operation Data Width DW The data width DW indicates if the read from the Transfer Window was a 8 bit 16 bit or 32 bit read action It defines how many bytes have to be delivered to the Local Controller by the Answer Frame Same coding as for the Disc...

Page 1966: ...fic and depends on the transmitted pipe number x Parity bit P Figure 22 14 Command Frame More details about the Command Frame handling of the MLI module are provided on Page 22 41 Table 22 4 PN for Command Coding Pipe Number PN Command Type 00B Activate MLI service request or other control signal s of the receiving controller The definition which signal becomes activated is defined by CMD The usag...

Page 1967: ...to request data from the Remote Controller The Answer Frame contains the following parts Header The header starts with frame code FC 10B followed by the pipe number PN The value of PN is taken from the Read Frame that has triggered the Answer Frame Read data field The read data field can be 8 bit 16 bit or 32 bit wide depending on the data width requested by the Read Frame that triggered the Answe...

Page 1968: ... signal propagation delays between the transmitter and the receiver As shown in Figure 22 16 each output signal passes through the port stage reaches the physical interface line between the MLI modules enters via an input stage and can be finally evaluated All these steps introduce an accumulating propagation delay In standard synchronous serial connections such as SPI this delay limits the reacha...

Page 1969: ...VALID and READY have to be established as independent signal pairs for each device As a result a Local Controller only needs one CLK and one DATA output but an individual set of READY and VALID handshake signals for each Remote Controller Please note that Read Frames and Answer Frames are based on an established connection between a Local and a Remote Controller because the Answer Frame is the onl...

Page 1970: ...hereas sampling on the receiver side takes place with falling edges of RCLK Transmitter valid handshake VALID This signal indicates the start and the end of each frame It is active 1 level during a frame transmission and passive 0 level while no frame is transferred Changes of TVALID on transmitter side take place with rising edges of TCLK whereas sampling of RVALID on the receiver side takes plac...

Page 1971: ...r checks its TREADY input with each rising edge of TCLK after TVALID has become 0 and increments a counter This counter is started from 0 at the end of a frame transmission TVALID becomes 0 and counts TCLK periods Ready Delay Time Counter If the condition TREADY 1 is detected before the programmed Ready Delay Time has elapsed the MLI receiver has indicated a frame reception without parity error to...

Page 1972: ...READY After TVALID has been asserted to 1 the transmitter checks the receiver s acknowledge TREADY becoming 0 A Non Acknowledge error condition is detected by the transmitter when at the end of a frame transmission the TREADY signal is still at high level TREADY 1 when TVALID becomes 0 Figure 22 19 shows the Non Acknowledge error case In this case the transmitter automatically sends the last frame...

Page 1973: ... 3 5 Signal Timing Figure 22 20 shows the MLI timing requirements Figure 22 20 Signal Timing t27 t25 t26 t16 t17 t15 t15 MLI_Tmg_2 vsd TDATAx TVALIDx TCLKx RDATAx RVALIDx RCLKx TREADYx RREADYx t10 t13 t11 t12 t14 t20 t27 MLI Transmitter Timing MLI Receiver Timing t23 t21 t22 t24 ...

Page 1974: ...culation of the signal propagation time these 2 clock cycles have to be taken into account The transmitter input TREADYx has to be stable a certain time before TVALID becomes low referring to the rising edge of TCLK when TVALID becomes low If at this point in time TREADYx is detected at a high level a Non Acknowledge error is signaled The same timing relation has to be considered at the end of the...

Page 1975: ...ediction values can be handled in parallel for the different pipes The MLI transmitter can compare the offset of each Transfer Window read or write access with the offset of the previous access to the same Transfer Window Between the accesses to a specific window other windows can be accessed without disturbing the prediction Bigger offset differences than 512 bytes are not supported by the addres...

Page 1976: ...equest structure see Page 22 58 The MLI transmitter events see Page 22 60 The MLI receiver events see Page 22 63 The baud rate generation see Page 22 68 22 2 1 Frame Handling The frame handling is based on receiver and transmitter registers and the Transfer Windows Depending on the type of access to the Transfer Windows different actions take place inside the MLI module Please refer to the followi...

Page 1977: ...ed buffer size is loaded into bit field TPxSTATR BS Bit field TPxBAR ADDR 28 most significant base address bits is loaded into bit field TCBAR ADDR MCA06303_mod Transmitting MLI Controller Receiving MLI Controller MLI Transmitter Ready TPxBAR is written TPxSTATR BS TPxBAR BS TCBAR ADDR TPxBAR ADDR TRSTATR PN x TRSTATR BAV 1 Send Copy Base Address Frame of pipe x RPxBAR ADDR Base address 28 bit RPx...

Page 1978: ...ta frames This ensures a correct offset prediction afterwards Receiving Controller When a Copy Base Address Frame for pipe x has been received correctly and acknowledged the following actions are executed in the MLI receiver The received 28 most significant address bits are written into the receiver pipe x base address register bit field RPxBAR ADDR This bit field determines the base address of th...

Page 1979: ...1 Normal Frame Sent x event TREADY 1 Send Write Offset and Data Frame of pipe x Address Prediction Calculate TPxSTATR AP and TPxSTATR OP TPxSTATR OP 0 TCR NO 1 yes yes no no Send Optimized Write Frame of pipe x MLI Receiver Ready Pipe x initialized RADRR ADDR RPxBAR ADDR RPxBAR modified by Offset RADRR ADDR RPxBAR ADDR RPxBAR ADDR RPxSTATR AP RDATAR DATA Data RCR DW Detected data width RCR TF 10B ...

Page 1980: ... TCR NO 1 the transmission of a Write Offset and Data Frame is started as soon as the MLI transmitter is idle no higher priority frames are pending and TREADY 1 If the address prediction method is enabled TCR NO 0 a Write Offset and Data Frame is started only if an address prediction is not possible indicated by TPxSTATR OP 0 If TPxSTATR OP 1 an address prediction is possible in the MLI transmitte...

Page 1981: ...TAR DATA 31 0 3 1 1 4 TPxSTATR DW 00B TPxSTATR DW 01B TPxSTATR DW 10B Header Header Header m TPxSTATR BS 1 x Pipe number m bit Offset Address TPxAOFR AOFF 4 m bit Offset Address TPxAOFR AOFF 4 m bit Offset Address TPxAOFR AOFF 20 m 36 m MCA06298 PN P 8 bit Data 1 0 2 12 TDRAR DATA 7 0 3 1 0 PN P 16 bit Data 1 0 2 20 TDRAR DATA 15 0 3 1 0 PN P 32 bit Data 1 0 2 37 TDRAR DATA 31 0 3 1 0 4 4 TPxSTATR...

Page 1982: ...nt is set and an SR output line is activated if enabled by RIER NFRIE 01B or 10B After these actions related to the reception of a Write Frame by the receiving controller the data that has been received from the transmitting controller is ready to be written into the Remote Window related to the receiving pipe This write operation can be executed in two ways RCR MOD 0 Automatic Data Mode is disabl...

Page 1983: ...gine operation is finished frame execution and reception continue normally If Automatic Data Mode is disabled no blocking mechanism has been implemented The receiving controller software has to take care to deal with the received data before it is overwritten by new incoming frames 22 2 1 3 Read Frames Read Frames transmit read request and optionally the read offset from the Local Controller to th...

Page 1984: ...alized TRSTATR DVx 0 TISR NSFIx 1 TREADY 1 Send Discrete Read Frame of pipe x Send Answer Frame of pipe x TRSTATR AV 0 TREADY 1 RDATAR DATA Read Data RCR DW Width RCR TF 11B TRSTATR RPx 0 RISR NFRI 1 Address Prediction Calculate TPxSTATR AP and TPxSTATR OP TPxSTATR OP 0 TCR NO 1 yes yes no no Parity check acknowledge frame RADRR ADDR RPxBAR ADDR RPxBAR modified by Offset Parity check acknowledge f...

Page 1985: ...s started If the address prediction method is enabled TCR NO 0 a Discrete Read Frame is started only if an address prediction is not possible indicated by TPxSTATR OP 0 If TPxSTATR OP 1 an address prediction is possible and an Optimized Read Frame is started Status flag TRSTATR DVx is cleared by hardware and MLI event status flag TISR NFSIx Normal Frame Sent event in pipe x is set and a service re...

Page 1986: ...e actual address stored in RPxBAR ADDR The result of this addition is stored in RADRR ADDR and also in RPxBAR ADDR and represents the destination address in the Remote Controller from where data should be read The transmitted data width DW is written into bit field RCR DW The information about the received frame type 01B for a Read Frame is written into bit field RCR TF MLI event status flag RISR ...

Page 1987: ...ote window read operation and the data transfer to TDRAR After TDRAR DATA has been updated status flag TRSTATR AV of the Remote Controller is set and the transmission of an Answer Frame is started Figure 22 30 Read Frame Handling on Remote Side Note In Automatic Data Mode Read Frames are leading to a read action executed by the MLI move engine During the move engine operation only one more MLI fra...

Page 1988: ...x bit by writing 1 to SCR CDVx and can start a new Read Frame Remote Controller Receiving the read request The Answer Frame is the only frame sent from the Remote Controller back to the Local Controller The transmitter registers of the Remote Controller are used to generate the Answer Frame Every time the transmitter data read answer register TDRAR is written in the Remote Controller the transmiss...

Page 1989: ...e Controller by a Read Frame is now available in RDATAR and can be read by a bus master e g the CPU of the Local Controller If an Answer Frame is received while the corresponding TRSTATR RPx bit is 0 the reception is declared as unintended and a Discarded Read Answer event is generated see Page 22 63 Figure 22 31 Answer Frame Note If an Answer Frame has been correctly received in the Local Control...

Page 1990: ... MLI Controller Receiving MLI Controller MLI Transmitter Ready TCMDR CMDPx is written TRSTATR CV 1 Send Command Frame of pipe x x Code Pipe 0 activate one signal of SR 3 0 RISR IC 1 MLI Receiver Ready TRSTATR CV 0 TISR CFSIx 1 Command Frame Sent in Pipe x event Interrupt Command Frame event Pipe x RISR CFRIx 1 Command Frame Received event Pipe 1 write RCR DPE Pipe 2 set reset RCR MOD or reset TRST...

Page 1991: ...nsmitted by a Command Frame and that cause a specific control task in the MLI receiver The received PN value is checked and the corresponding control actions are executed according to Table 22 5 Independent of the received Pipe Number event status flag RISR CFRIx Command Frame Received event in pipe x is set and a service request output is activated if enabled by RIER CFRIEx 1 If a Command Frame i...

Page 1992: ...set RCR MOD 1 0010B Disable Automatic Data Mode in receiving MLI set RCR MOD 0 0100B Clear bit TRSTATR RP0 in receiving MLI 0101B Clear bit TRSTATR RP1 in receiving MLI 0110B Clear bit TRSTATR RP2 in receiving MLI 0111B Clear bit TRSTATR RP3 in receiving MLI 1111B Generate break output signal BRKOUT in receiving MLI if enabled by RCR BEN 1 others no effect reserved for future use 11B Any Free prog...

Page 1993: ...agation delay and to optimize the ready delay time see Page 22 74 Note There is no protection against frames where more than one bit is corrupted e g shortened frames In such a case an unpredictable behavior of the MLI module may occur Transmitting Controller The MLI transmitter counts the detected parity error conditions and generates a parity error event if a programmable number max 16 of parity...

Page 1994: ... the Transmitter Receiving Controller The receiver always checks the parity bit of a received frame for even parity A receiver parity error condition is detected if the received parity bit does not match with the internally calculated one If no receiver parity error condition is found after the reception of a frame RREADY is immediately set to 1 otherwise RREADY is kept at 0 until a defined number...

Page 1995: ... cleared by software by writing a 1 to bit SCR CRPE The receiver parity error flag RCR PE is cleared by hardware after a correct frame reception It can be cleared by software by writing a 1 to bit SCR CRPE The software can check for accumulated parity error conditions by reading RCR MPE or RISR PEI for the status of the latest received frame it can check RCR PE The delay for parity error bit field...

Page 1996: ...be enabled to support communication between MLI transmitter and MLI receiver without sending address offset information in the frames to optimize the required MLI bandwidth This feature reduces the required bandwidth for MLI communication Both communication partners MLI transmitter and the MLI receiver are able to detect regular offset differences of consecutive window accesses to the same window ...

Page 1997: ... Window and the number m of offset bits are given by RPxSTATR BS The bit positions RPxBAR 31 m are kept constant whereas the bit positions RPxBAR m 1 0 are replaced 22 2 2 4 Automatic Data Mode The MLI module supports automatic data transfers for read or Write Frames without any CPU load in the receiving controller This features is based on a move engine block providing the data the complete addre...

Page 1998: ... 32 fixed address ranges available that can be individually enabled disabled by the address range enable bits AER0 AENx and AER1 AENx x 0 31 If bit AERy AENx is set read write accesses to the associated address range x are supported in automatic mode If bit AENx is cleared read write accesses to the associated address range x are not automatically executed a memory protection error event is genera...

Page 1999: ... service request signals in the Local Controller and to transfer the requests to the Remote Controller without intervention of any CPU Bit CIVx is automatically cleared after successful transmission of the related Command Frame or by writing 1 to SCR CCIVx Note The connection of the TR 3 0 input lines is product specific Detailed information is given in the module implementation chapter see Page 2...

Page 2000: ...er to the device specific implementation chapter for details see Page 22 138Page 22 149 Answer Frame only one frame pending allowed at a time Triggered Command Transfer CIV0 before CIV1 before CIV2 before CIV3 Software driven Command Frames CV0 before CV1 before CV2 before CV3 Read or Write Frames DV0 before DV1 before DV2 before DV3 Base Address Copy Frame only one frame pending allowed at a time...

Page 2001: ...sions are programmed the waveform diagrams have to be interpreted accordingly In order to avoid naming mismatches the signals keep their names although a polarity inversion might have been programmed If desired polarity inversions for the same signal have to be programmed in the transmitter and in the receiver to guaranty signal consistency there has always to be an even number of inversions betwe...

Page 2002: ... condition in the on chip debug support logic or trigger other functions This signal is activated as a pulse by a Command Frame The service request outputs SR 7 0 of the MLI module can be activated as a pulse by transmitter or receiver events for all SRx as well as by Command Frames only for SR 3 0 The MLI module also supports 4 trigger inputs TR 3 0 A rising edge at input TRx sets bit TRSTATR CIV...

Page 2003: ... 2 3 2 Receiver I O Line Control Figure 22 37 shows the MLI receiver I O control logic 1 0 1 0 1 0 1 0 1 0 1 0 MCA06301_mod TVALID TDATA TCLK TVALIDB TVEB TVPB TDATA TRS TREADYA TREADYB TREADYC TREADYD TRP TRE TREADY MLI Transmitter MLI Transmitter I O Control Logic TVALIDA TVEA TVPA TVALIDD TVED TVPD TVALIDC TVEC TVPC TDP TCLK TCE TCP 2 01 10 11 00 1 0 OICR OICR OICR OICR OICR OICR OICR OICR OICR...

Page 2004: ...1 0 RRPB RVS RVALIDA RVALIDB RVALIDC RVALIDD RVP 1 0 01 10 11 00 RVE RVALID MLI Receiver MLI Receiver I O Control Logic RREADYA 1 0 RRPA RREADYD 1 0 RRPD RREADYC 1 0 RRPC RRS 01 10 11 00 RCS RCLKA RCLKB RCLKC RCLKD RCP 1 0 01 10 11 00 RCE RDS RDATAA RDATAB RDATAC RDATAD RDP 1 0 01 10 11 00 2 2 2 2 OICR OICR OICR OICR OICR OICR OICR OICR OICR OICR OICR OICR OICR ...

Page 2005: ...is accessed Only one receiver being available in the Local Controller the reception of data can be handled only either from one or the other Remote Controller The software has to ensure that only one Remote Controller sends data back to the Local Controller e g by using Read Frames or by enabling disabling the generation of Write Frames in the Remote Controllers Figure 22 38 Connecting Two Remote ...

Page 2006: ...r to the Local Controller without using Read Frames In a ring structure the Read Frame handling should be avoided It is possible for the Local Controller to access both Remote Controllers independently For example the Remote Window of pipe x covers the address range of Remote Controller X whereas pipe y targets the Transfer Window y of Remote Controller X In Remote Controller Y the pipe y targets ...

Page 2007: ...registers TIER for transmitter events or RIER for receiver events These two registers also contain the enable control bits that allow each event source to be enabled disabled individually for service request activation Each event can be connected to exactly one of the eight service request outputs SR 7 0 by a 3 bit interrupt node pointer One additional register the Global Interrupt Set Register GI...

Page 2008: ...connected to the demultiplexers of the MLI event specific lines Furthermore a service request output SRx can be triggered by software if the corresponding interrupt set bit in register GINTR is written with a 1 Figure 22 39 Service Request Compressor MCA06319_mod Node Pointer TINPR Service Request Output SR0 001 010 011 000 Transmitter Event with own Node Pointer To SR1 OR Gate To SR2 OR Gate SR0 ...

Page 2009: ...vents Table 22 7 MLI Transmitter Events Events Events combined to See Parity Error Parity Time out Error Page 22 61 Time out Error Normal Frame Sent in Pipe 0 Normal Frame Sent in Pipe 0 Page 22 61 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 3 Normal Frame Sent in Pipe 3 Command Frame Sent in Pipe 0 Comma...

Page 2010: ...ent Figure 22 40 Parity Time out Error Event Logic 22 2 5 2 Normal Frame Sent x Event A Normal Frame sent x x 0 3 event is generated when a Normal Frame has been sent and correctly received in pipe x Figure 22 41 Normal Frame Sent x Event Logic PEIE TIER PEIR MCA06311a_mod TEIE TIER TEIR 1 Software Clear Parity Error Event PEI TISR Set Time out Error Event TEI TISR Set Software Clear PTEIP 3 TINPR...

Page 2011: ...o each pipe All four pipe related Command Frame sent events are concatenated to one common Command Frame sent event Figure 22 42 Command Frame Sent Event Logic Command Frame Sent In Pipe 0 Event CFSI0 TISR Software Clear Set CFSI0 Control Logic Command Frame Sent in Pipe 1 Event CFSI1 Control Logic CFSI2 Control Logic CFSI3 Control Logic Command Frame Sent in Pipe 2 Event Command Frame Sent in Pip...

Page 2012: ...e 22 43 Discarded Read Answer Event Logic Table 22 8 MLI Receiver Interrupts Events Events combined to See Discarded Read Answer Discarded Read Answer Page 22 63 Memory Access Protection Error Memory Access Protection Parity Error Page 22 64 Parity Error Normal Frame Correctly Received Normal Frame Received Page 22 65 Move Engine Access Terminated Interrupt Command Frame Interrupt Command Frame Pa...

Page 2013: ...rammable maximum number of receiver parity errors is reached Both MLI events have separate status control bits but are concatenated to one common error event Figure 22 44 Memory Access Protection Parity Error Event Logic MCA06315a_mod MPEIE RIER MPEIR PEIE RIER PEIR Memory Access Protection Parity Error Event Software Clear MPEI RISR Set PEI RISR Set Memory Access Protection Error Event Parity Err...

Page 2014: ...Frame but not a Command Frame or if the move engine has terminated its read or write access Both event sources have separate status control bits but are concatenated to one common Normal Frame received event Figure 22 45 Normal Frame Received Event Logic NFRIE RIER NFRIR NFRI RISR Set MCA06316a_mod RIER MEIR MEI RISR Set 0 Normal Frame Received Event 2 Software Clear Software Clear Normal Frame Co...

Page 2015: ...received correctly on pipe 0 with a valid command code for service request output activation CMD 0000B to 0011B The received command code determines which of the service request outputs SR 3 0 should be activated Figure 22 46 Interrupt Command Frame Event Logic ICE RIER ICER Software Reset MCA06312a_mod Interrupt Command Frame Event IC RISR Set CMD PN 0 To SR0 To SR3 To SR1 To SR2 ...

Page 2016: ...related Command Frame received in pipe x events are concatenated to one common Command Frame received event Figure 22 47 Command Frame Received Event Logic Command Frame Received in Pipe 0 Event CFRI0 RISR Set CFRI0 Control Logic Command Frame Received in Pipe 1 Event CFRI1 Control Logic CFRI2 Control Logic CFRI3 Control Logic Command Frame Received in Pipe 2 Event Command Frame Received in Pipe 3...

Page 2017: ...on from 3FFH to 000H FDR RESULT represents the counter value and FDR STEP defines the reload value In order to achieve fMLI fSYS FDR STEP must be programmed with 3FFH The output frequency in normal divider mode is defined according the following equation 22 1 Fractional Divider Mode If the fractional divider mode is selected FDR DM 10B the clock fMLI is derived from the input clock fSYS by divisio...

Page 2018: ...lue of register OICR and bit RCR RCVRST is overwritten by hardware in the next two clock cycles after a reset first OICR followed by RCR The value applied during reset is given in the register description This automatic overwrite allows adapting the module to different application requirements without changing the module itself For example during reset the receiver is set to a defined state and ca...

Page 2019: ... Local Controller s transmitter to the Remote Controller s receiver and the Remote Controller s receiver have to be initialized 3 The Remote Controller s transmitter has to be initialized by data write actions from the Local Controller via the Remote Controller s receiver to the Remote Controller s transmitter registers 4 The pipes from the Remote Controller s transmitter back to the Local Control...

Page 2020: ...ting A can correspond to an inactive setting MLI not used for communication whereas the setting B is used for MLI communication In the case a memory access protection is implemented in the receiver and automatic handling of data is desired the user has to enable the corresponding address range in registers AER and ARR After a reset in most microcontrollers the access protection is generally disabl...

Page 2021: ... There are two possibilities to get the MLI communication started First easier possibility is to write TCR MDP to 14 and to set RCR DPE to 15 The second possibility could be used to optimize the bandwidth of the MLI connection It is described in Section 22 3 5 on Page 22 74 22 3 3 Remote Receiver Setup The initialization of the Remote Controller s receiver is done by frames sent by the Local trans...

Page 2022: ...Command Frame in pipe 2 with CM 0001B to set RCR MOD 1 in the Remote Controller 22 3 4 Remote Transmitter and Local Receiver Setup The initialization of the Remote Controller s transmitter and the Local Controller s receiver can be done by data frames sent by the local transmitter Therefore the Remote Controller s receiver has to be able to receive frames the port structure has to be set up accord...

Page 2023: ...the end of the frame is indicated in bit field TSTATR RDC The receiver participates in the control handshake by changing its RREADY output as a reaction to an incoming RVALID signal For the transmitter the TREADY input delivers the information that a receiver is connected and that it is ready for reception transfer only starts if TREADY 1 If a receiver is not able to handle the data or is not conn...

Page 2024: ...on of DPE there is no difference in time between a frame with or without a parity error having been detected The value given by TSTATR RDC indicates how many TCLK cycles are necessary for a control handshake This value should be incremented by a value DELTA value see below and written to TCR MDP The transmitter parity has to be programmed to even parity to be able to generate frames that are not d...

Page 2025: ...hanism needs a start trigger for the first data word transfer register GINTR can be written with the appropriate pattern to activate an SRx output 22 3 7 Connection of MLI to SPI The handshake signals between a transmitter and a receiver are based on a synchronous transfer protocol In the SPI protocol the shift clock and the data signal are equivalent to CLK and DATA In case of an 4 wire SPI the s...

Page 2026: ...y generation could be skipped for frames received by the SPI module and an error detection mechanism on an upper software layer could be implemented For frames sent by an SPI module the parity bit has to be calculated and sent correctly Otherwise the MLI receiver will discard the received frame ...

Page 2027: ...n Table 22 17 on Page 22 151 All registers in the MLI address spaces are reset with the application reset MLI Kernel Register Overview Figure 22 51 MLI Kernel Registers TPxBAR MCA06320a_mod TPxAOFR TCBAR RPxBAR RADRR FDR TSTATR TPxSTATR TCMDR TRSTATR TCR RPxSTATR SCR TIER TISR TINPR RIER RISR RINPR GINTR OICR AER ARR x 0 3 Number of pipes General Module Registers General Status Control Registers A...

Page 2028: ... 22 84 FDR Fractional Divider Register 0CH Page 22 81 TCR Transmitter Control Register 10H Page 22 95 TPxBAR MCA06320b_mod TPxAOFR TCBAR RPxBAR RADRR FDR TSTATR TPxSTATR TCMDR TRSTATR TCR RPxSTATR SCR TIER TISR TINPR RIER RISR RINPR GINTR OICR AERx ARRx x 0 3 Number of pipes General Module Registers General Status Control Registers Access Protection Registers Transmitter Control Status Registers T...

Page 2029: ...2 119 RADDR Receiver Address Register 8CH Page 22 121 RDATAR Receiver Data Register 90H Page 22 122 SCR Set Clear Register 94H Page 22 86 TIER Transmitter Interrupt Enable Register 98H Page 22 110 TISR Transmitter Interrupt Status Register 9CH Page 22 112 TINPR Transmitter Interrupt Node Pointer Register 0A0H Page 22 114 RIER Receiver Interrupt Enable Register A4H Page 22 123 RISR Receiver Interru...

Page 2030: ...Reset Value 03FF 43FFH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value In normal divider mode STEP contains the reload value for RESULT In fractional divider mode this bit field defines the 10 bit value that is added to the ...

Page 2031: ...it field DM DM 15 14 rw Divider Mode This bit fields defines the functionality of the fractional divider block 00B Fractional divider is switched off no output clock is generated RST_EXT_DIV is 1 RESULT is not updated default after reset 01B Normal divider mode selected 10B Fractional divider mode selected 11B Fractional divider is switched off no output clock is generated RESULT is not updated RE...

Page 2032: ...rdware while input signal ECEN is at high level DISCLK 31 rwh Disable Clock 0B Clock generation of fOUT fMLI is enabled according to the setting of bit field DM 1B Fractional divider is stopped Signal fOUT fMLI becomes inactive No change except when writing bit field DM In case of a conflict between hardware reset and software set of DISCLK the software set wins Any write or read modify write acti...

Page 2033: ...08H Reset Value 0025 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number This bit field defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module i...

Page 2034: ... activated under software control see Page 22 59 GINTR Global Interrupt Set Register B0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SI MLI7 SI MLI6 SI MLI5 SI MLI4 SI MLI3 SI MLI2 SI MLI1 SI MLI0 r w w w w w w w w Field Bits Type Description SIMLIx x 0 7 x w Set MLI Service Request Output Line x 0B No action 1B Service request...

Page 2035: ... C AV 0 C BAV C MOD w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C CV3 C CV2 C CV1 C CV0 C DV3 C DV2 C DV1 C DV0 0 S MOD S CV3 S CV2 S CV1 S CV0 w w w w w w w w w w w w w w Field Bits Type Description SCV0 SCV1 SCV2 SCV3 0 1 2 3 w Set Command Valid 0B No effect 1B Bit TRSTATR CVx is set SMOD 4 w Set MOD Flag 0B No effect 1B If CMOD 0 RCR is set If CMOD 1 RCR MOD is cleared CDV0 CDV1...

Page 2036: ...25 w Clear Receiver PE Flag 0B No effect 1B Bit RCR PE is cleared CTPE 26 w Clear Transmitter PE Flag 0B No effect 1B Bit TSTATR PE is cleared CNAE 27 w Clear NAE Flag 0B No effect 1B Bit TSTATR NAE is cleared CCIV0 CCIV1 CCIV2 CCIV3 28 29 30 31 w Clear Command Interrupt Valid x Flag 0B No effect 1B Bit TSTATR CIVx is cleared 0 7 5 23 18 w Reserved Read as 0 should be written with 0 Field Bits Typ...

Page 2037: ...RP C RRP B RRP A RRS rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RVE TDP TCP TCE TRE TRP TRS TVP D TVP C TVP B TVP A TVE D TVE C TVE B TVE A rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description TVEA TVEB TVEC TVED 0 1 2 3 rw Transmitter Valid Enable These bits enable the module kernel output signals TVALIDx x A B C D to be driven by MLI transmitter...

Page 2038: ...1 TREADY is active if 0 TRE 11 rw Transmitter Ready Enable This bit enables the MLI transmitter input signal TREADY 0B TREADY signal is disabled always at 0 level 1B TREADY signal is enabled and driven by TREADYx according to the settings of TRS and TRP TCE 12 rw Transmitter Clock Enable This bit enables the module kernel output signal TCLK 0B TCLK is disabled and remains at passive level as selec...

Page 2039: ...ADYx x A B C D that is driven by the MLI receiver output signal RREADY The RREADYx output signals that are not selected drives a passive level according to the setting of RRPx 00B RREADYA is selected 01B RREADYB is selected 10B RREADYC is selected 11B RREADYD is selected RRPA RRPB RRPC RRPD 18 19 20 21 rw Receiver Ready Polarity These bits determine the polarity of the module kernel receiver outpu...

Page 2040: ...for RCLKx selected RCLKx is at 0 level in passive state 1B Inverted polarity for TCLK selected RCLKx is at 1 level in passive state RCE 28 rw Receiver Clock Enable This bit enables the MLI receiver input clock RCLK 0B RCLK signal is disabled always at 0 level 1B RCLK signal is enabled and driven by RCLKx according to the settings of RCS and RCP RDS 30 29 rw Receiver Data Selector This bit field de...

Page 2041: ...26 25 24 23 22 21 20 19 18 17 16 AEN 31 AEN 30 AEN 29 AEN 28 AEN 27 AEN 26 AEN 25 AEN 24 AEN 23 AEN 22 AEN 21 AEN 20 AEN 19 AEN 18 AEN 17 AEN 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEN 15 AEN 14 AEN 13 AEN 12 AEN 11 AEN 10 AEN 9 AEN 8 AEN 7 AEN 6 AEN 5 AEN 4 AEN 3 AEN 2 AEN 1 AEN 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Des...

Page 2042: ... Bits Type Description SLICE0 4 0 rw Address Slice 0 SLICE0 selects a specific sub range within address sub range 0 SIZE0 7 5 rw Address Size 0 SIZE0 determines the sub range size within address sub range 0 SLICE1 12 8 rw Address Slice 1 SLICE1 selects a specific sub range within address sub range 1 SIZE1 15 13 rw Address Size 1 SIZE1 determines the sub range size within address sub range 1 SLICE2...

Page 2043: ...TC1784 Micro Link Interface MLI User s Manual 22 94 V1 1 2011 05 MLI V2 0 SIZE3 31 29 rw Address Size 3 SIZE3 determines the sub range size within address sub range 3 Field Bits Type Description ...

Page 2044: ...ter 10H Reset Value 0000 0110H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 TDEL r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TP NO MDP MNAE MPE 0 0 DNT MOD rw rw rw rwh rwh r rw rw rw Field Bits Type Description MOD 0 rw Mode of Operation This bit enables the MLI transmitter 0B The MLI transmitter is disabled 1B The MLI transmitter is enabled DNT 1 rw Data in Not Transmission This bit determin...

Page 2045: ...rror event is generated if 14 transmitter parity error conditions are detected 1111B A parity error event is generated if 15 transmitter parity error conditions are detected MNAE 9 8 rwh Maximum Non Acknowledge Errors This bit field determines the maximum number of consecutive Non Acknowledge error conditions that can be still detected in the transmitter until a time out event is generated MNAE is...

Page 2046: ...prediction enabled 1B Optimized method address prediction disabled TP 15 rw Type of Parity This bit will determines the type of parity used in frame transmissions For correct data transfers TP 0 has to be programmed The value TP 1 can be selected to force parity errors to analyze the propagation delay see Page 22 26 0B Even parity is selected 1B Odd parity selected TDEL 19 16 rw Transmission Delay...

Page 2047: ... is cleared to zero and starts counting up the TCLK clock periods until a TREADY high level is detected see Page 22 22 APN 6 5 rh Answer Pipe Number This bit field is written by the MLI receiver with the Pipe Number of a received Read Frame APN is used by an Answer Frame that is transmitted as response to the Read Frame 00B Pipe 0 is used in Answer Frame 01B Pipe 1 is used in Answer Frame 10B Pipe...

Page 2048: ...hen a Non Acknowledge error condition is detected by the MLI transmitter after a frame transmission see Page 22 47 NAE is cleared by hardware if a transmitted frame has been acknowledged correctly Bit NAE can be cleared by software via bit SCR CNAE 0 31 9 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2049: ...ler BS further determines how many address offset bits are transmitted in a Write Offset and Data Frame or in a Discrete Read Frame When register TPxBAR is written for generation of a Copy Base Address Frame BS is updated by the Copy Base Address Frame see Page 22 28 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window ...

Page 2050: ...Page 22 26 and Page 22 47 OP 16 rh Use Optimized Frame When address optimization is enabled with TCR NO 0 this bit indicates if address prediction is possible in the transmitter OP is written with each transmitter address prediction calculation see Page 22 26 and Page 22 47 0B No address prediction is possible A Write Offset and Data Frame or a Discrete Read Frame are used for transmission 1B Addr...

Page 2051: ...5 12 11 8 7 4 3 0 0 CMDP3 0 CMDP2 0 CMDP1 0 CMDP0 r rw r rw r rw r rw Field Bits Type Description CMDP0 3 0 rw Command Code for Pipe 0 This bit field contains the command code related to pipe 0 The pipe 0 command codes allow an activation pulse of one of the service request outputs SR 3 0 in the receiving controller 0001B Activate SR0 0010B Activate SR1 0011B Activate SR2 0100B Activate SR3 Other ...

Page 2052: ...Automatic Data Mode RCR MOD 0 0100B Clear bit TRSTATR RP0 0101B Clear bit TRSTATR RP1 0110B Clear bit TRSTATR RP2 0111B Clear bit TRSTATR RP3 1111B Activate a pulse at BRKOUT Other bit combinations are reserved for future use no further action in the receiver CMDP3 27 24 rw Command Code for Pipe 3 This bit field contains the command code related to pipe 3 The command codes for pipe 3 are free prog...

Page 2053: ...d Interrupt Valid Bit is set to 1 by the MLI transmitter whenever it detects a rising edge at the corresponding TRx input line for Triggered Command Frames in pipe 0 It is cleared by hardware when the Command Frame has been correctly transmitted CIVx can be cleared by software via bit SCR CCIVx CV0 CV1 CV2 CV3 4 5 6 7 rh Command Valid Bit is set by hardware when a TCMDR CMDPx bit field is written ...

Page 2054: ...e has been correctly sent DVx can be cleared by software via bit SCR CDVx RP0 RP1 RP2 RP3 20 21 22 23 rh Read Pending Bit is set by hardware when the TPxAOFR register of the MLI transmitter is updated after a read access to a Transfer Window of pipe x RPx is cleared by hardware when the MLI receiver in the Local Controller receives an Answer Frame for pipe x from the Remote Controller RPx can be c...

Page 2055: ...x TPxAOFR x 0 3 Transmitter Pipe x Address Offset Register 30H 4H x Reset Value 0000 0000H 31 16 15 0 0 AOFF r rh Field Bits Type Description AOFF 15 0 rh Address Offset Whenever a location within a Transfer Window is accessed read or written AOFF is loaded with the lowest 16 address bits of the access Also in the case of a small Transfer Window access all AOFF bits are loaded but AOFF 15 13 are n...

Page 2056: ...ter 40H 4H x Reset Value 0000 0000H 31 0 DATA rh Field Bits Type Description DATA 31 0 rh Data Whenever a location within a Transfer Window is written the data is loaded in this bit field TDRAR Transmitter Data Read Answer Register 50H Reset Value 0000 0000H 31 0 DATA rwh Field Bits Type Description DATA 31 0 rwh Data This bit field is loaded with data that is read from the address requested by a ...

Page 2057: ...bit field determines the coded buffer size of the pipe x Remote Window in the receiving controller When writing TPxBAR BS is copied into bit field TPxSTATR BS 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window B 1101B 14 bit offset address of Remote Window 1110B 15 bit offset address of Remote Window 1111B 16 bit offs...

Page 2058: ...f the latest write access to TPxBAR ADDR TCBAR Transmitter Copy Base Address Register 64H Reset Value 0000 0000H 31 4 3 0 ADDR 0 rh r Field Bits Type Description ADDR 31 4 rh Address This bit field contains the 28 address bits written to TPxBAR ADDR This value will be transferred to the receiving controller to define the base address of the Remote Window for pipe x 0 3 0 r Reserved Read as 0 shoul...

Page 2059: ...PE IE CFS IE3 CFS IE2 CFS IE1 CFS IE0 NFS IE3 NFS IE2 NFS IE1 NFS IE0 r rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NFSIE0 NFSIE1 NFSIE2 NFSIE3 0 1 2 3 rw Normal Frame Sent in Pipe x Interrupt Enable 0B Normal frame sent in pipe x event is disabled for activation of an SRx line 1B Normal frame sent in pipe x event is enabled for activation of an SRx line CFSIE0 CFSIE1 CFSIE2 CFSIE3 4...

Page 2060: ...NFSIR0 NFSIR1 NFSIR2 NFSIR3 16 17 18 19 w Normal Frame Sent in Pipe x Flag Clear 0B No action 1B Clear TISR NFSIx CFSIR0 CFSIR1 CFSIR2 CFSIR3 20 21 22 23 w Command Frame Sent in Pipe x Flag Clear 0B No action 1B Clear TISR CFSIx PEIR 24 w Parity Error Flag Clear 0B No action 1B Clear TISR PEIx TEIR 25 w Time Out Error Flag Clear 0B No action 1B Clear TISR TEIx 0 15 10 31 26 r Reserved Read as 0 sh...

Page 2061: ...0 r rh rh rh rh rh rh rh rh rh rh Field Bits Type Description NFSI0 NFSI1 NFSI2 NFSI3 0 1 2 3 rh Normal Frame Sent in Pipe x Flag The service request output that can be activated is defined by TINPR NFSIPx 0B A Normal Frame has not yet been sent 1B A Write or Read Frame has been correctly sent and acknowledged for pipe x CFSI0 CFSI1 CFSI2 CFSI3 4 5 6 7 rh Command Frame Sent in Pipe x Flag The serv...

Page 2062: ... 9 rh Time Out Error Flag The service request output that can be activated is defined by TINPR PTEIPx 0B A time out error event has not yet been detected 1B A time out error event has been detected 0 31 10 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2063: ... in pipe 0 event occurs if enabled 000B The service request output SR0 is selected 001B The service request output SR1 is selected B 110B The service request output SR6 is selected 111B The service request output SR7 is selected NFSIP1 6 4 rw Normal Frame Sent in Pipe 1 Interrupt Pointer This bit field determines which service request output SRx becomes active when a Normal Frame sent in pipe 1 ev...

Page 2064: ...utput SRx becomes active when a Command Frame sent event occurs if enabled Coding see NFSIP0 PTEIP 22 20 rw Parity or Time Out Interrupt Pointer This bit field determines which service request output SRx becomes active when a parity time out event occurs if enabled Coding see NFSIP0 0 3 7 11 15 19 31 23 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2065: ... CMDP3 DPE rh rh rh rh rh rh rh Field Bits Type Description DPE 3 0 rh Delay for Parity Error DPE determines the number of RCLK clock periods that the MLI receiver waits before the RREADY signal is raised again when it has detected a parity error see Page 22 22 When a pipe 1 Command Frame is received by the MLI receiver the command code is stored in this bit field see Page 22 41 0000B Zero RCLK cl...

Page 2066: ... It indicates the relevant data width 00B 8 bit relevant data width in RDATAR 01B 16 bit relevant data width in RDATAR 10B 32 bit relevant data width in RDATAR 11B Reserved TF 12 11 rh Type of Frame This bit field determines the frame type that has most recently been received by the MLI receiver It is updated whenever the MLI receiver updates RDATAR RADDR or RPxBAR The most recently received frame...

Page 2067: ...r error condition is detected 0001B A receiver parity event is generated if a receiver error condition is detected 0010B A receiver parity event is generated if 2 receiver error conditions are detected B 1110B A receiver parity event is generated if 14 receiver error conditions are detected 1111B A receiver parity event is generated if 15 receiver error conditions are detected BEN 20 rw Break Out ...

Page 2068: ...cription BS 3 0 rh Buffer Size This bit field indicates the size of pipe x Remote Window in the receiving controller It is updated by hardware when a Copy Base Address Frame has been received see Page 22 28 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window B 1110B 15 bit offset address of Remote Window 1111B 16 bit o...

Page 2069: ... Description ADDR 31 0 rh Address ADDR indicates the complete target address for the pipe x Remote Window If a pipe x Copy Base Address Frame is received ADDR 31 4 becomes loaded with the transmitted 28 bit address and bits 3 0 are cleared If a write or Read Frame with m bits of address offset is received bits ADDR 31 m are held constant and bits ADDR m 1 0 are replaced by the received offset If a...

Page 2070: ...s ADDR indicates the complete target address for the most recently or currently targeted Remote Window pipe x If a Copy Base Address Frame is received ADDR is unchanged If a write or Read Frame with m bits of address offset is received bits ADDR 31 m replaced by the bits RPxBAR ADDR 31 m and bits ADDR m 1 0 are replaced by the received offset If an optimized read or data frame is received the addr...

Page 2071: ...DATAR Receiver Data Register 90H Reset Value 0000 0000H 31 0 DATA rh Field Bits Type Description DATA 31 0 rh Data In the receiving controller DATA contains the data received by a Write Frame or an Answer Frame Bit field RCR DW determines the width of the relevant data that is stored in RDATAR RCR DW 00B RDATAR 7 0 are relevant 8 bit RCR DW 01B RDATAR 15 0 are relevant 16 bit RCR DW 10B RDATAR 31 ...

Page 2072: ...w rw rw rw rw rw Field Bits Type Description NFRIE 1 0 rw Normal Frame Received Interrupt Enable This bit field defines if an SRx output is activated if a Normal Frame is correctly received 00B The SRx activation is disabled 01B The selected SRx line is activated each time a Normal Frame is correctly received 10B The selected SRx line is activated each time a Normal Frame is correctly received tha...

Page 2073: ... This bit determines if an SRx output line is activated if a memory access protection error is detected 0B Memory access protection error event is disabled for activation of an SRx line 1B Memory access protection error event is enabled for activation of an SRx line DRAIE 9 rw Discarded Read Answer Interrupt Enable This bit determines if an SRx output line is activated if a discarded read Answer F...

Page 2074: ... ICE PEIR 23 w Parity Error Interrupt Flag Clear 0B No action 1B Clear RISR PEI MPEIR 24 w Memory Protection Error Interrupt Flag Clear 0B No action 1B Clear RISR MPEI DRAIR 25 w Discarded Read Answer Interrupt Flag Clear 0B No action 1B Clear RISR DRAI 0 15 10 31 26 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2075: ...ed Interrupt Flag This flag is set when a write or a Read Frame has been received The service request output that is activated is defined by RINPR NFRIP MEI 1 rh MLI Move Engine Interrupt Flag This flag is set when the move engine has finished an operation read or write depending on received frame The service request output that is activated is defined by RINPR MPPEIP CFRI0 CFRI1 CFRI2 CFRI3 2 3 4...

Page 2076: ...en a memory protection event has occurred The service request output that is activated is defined by RINPR MPPEIP DRAI 9 rh Discarded Read Answer Interrupt Flag This flag is set when the discarded read answer event has occurred This condition occurs if an Answer Frame is received while none of the TRSTATR RPx bits is set the Answer Frame was not expected The service request output that is activate...

Page 2077: ...l Frame received event occurs 000B The service request output SR0 is selected 001B The service request output SR1 is selected B 110B The service request output SR6 is selected 111B The service request output SR7 is selected CFRIP 6 4 rw Command Frame Received Interrupt Pointer This bit field determines which service request output SRx becomes active when a Command Frame received event occurs Codin...

Page 2078: ...TC1784 Micro Link Interface MLI User s Manual 22 129 V1 1 2011 05 MLI V2 0 0 3 7 11 31 15 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2079: ...p functional blocks The MLI0 module is supplied with clock control address decoding and interrupt control logic Four of the eight module service request outputs are connected to interrupt nodes Four service request outputs of the MLI0 module are connected as DMA request input to the DMA controller The four data clock and control lines of the MLI receiver and transmitter are connected to GPIO lines...

Page 2080: ...cted to low level SR 3 0 Interrupt Control To DMA SR 7 4 Port 2 Control P2 1 TREADY0A TREADYA TCLK TREADYD TVALIDA TVALIDD TDATA Transmitter Receiver RCLKA RCLKD RREADYA RREADYD RVALIDA RVALIDD RDATAA RDATAB TREADYB RREADYB RVALIDB RDATAD TVALIDB RCLKB MLI0 Module Kernel MCB06322_mod P2 0 TCLK0 P5 14 TREADY0B P2 2 TVALID0A P2 3 TDATA0 P2 4 RCLK0A P2 5 RREADY0A P2 6 RVALID0A P2 7 RDATA0A P5 11 RCLK...

Page 2081: ...ettings are shown in the following sections Figure 22 54 MLI0 Implementation Specific Special Function Registers 22 5 2 1 Automatic Register Overwrite The following values are applied after reset see Page 22 69 OICR 1000 8000H Setting A is selected RCR RCVRST 0 the receiver is enabled for reception MCA06321_mod DMA_MLI0SRCx Interrupt Registers P2_IOCR4 Port Registers P2_PDR x 0 3 P5_IOCR8 P5_IOCR1...

Page 2082: ... MultiCAN module can be used for external clock enable control of the fractional divider fDMA This is the module clock used inside the MLI kernels for control purposes such as for clocking of control logic and register operations The clock control register DMA_CLC makes it possible to enable disable fDMA under certain conditions DMA_CLC is described in the DMA chapter of this document fMLI0 This c...

Page 2083: ... applies to normal divider mode of the fractional divider FDR DM 01B Equation 22 5 applies to fractional divider mode FDR DM 10B After a reset operation the MLI module is enabled in normal divider mode According the MLI0_FDR register s reset value of 03FF 43FFH the selected baud rate is fDMA 2 Note that the DMA controller is also enabled after a reset operation with clock fDMA fSYS Baud rateMLIx f...

Page 2084: ...l registers When the MLI0 module is connected to the GPIO port lines the correct settings of the enable polarity control bits and bit fields in the output input control register MLI0_IOCR must also be regarded transmitter I O line control see Page 22 54 receiver I O line control see Page 22 55 Note that after a reset operation the MLI0 module although enabled have no direct connections to the GPIO...

Page 2085: ...LI0_OICR TRE 1 MLI0_OICR TRP X MLI0_OICR TRS 01B Input P5 13 TVALID0B P5_IOCR12 PC13 1X01B MLI0_OICR TVEB 1 MLI0_OICR TVPB X Output P5 12 TDATA0 P5_IOCR12 PC12 1X01B MLI0_OICR TDP X Output P5 11 RCLK0B P5_IOCR8 PC11 0XXXB MLI0_OICR RCE 1 MLI0_OICR RCP X MLI0_OICR RCS 01B Input P5 10 RREADY0B P5_IOCR8 PC10 1X01B MLI0_OICR RRS 01B MLI0_OICR RRPB X Output P5 9 RVALID0B P5_IOCR8 PC9 0XXXB MLI0_OICR RV...

Page 2086: ... service request control registers are named as DMA_MLI0SRCy and described in the DMA chapter implementation part of the TC1784 User s Manual All MLI service request output connections are listed in Table 22 12 Table 22 12 Service Request Lines and Interconnections of MLI0 Module Service Req Output Line Connected to Node or DMA Request Input Description MLI0 SR0 DMA_MLI0SRC0 MLI0 Service Request N...

Page 2087: ...e DMA Access Protection Address Ranges in the DMA chapter is also valid for MLI register bits AER AENRx x 0 31 The Tables Address Protection Sub Range Definition for PMI OVRAM DMI and PCP PRAM in the DMA chapter are also valid for MLI register bits ARR SLICEn and ARR SIZEn n 0 3 22 5 7 MLI0 Transfer Window Address Maps The MLI0 module supports four Small Transfer Windows STW one for each pipe and ...

Page 2088: ...est to with the DMA controller The data clock and control lines of each MLI receiver and transmitter are connected to GPIO lines Alternate functions of Port 1 and Port 5 lines are assigned to the MLI0 module I O lines while alternate functions of Port 8 lines are assigned to the MLI0 module I O lines Additionally within one MLI module transmitter and receiver signals can be dynamically connected a...

Page 2089: ...DATAC are connected to low level SR 3 0 fMLI0 Address Decoder Interrupt Control Clock Control To DMA SR 7 4 Port 1 Control P1 5 TREADY0A Port 5 Control TREADYA TCLK TREADYD TVALIDA TVALIDD TDATA Transmitter Receiver RCLKA RCLKD RREADYA RREADYD RVALIDA RVALIDD RDATAA RDATAB TREADYB RREADYB RVALIDB RDATAD TVALIDB RCLKB MLI0 Module Kernel MCA05906_mod P1 4 TCLK0 P1 3 TREADY0B P1 6 TVALID0A P1 7 TDATA...

Page 2090: ... lines TVALIDC and RREADYC are reserved for emulation purposes Unused transmitter receiver input lines TREADYC RCLKC RVALIDC and RDATAC are reserved for emulation purposes and should not be selected during normal operation of the TC1784 See also Page 22 145 for additional details on I O line control and function Interrupt Control MCA05907_mod Port 8 Control SR 1 0 fMLI1 Address Decoder Clock Contr...

Page 2091: ... following sections Figure 22 58 MLI0 MLI1 Implementation Specific Special Function Registers 22 5 9 1 Automatic Register Overwrite The following values are applied after reset see Page 22 69 OICR 1000 8000H Setting A is selected RCR RCVRST 0 the receiver is enabled for reception P1_IOCR0 MCA05908_mod DMA_MLI0SRCx Interrupt Registers P1_IOCR4 P1_IOCR8 Port Registers Clock Control Register DMA_MLI1...

Page 2092: ...ule can be used for external clock enable control of the fractional divider fDMA This is the module clock used inside the MLI kernels for control purposes such as for clocking of control logic and register operations The clock control register DMA_CLC makes it possible to enable disable fDMA under certain conditions DMA_CLC is described in the DMA chapter of this document fMLI0 and fMLI1 This cloc...

Page 2093: ...applies to normal divider mode of the fractional divider FDR DM 01B Equation 22 7 applies to fractional divider mode FDR DM 10B After a reset operation both MLI modules are enabled in normal divider mode According the MLIx_FDR register s reset value of 03FF 43FFH the selected baud rate is fDMA 2 Note that the DMA controller is also enabled after a reset operation with clock fDMA fSYS Baud rateMLIx...

Page 2094: ...registers When the MLI modules are connected to the GPIO port lines the correct settings of the enable polarity control bits and bit fields in the output input control registers MLI0_IOCR and MLI1_IOCR must also be regarded transmitter I O line control see Page 22 54 receiver I O line control see Page 22 55 Note that after a reset operation the MLI0 and MLI1 modules although enabled have no direct...

Page 2095: ...B MLI0_OICR RDP X MLI0_OICR RDS 00B Input P1 13 RCLK0B P1_IOCR12 PC13 0XXXB MLI0_OICR RCE 1 MLI0_OICR RCP X MLI0_OICR RCS 01B Input P1 14 RVALID0B P1_IOCR12 PC14 0XXXB MLI0_OICR RVE 1 MLI0_OICR RVP X MLI0_OICR RVS 01B Input P1 15 RDATA0B P1_IOCR12 PC15 0XXXB MLI0_OICR RDP X MLI0_OICR RDS 01B Input P5 4 RREADY0B P5_IOCR4 PC4 1X10B MLI0_OICR RRS 01B MLI0_OICR RRPB X Output P5 6 TVALID0B P5_IOCR4 PC6...

Page 2096: ...X Output P8 3 TDATA1 P8_IOCR0 PC3 1X11B MLI1_OICR TDP X Output P8 4 RCLK1A P8_IOCR4 PC4 0XXXB MLI1_OICR RCE 1 MLI1_OICR RCP X MLI1_OICR RCS 00B Input P8 5 RREADY1A P8_IOCR4 PC5 1X11B MLI1_OICR RRS 00B MLI1_OICR RRPA X Output P8 6 RVALID1A P8_IOCR4 PC6 0XXXB MLI1_OICR RVE 1 MLI1_OICR RVP X MLI1_OICR RVS 00B Input P8 7 RDATA1A P8_IOCR4 PC7 0XXXB MLI1_OICR RDP X MLI1_OICR RDS 00B Input Table 22 14 ML...

Page 2097: ... are located inside the DMA address area Therefore all MLI0 MLI1 service request control registers are named as DMA_MLIxSRCy and described in the DMA chapter implementation part of the TC1784 User s Manual All MLI service request output connections are listed in Table 22 15 Table 22 15 Service Request Lines and Interconnections of MLI0 MLI1 Module Service Req Output Line Connected to Node or DMA R...

Page 2098: ...A Access Protection Address Ranges in the DMA chapter is also valid for MLI register bits AER0 AENRx and AER1 AENRx x 0 31 The Tables Address Protection Sub Range Definition for PMI OVRAM DMI and PCP PRAM in the DMA chapter are also valid for MLI register bits ARR0 1 SLICEn and ARR0 1 SIZEn n 0 3 MLI1 SR0 DMA_MLI1SRC0 MLI1 Service Request Node 0 in DMA SR1 DMA_MLI1SRC1 MLI1 Service Request Node 1 ...

Page 2099: ... to F01E 1FFFH Pipe 1 F01E 2000H to F01E 3FFFH Pipe 2 F01E 4000H to F01E 5FFFH Pipe 3 F01E 6000H to F01E 7FFFH Large Transfer Window LTW Pipe 0 F020 0000H to F020 FFFFH Pipe 1 F021 0000H to F021 FFFFH Pipe 2 F022 0000H to F022 FFFFH Pipe 3 F023 0000H to F023 FFFFH MLI1 Small Transfer Window STW Pipe 0 F01E 8000H to F01E 9FFFH Pipe 1 F01E A000H to F01E BFFFH Pipe 2 F01E C000H to F01E DFFFH Pipe 3 F...

Page 2100: ...MLI0_ TSTATR MLI0 Transmitter Status Register F010 C014H U SV BE 0000 0000H MLI0_ TP0STATR MLI0 Transmitter Pipe 0 Status Register F010 C018H U SV BE 0000 0000H MLI0_ TP1STATR MLI0 Transmitter Pipe 1 Status Register F010 C01CH U SV BE 0000 0000H MLI0_ TP2STATR MLI0 Transmitter Pipe 2 Status Register F010 C020H U SV BE 0000 0000H MLI0_ TP3STATR MLI0 Transmitter Pipe 3 Status Register F010 C024H U S...

Page 2101: ...LI0_ TP1BAR MLI0 Transmitter Pipe 1 Base Address Register F010 C058H U SV U SV 0000 0000H MLI0_ TP2BAR MLI0 Transmitter Pipe 2 Base Address Register F010 C05CH U SV U SV 0000 0000H MLI0_ TP3BAR MLI0 Transmitter Pipe 3 Base Address Register F010 C060H U SV U SV 0000 0000H MLI0_ TCBAR MLI0 Transmitter Copy Base Address Register F010 C064H U SV BE 0000 0000H MLI0_ RCR MLI0 Receiver Control Register F...

Page 2102: ...ransmitter Interrupt Enable Register F010 C098H U SV U SV 0000 0000H MLI0_ TISR MLI0 Transmitter Interrupt Status Register F010 C09CH U SV BE 0000 0000H MLI0_ TINPR MLI0 Transmitter Interrupt Node Pointer Register F010 C0A0H U SV U SV 0000 0000H MLI0_ RIER MLI0 Receiver Interrupt Enable Register F010 C0A4H U SV U SV 0000 0000H MLI0_ RISR MLI0 Receiver Interrupt Status Register F010 C0A8H U SV BE 0...

Page 2103: ...n Register F010 C108H U SV BE 0025 C0XXH MLI1_ FDR MLI1 Fractional Divider Register F010 C10CH U SV SV E 03FF 43FFH MLI1_ TCR MLI1 Transmitter Control Register F010 C110H U SV U SV 0000 0110H MLI1_ TSTATR MLI1 Transmitter Status Register F010 C114H U SV BE 0000 0000H MLI1_ TP0STATR MLI1 Transmitter Pipe 0 Status Register F010 C118H U SV BE 0000 0000H MLI1_ TP1STATR MLI1 Transmitter Pipe 1 Status R...

Page 2104: ...00 0000H MLI1_ TP2DATAR MLI1 Transmitter Pipe 2 Data Register F010 C148H U SV BE 0000 0000H MLI1_ TP3DATAR MLI1 Transmitter Pipe 3 Data Register F010 C14CH U SV BE 0000 0000H MLI1_ TDRAR MLI1 Transmitter Data Read Answer Register F010 C150H U SV U SV 0000 0000H MLI1_ TP0BAR MLI1 Transmitter Pipe 0 Base Address Register F010 C154H U SV U SV 0000 0000H MLI1_ TP1BAR MLI1 Transmitter Pipe 1 Base Addre...

Page 2105: ...84H U SV BE 0000 0000H MLI1_ RP3STATR MLI1 Receiver Pipe 3 Status Register F010 C188H U SV BE 0000 0000H MLI1_ RADRR MLI1 Receiver Address Register F010 C18CH U SV BE 0000 0000H MLI1_ RDATAR MLI1 Receiver Data Register F010 C190H U SV BE 0000 0000H MLI1_ SCR MLI1 Set Clear Register F010 C194H U SV U SV 0000 0000H MLI1_ TIER MLI1 Transmitter Interrupt Enable Register F010 C198H U SV SV 0000 0000H M...

Page 2106: ...trol Register F010 C1B4H U SV U SV 1000 8000H MLI1_ AER0 MLI1 Access Enable Register 0 F010 C1B8H U SV SV E 0000 0000H MLI1_ ARR0 MLI1 Access Range Register 0 F010 C1BCH U SV SV E 0000 0000H MLI1_ AER1 MLI1 Access Enable Register 1 F010 C1C0H U SV SV E 0000 0000H MLI1_ ARR1 MLI1 Access Range Register 1 F010 C1C4H U SV SV E 0000 0000H Reserved F010 C1C0H F010 C1CCH BE BE Table 22 17 Address Map of ...

Page 2107: ...ycles This chapter is structured as follows Introduction see Section 23 1 Operating the ADC see Section 23 2 Module implementation in TC1784 see Section 23 3 23 1 Introduction This section gives an overview about the feature set of the ADC module and introduces the general structure It describes the ADC block diagram see Section 23 1 Feature set description see Section 23 1 2 Abbreviations see Sec...

Page 2108: ...ert an analog input signal into a digital value and provides means for triggering conversions data handling and storage With this structure parallel conversion of up to two analog input channels is supported Figure 23 1 ADC Module Block Diagram ADC kernel 1 ADC_2_kernels AD converter conversion control ADC kernel 0 analog inputs data result handling request control bus inter face AD converter conv...

Page 2109: ...r phase current measurements in AC drives Control capability for an external analog multiplexer respecting the additional set up time Adjustable sampling times to accommodate output impedance of different analog signal sources sensors etc Possibility to cancel running conversions on demand with automatic restart Flexible interrupt generation possibility of DMA support Limit checking to reduce inte...

Page 2110: ...gital converter DMA direct memory access mechanism DNL differential non linearity error FIFO first in first out data buffer mechanism INL integral non linearity error LSBn finest granularity of the analog value in digital format represented by one least significant bit of the conversion result with n bits resolution measurement range divided in 2n equally distributed steps SCU system control unit ...

Page 2111: ... signals EMUX 2 0 of each ADC kernel A request control unit defining which analog input channel has to be converted next It contains 5 request sources that can trigger conversions depending on different events such as edges of PWM or timer signals or events at port pins Each request source can trigger either 1 up to 4 or up to 16 conversions in a sequence A result handling unit providing 16 result...

Page 2112: ...2 ADC Kernel Block Diagram ADC_kernel _overv AD converter conversion control result handling request control interrupt generation ADC kernel analog input channel CH0 analog input channel CH15 standard analog reference VAREF analog reference ground VAGND external multi plexer control EMUX 2 0 ...

Page 2113: ... by other modules or under SW control As a consequence there can be two or more conversion requests pending at the same time To allow the user to adapt the request source mechanism to the application needs the trigger capability the channel number s to be converted and the priority can be individually programmed for each request source An arbiter block regularly scans the request sources for pendi...

Page 2114: ...conversion Request sources 1 and 3 16 channel scan sources can issue conversion requests for a sequence of up to 16 input channels It can be programmed which channel takes part in this sequence The sequence always starts with the highest enabled channel number and continues towards lower channel numbers order defined by the channel number each channel can be converted only once per sequence This m...

Page 2115: ... sequence of conversion results before the CPU has to interact A digital anti aliasing or data reduction filter accumulating a programmable number of conversion results before generating a result event interrupt This feature can be used to avoid CPU intervention on each conversion result if a certain number of conversion results are added before further treatment especially for fast conversions se...

Page 2116: ...uto scan sequence by triggering the read out by a result event if the conversion results of all channels taking part in the auto scan sequence target the same result register e g with FIFO mechanism or with a wait for read condition to avoid data loss Request source events A request source event is detected if a scan source has completely finished the requested conversion sequence For a sequential...

Page 2117: ...es and series resistors RAIN Only the switch to the selected analog input is closed during the sample phase During the conversion phase or while no conversion is running ADC is idle all switches are open The voltage at the analog input channel CHx is represented by VAINx Figure 23 4 Signal Path Model A simplified model for the analog input signal path is given in Figure 23 4 An analog voltage sour...

Page 2118: ...und VSSM or to the analog power supply VDDM It is recommended to use an operating range for the input voltage between approximately 3 and 97 of VDDM to reduce input leakage values Furthermore the leakage is influenced by an overload condition at adjacent analog inputs During an overload condition an input voltage exceeding the supply range is applied at an input and the built in protection circuit...

Page 2119: ...ing the conversion phase In order to limit the error introduced by this effect to 1 2 LSBn the external blocking capacitor CAREF for the reference input should be at least 2n CAIN The reference current IAREF introduces a voltage drop at RAREF that should not be neglected for the calculation of the overall accuracy The average reference current during a conversion depends on the reference voltage l...

Page 2120: ...ital transition between the values of 0 and 1 occurs A gain error is the deviation from the ideal transfer characteristics for an input voltage close to the reference voltage It describes the difference between the reference voltage and the input voltage where the last digital transition between the values of 2n 2 and 2n 1 occurs A differential non linearity error DNL describes the variations in t...

Page 2121: ...rnel registers see Section 23 2 6 Configuring the request source arbiter see Section 23 2 7 Arbiter registers see Section 23 2 8 Request source operation Scan request source handling see Section 23 2 9 Scan request source registers see Section 23 2 10 Sequential request source handling see Section 23 2 11 Sequential request source registers see Section 23 2 12 Channel and result register operation...

Page 2122: ...e in the ADC module are located in the address range of ADC0 All ADC registers including KSCFG NOMCFG and KSCFG COMCFG are reset by an application reset class 3 whereas bit field KSCFG SUMCFG is reset by a debug reset class 1 Note Register bits marked w always deliver 0 when read Access rights within the address range of an ADC kernel Read or write access to defined register addresses U SV Accesse...

Page 2123: ...ass 3 Page 23 48 RSPR4 Request Source Priority Register 4 044H U SV U SV Class 3 Page 23 49 Request Source 0 Registers available in the address range of each kernel QMR0 Queue 0 Mode Register 080H U SV U SV Class 3 Page 23 65 QSR0 Queue 0 Status Register 084H U SV U SV Class 3 Page 23 68 Q0R0 Queue 0 Register 0 088H U SV U SV Class 3 Page 23 70 QBUR0 Queue 0 Backup Register 08CH U SV U SV Class 3 ...

Page 2124: ... 72 QINR2 Queue 2 Input Register 0ACH U SV U SV Class 3 Page 23 74 Request Source 3 Registers available in the address range of each kernel CRCR3 Conversion Request 3 Control Register 0B0H U SV U SV Class 3 Page 23 54 CRPR3 Conversion Request 3 Pending Register 0B4H U SV U SV Class 3 Page 23 56 CRMR3 Conversion Request 3 Mode Register 0B8H U SV U SV Class 3 Page 23 57 Request Source 4 Registers av...

Page 2125: ... CHFR Channel Flag Register 060H U SV U SV Class 3 Page 23 86 CHFCR Channel Flag Clear Register 064H U SV U SV Class 3 Page 23 87 CHENPR0 Channel Event Node Pointer Register 0 068H U SV U SV Class 3 Page 23 88 CHENPR8 Channel Event Node Pointer Register 8 06CH U SV U SV Class 3 Page 23 89 Result Registers available in the address range of each kernel RESR0 Result Register 0 180H U SV U SV Class 3 ...

Page 2126: ...H U SV U SV Class 3 Page 23 110 Additional Feature Registers available in the address range of each kernel APR Access Protection Register 218H U SV SV E Class 3 Page 23 123 EMCTR External Multiplexer Control Register 220H U SV U SV Class 3 Page 23 124 SYNCTR Synchronization Control Register 048H U SV U SV Class 3 Page 23 128 BWDENR Broken Wire Detection Enable Register 224H U SV U SV Class 3 Page ...

Page 2127: ...pending in the device The kernel behavior is defined by KSCFG SUMCFG For the ADC module the following internal actions can be influenced by mode control A current conversion of an analog value If the request control unit has found a pending conversion request the conversion can be started This start has to be enabled by the mode control If the current kernel mode allows the conversion start run mo...

Page 2128: ... application needs and it is very unlikely that different stop modes are required in parallel in the same application As a result only one stop mode type either 0 or 1 should be used in the bit fields in register KSCFG Do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 or vice versa for the ADC module stop mode 0 A currently running AD conversion is comple...

Page 2129: ... switched off default after reset The complete converter is switched off and held in its reset state conversions are not possible To start a conversion ANON has to be programmed to the desired mode A maximum wake up time of about 10 µs has to be respected before starting a conversion Furthermore digital logic blocks are set to their initial state ANON 01B and 10B Reserved These modes are reserved ...

Page 2130: ...es the duration of an arbiter round It can be adjusted by programming bit field GLOBCTR DIVD All other digital structures such as interrupts etc are directly driven by the module clock fADC Figure 23 6 Clocking Scheme Note If the clock generation for the converter of the ADC falls below a minimum value or is stopped during a running conversion the conversion result can be corrupted For correct ADC...

Page 2131: ... 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the suspend mode EDIS 3 rw Sleep Mode Enable Cont...

Page 2132: ...FG Kernel State Configuration Register 00CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BP SUM 0 SUMCFG BP NOM 0 NOMCFG SUS REQ ACK 0 r w r rw w r rw rh rh r Field Bits Type Description ACK 2 rh Module Acknowledge This bit monitors the state of the ADC module s acknowledge on incoming requests 0B The acknowledge is not activate...

Page 2133: ...ite access to the bit field NOMCFG It always reads 0 0B The bit field NOMCFG is not changed 1B The bit field NOMCFG is updated with the written value SUMCFG 9 8 rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode Coding like NOMCFG BPSUM 11 w Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG It always reads 0 0B The bit fie...

Page 2134: ...System Units part Volume 1 ADC0_SRCx x 0 5 ADC Service Request Control Register x 3FCH x 4 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR ...

Page 2135: ...nnections depending on the device implementation please refer to the implementation description in Section 23 3 for details Note Signals from a synchronous domain can of course be connected to inputs with a synchronization stage The additional synchronization delay of two ADC module clock cycles and an additional uncertainty of one ADC module clock cycle for asynchronous signals have to be taken i...

Page 2136: ...EQGTx_2 is selected 011B The input signal REQGTx_3 is selected 100B The input signal REQGTx_4 is selected 101B The input signal REQGTx_5 is selected 110B The input signal REQGTx_6 is selected 111B The input signal REQGTx_7 is selected TMEN 4 rw Timer Mode Enable of Source x This bit enables the timer mode for equidistant sampling for request source x 0B The timer mode is disabled The standard gati...

Page 2137: ...l REQTRx_6 is selected 111B The input signal REQTRx_7 is selected FEN 12 rw Falling Edge Enable of Source x This bit enables the request trigger for falling edges of the selected REQTRx signal for request source x 0B The request trigger with a falling edge is disabled 1B The request trigger with a falling edge is enabled REN 13 rw Rising Edge Enable of Source x This bit enables the request trigger...

Page 2138: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision This bit field indicates the revision number of the module implementation depending on the design step The given value of 00H is a placeholder for the actual number Bits 3 0 refer to the version of the digital part and bits 7 4 indicate the version of the analog part anid MOD_TYPE 15 ...

Page 2139: ...er 204H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SI SR7 SI SR6 SI SR5 SI SR4 SI SR3 SI SR2 SI SR1 SI SR0 r w w w w w w w w Field Bits Type Description SISRx x 0 7 x w Set Interrupt for SRx Line Writing a 1 to a bit position sets an interrupt request at the SRx output of the ADC kernel the activation is finished automatically...

Page 2140: ... 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARB M 0 ARBRND ANON DIVD DIVA rw rw rw rw rw rw Field Bits Type Description DIVA 5 0 rw Divider Factor for Analog Internal Clock This bit field defines the number of fADC clock cycles to generate the fADCI clock for the converter used as internal base for the conversions and the sample time calculation The minimum divider is 4 00H fADCI fADC 4 01H f...

Page 2141: ...NON bit description see there if this kernel is the synchronization master or without synchronization feature For a synchronization slave this bit field is not taken into account ARBRND 11 10 rw Arbitration Round Length This bit field defines the number of arbitration slots per arbitration round arbitration round length tARB 00B An arbitration round contains 4 arbitration slots tARB 4 fADCD 01B An...

Page 2142: ...to be chosen in a synchronization slave see Section 23 2 19 and for equidistant sampling using the signal ARBCNT see Section 23 2 20 1B The arbiter only runs if at least one conversion request of an enabled request source is pending This setting leads to a reproducible latency from an incoming request to the conversion start if the converter is idle Synchronized conversions are not supported 0 31 ...

Page 2143: ...ndent of the current mode of the ADC ANON selected channel for conversion 0B The multiplexer test mode is disabled The analog input CH7 can be used for normal measurements 1B The multiplexer test mode is enabled The analog input CH7 is internally connected to ground via voltage divider based on an additional resistor 1 SUCAL 5 rw Start Up Calibration The transition from 0 to 1 of this bit starts t...

Page 2144: ... enabled for the selected selected input if MTMEN 1 MTMEN 15 rw Multiplexer Test Mode Enable This bit enables the multiplexer test mode for the channel number selected by MTMCH If an even channel number is selected this bit is internally considered as 0 0B The multiplexer test mode for the selected input channel is disabled This analog input can be used for normal measurements 1B The multiplexer t...

Page 2145: ...This bit indicates that a conversion is currently active 0B The analog part is idle 1B A conversion is currently active SAMPLE 1 rh Sample Phase This bit indicates that an analog input signal is currently sampled 0B The analog part is not in the sampling phase 1B The analog part is in the sampling phase CAL 2 rh Calibration Phase This bit indicates that the analog part is in the startup calibratio...

Page 2146: ... generation of fADCI and fADCD is stopped counters set to an initial value Furthermore the arbiter finishes its current arbitration round if running and then remains in the idle state 01B reserved do not use 10B reserved do not use 11B The analog part of the ADC module is switched on and conversions are possible SYNRUN 10 rh Synchronous Conversion Running This bit indicates that a synchronous para...

Page 2147: ...s running This bit field is updated with each conversion start 000B The channel requested by the request source of arbitration slot 0 is has been converted 001B The channel requested by the request source of arbitration slot 1 is has been converted 110B The channel requested by the request source of arbitration slot 6 is has been converted 111B The channel requested by a synchronous injection is h...

Page 2148: ... is started in an arbitration round this arbitration round does not deliver an arbitration winner In the TC1784 the following request sources are available Request source 0 in arbitration slot 0 1 stage sequential source This request source can issue a conversion request for a single input channel Request source 1 in arbitration slot 1 16 channel scan source This request source can issue a convers...

Page 2149: ...conversions of more than one ADC kernel are possible The trigger for the conversion triggers has to be generated synchronously to the arbiter timing Incoming triggers should have exactly n times the granularity of the arbiter n 1 2 3 In order to allow some flexibility the duration of an arbitration slot can be programmed in cycles of fADC If bit GLOBCTR ARBM 1 the arbiter stops after an arbitratio...

Page 2150: ...version has the lower priority and the arbiter winner has been programmed for wait for start mode the currently running conversion is completed Then the conversion of the arbitration winner is started This mode can be used if the timing requirement for the higher priority conversions allow a jitter between t3 and t4 in Figure 23 8 in the range of a running conversion If a conversion is currently r...

Page 2151: ... and a conversion request is activated In wait for read mode the currently running conversion of channel A is finished normally t4 After the conversion of channel A is finished the conversion of channel B is started With the start of the conversion the related conversion request is cleared t5 The conversion of channel B is finished t6 The trigger event for channel A occurs and a conversion request...

Page 2152: ...onversion the related conversion request is cleared t10 The conversion of channel B is finished In the meantime the pending request for channel A has been identified as arbitration winner and the conversion of channel A is started With the start of the conversion the related conversion request is cleared t11 The conversion of channel A is finished ...

Page 2153: ... Bits Type Description ASENx x 0 4 x rw Arbitration Slot x Enable Each bit enables an arbitration slot of the arbiter round ASEN0 enables the arbitration slot 0 ASEN1 the slot 1 etc If an arbitration slot is disabled it is considered as being empty The request bits of the request sources are not modified by write actions to ASENR 0B The corresponding arbitration slot is disabled and is not taken i...

Page 2154: ... CSM 0 0 PRIO 0 rw r rw rw r rw rw r rw rw r rw Field Bits Type Description PRIO0 PRIO1 PRIO2 PRIO3 1 0 5 4 9 8 13 12 rw Priority of Request Source x This bit field defines the priority of the conversion request source x located in arbitration slot x 00B Lowest priority is selected 11B Highest priority is selected CSM0 CSM1 CSM2 CSM3 3 7 11 15 rw Conversion Start Mode of Request Source x This bit ...

Page 2155: ...s bit field defines the priority of the conversion request source 4 located in arbitration slot 4 00B Lowest priority is selected 11B Highest priority is selected CSM4 3 rw Conversion Start Mode of Request Source 4 This bit defines the conversion start mode of the conversion request source 4 located in arbitration slot 4 0B The wait for start mode is selected 1B The cancel inject repeat mode is se...

Page 2156: ...nversion request pending The pending conversion requests indicate if an input channel has to be converted in an ongoing scan sequence see bits in registers CRPR1 CRPR3 A conversion request can only be issued to the request source arbiter if at least one pending bit is set With each conversion start that has been triggered by the scan request source the corresponding pending bit is automatically cl...

Page 2157: ...ted Also the edge selection for the trigger event is done in these registers The gating mechanism has to be defined by CRMRx ENGT The corresponding arbitration slot has to be enabled to accept conversion requests from the scan source see register ASENR The load event has to be defined by bits in CRMRx to start a scan sequence If a load event occurs while CRMRx LDM 0 the content of CRCRx is copied ...

Page 2158: ...anism does not modify the contents of the conversion pending bits but only prevents the arbiter from accepting requests from the request handling block The pending request bits can be cleared by writing bit CRMRx CLRPND 1 It is recommended to stop the scan sequence before clearing the pending bits 23 2 9 3 Request Source Event and Interrupt A request source event of a scan source occurs if the las...

Page 2159: ...upt Generation of a Scan Request Source ADC_scan_source_int EVFR FSx request source event request source event indication flag set CRMRx ENSI request source event interrupt enable EVNPRy SENPx request source event interrupt node pointer scan sequence finished EVFR GFSx gated event indication flag set ...

Page 2160: ...can be accessed at two different addresses One address for read and write access is given for CRCRx attribute rw leading to a data write to the bits in CRCRx without an automatic load event The second address only used for write actions is given for CRPRx additional attribute h leading to a data write to the bits in CRCRx with an automatic load event one clock cycle later CRCR1 Conversion Request ...

Page 2161: ...bit position x in this register The corresponding bit x in the conversion request pending register will be overwritten by this bit LDM 0 or bit wisely OR combined with this bit LDM 1 when the load event occurs 0B The analog channel CHx will not be requested for conversion by this request source 1B The analog channel CHx will be requested for conversion by this request source 0 31 16 r Reserved Rea...

Page 2162: ...set Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHP 15 CHP 14 CHP 13 CHP 12 CHP 11 CHP 10 CHP 9 CHP 8 CHP 7 CHP 6 CHP 5 CHP 4 CHP 3 CHP 2 CHP 1 CHP 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CHPx x 0 15 x rwh Channel Pending Bit x Write view A write to this address targets the bits in ...

Page 2163: ...r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 LD EV CLR PND REQ GT 0 LD M SC AN EN SI EN TR ENGT r w w rh r rw rw rw rw rw Field Bits Type Description ENGT 1 0 rw Enable Gate This bit field enables the gating functionality for the request source 00B The request source does not issue conversion requests 01B The request source issues conversion requests if at least one pending bit is set 10B The request...

Page 2164: ... enables a permanent scan functionality If enabled the load event is automatically generated if a request source event occurs 0B The permanent scan functionality is disabled 1B The permanent scan functionality is enabled LDM 5 rw Load Event Mode This bit defines the transfer mechanism triggered by the load event 0B With the load event the value of register CRCRx is copied to the pending register C...

Page 2165: ...TC1784 Analog to Digital Converter ADC User s Manual 23 59 V1 1 2011 05 ADC V1 3 0 6 31 10 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2166: ...n handle a single input channel 1 stage queue for 1 entry This mechanism could be used for SW controlled conversion requests or HW triggered conversions of a single input channel to inject a single conversion into a running sequence Figure 23 11 Sequential Request Source The internal structure and the handling of the sequential sources is similar for both versions The programmed sequence is stored...

Page 2167: ...tage defines which channel will be requested next for a conversion see Q0R0 Q0R2 Q0R4 It also defines if the request should be triggered by an external event or if the requested conversion should follow the previous one as soon as possible It also enables the request source interrupt generation after the conversion The contents of this queue stage is cleared when the requested conversion is starte...

Page 2168: ...ponding arbitration slot has to be enabled to accept conversion requests from the sequential source see register ASENR To start a sequence of a sequential request source the following mechanisms are supported An external trigger signal can be selected to start a scan sequence controlled by HW by an external module or signal e g a timer unit or an input pin The trigger feature is enabled by QMRx EN...

Page 2169: ...equested by this source is completely finished The interrupt enable bits are located in the queue 0 register if this has not been a repeated start after an abort or in the queue backup register if this has been a repeated start after an abort e g see Q0R0 for request source 0 or in the queue backup register if this has been a repeated start after an abort e g see QBUR0 for request source 0 A reque...

Page 2170: ...st Source ADC_seq_source_int to SR0 EVFR FSx to SR1 to SR7 request source event request source event indication flag set Q0Rx ENSI request source event interrupt enable EVNPRy SENPx request source event interrupt node pointer conversion finished triggered by request source QBURx ENSI QBURx V 1 0 EVCR GFSx gated event indication flag set ...

Page 2171: ...ation slot has to be disabled and SW has to wait for at least two arbitration rounds to be sure that this request source can no longer be an arbitration winner Then it has to check GLOBSTR CRSC and GLOBSTR BUSY to be sure that a conversion triggered by this request source is no longer running Then SW can read QBURx and Q0Rx and can start modification of the queue content QMR0 Queue 0 Mode Register...

Page 2172: ...ng signal REQGTx 1 11B The request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register and the selected gating signal REQGTx 0 ENTR 2 rw Enable External Trigger This bit enables the external trigger possibility 0B The external trigger is disabled and the trigger event is not generated 1B The external trigger is enabled and a ...

Page 2173: ... request source waits for a trigger event a conversion request is started FLUSH 10 w Flush Queue 0B No action 1B All entries in the queue including the backup stage and the event flag EV are cleared The queue contains no more valid entry CEV 11 w Clear Event Flag 0B No action 1B Bit EV is cleared 0 7 3 31 12 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2174: ...ster 0C4H Reset Value 0000 0020H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EV REQ GT 0 EMP TY 0 FILL r rh rh r rh r rh Field Bits Type Description FILL 3 0 rh Filling Level1 This bit field indicates how many queue entries are valid in the sequential source It is incremented each time a new entry is written to QINRx or by an enabled refill mechanism...

Page 2175: ...REQGTx input 0B The level is 0 1B The level is 1 EV 8 rh Event Detected This bit indicates that an event has been detected while at least one valid entry has been in the queue queue register 0 or backup stage Once set this bit is cleared automatically when the requested conversion is started 0B A trigger event has not been detected 1B A trigger event has been detected 0 4 6 31 9 r Reserved Read as...

Page 2176: ... r rh Field Bits Type Description REQCHNR 3 0 rh Request Channel Number This bit field indicates the channel number that will be or is currently requested RF 5 rh Refill This bit indicates if the pending request is discarded after the conversion start or if it is automatically refilled into the queue input of the request queue 0B The request is discarded after the conversion start 1B The request i...

Page 2177: ... event 0B The request handler does not wait for a trigger event 1B The request handler waits for a trigger event V 8 rh Request Channel Number Valid This bit indicates if the queue register 0 contains a valid queue entry 0B The queue entry is not valid and does not lead to a conversion request 1B The queue entry is valid and leads to a conversion request 0 4 31 9 r Reserved Read as 0 should be wri...

Page 2178: ...CH Reset Value 0000 0000H QBUR4 Queue 4 Backup Register 0CCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 V EX TR EN SI RF 0 REQCHNR r rh rh rh rh r rh Field Bits Type Description REQCHNR 3 0 rh Request Channel Number This bit field contains the channel number of an aborted conversion that has been requested by this request sour...

Page 2179: ...ntry in the queue backup register is valid REQCHNR RF TR and ENSI are valid Bit V is set if a running conversion that has been requested by this request source is aborted It is cleared when the repeated conversion is started 0B The backup register does not contain a valid entry 1B The backup register contains a valid entry It will be requested before a valid entry in queue register 0 will be reque...

Page 2180: ...Reset Value 0000 0000H QINR2 Queue 2 Input Register 0ACH Reset Value 0000 0000H QINR4 Queue 4 Input Register 0CCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EX TR EN SI RF 0 REQCHNR r w w w r w Field Bits Type Description REQCHNR 3 0 w Request Channel Number This bit field defines the requested channel number RF 5 w Refill Thi...

Page 2181: ...e related conversion is finished 1B A request source event interrupt is generated if the related conversion is finished EXTR 7 w External Trigger This bit defines the external trigger functionality 0B A valid queue entry immediately leads to a conversion request 1B A valid queue entry waits for a trigger event to occur before issuing a conversion request 0 4 31 8 r Reserved Read as 0 should be wri...

Page 2182: ...lias feature In addition to the general channel control the ADC kernel supports a mechanism named alias feature see Section 23 2 13 3 to redirect a conversion request to another channel number 23 2 13 1 Input Classes An input class defines the length of the sample phase and the resolution of the conversion In most applications the characteristics of the input circuitries RC input low pass filter a...

Page 2183: ... channel and to store the conversion results in two different result registers The same signal can be measured twice without the need to read out the conversion result to avoid data loss This allows triggering both conversions quickly one after the other and being independent from CPU interrupt latency The sensor signal is connected to only one input channel instead of two analog inputs This saves...

Page 2184: ... A and B For each channel the user can select these boundaries from a set of 4 programmable values LCBR0 to LCBR3 With this structure the conversion result range is split into three areas Area I The conversion result is below or equal to both boundaries Area II The conversion result is above one boundary and below or equal to the other boundary Area III The conversion result is above both boundari...

Page 2185: ... only if the conversion results are not in the normal operating range defined by area II LCC 010B Typical applications for limit checking are temperature monitoring or overcurrent sensing As long as the measured temperature value is below a boundary value the CPU does not need to be informed In this case a channel event should be generated only if the conversion result is in area III LCC 111B to i...

Page 2186: ...eas writing 0 has no effect The indication flags can be cleared by SW by writing a 1 to the corresponding bit position in register CHFCR Figure 23 16 Channel Event Interrupt Generation The service request output ADCy_SRx that is selected by the channel node pointer bit fields in registers CHENPR0 or CHENPR8 is activated each time the related channel event is detected A service request output can b...

Page 2187: ... SEL rw rw rw rw rw rw rw Field Bits Type Description BNDASEL 1 0 rw Boundary A Selection This bit field defines which boundary will be taken as boundary A for the limit checking 00B The value given by LCBR0 is selected 01B The value given by LCBR1 is selected 10B The value given by LCBR2 is selected 11B The value given by LCBR3 is selected BNDBSEL 3 2 rw Boundary B Selection This bit field define...

Page 2188: ... Input Selection This bit field defines the reference source for this channel 00B The standard reference input VAREF is selected 01B The alternative reference input CH0 is selected 10B reserved do not use 11B reserved do not use ICLSEL 11 10 rw Input Class Selection These bits are used to select the input class 00B The input class 0 is selected 01B The input class 1 is selected 10B The input class...

Page 2189: ...rw Field Bits Type Description STC 7 0 rw Sample Time Control This bit field defines the additional length of the sample phase given in analog clock cycles fADCI A minimum sample phase of 2 analog clock cycles is extended by the programmed value sample phase length 2 STC fADCI DW 9 8 rw Data Width This bit field defines how many bits are converted for the result The MSBs of conversion results with...

Page 2190: ...H Reset Value 0000 0100H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ALIAS1 0 0 ALIAS0 r rw rw r rw rw Field Bits Type Description ALIAS0 3 0 rw Alias Value for CH0 Conversion Requests The channel indicated in this bit field is converted instead of channel CH0 The conversion is done with the settings defined for channel CH0 ALIAS1 11 8 rw Alias Val...

Page 2191: ...it Check Boundary Register 1 0F4H Reset Value 0000 0E64H LCBR2 Limit Check Boundary Register 2 0F8H Reset Value 0000 0554H LCBR3 Limit Check Boundary Register 3 0FCH Reset Value 0000 0AA8H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BOUNDARY 0 r rw r Field Bits Type Description BOUNDARY 11 2 rw Boundary for Limit Checking This bit field contains the ...

Page 2192: ...F C13 F C12 F C11 F C10 F C9 F C8 F C7 F C6 F C5 F C4 F C3 F C2 F C1 F C0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description FCx x 0 15 x rwh Event Flag for Channel x Flag FCx indicates that a channel event for channel x has been detected Writing a 0 has no effect whereas writing a 1 sets the written bit position without generating an interrupt Bit FCx is c...

Page 2193: ...1 bit CHFR x is cleared software overrules hardware CHFCR Channel Flag Clear Register 064H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF C15 CF C14 CF C13 CF C12 CF C11 CF C10 CF C9 CF C8 CF C7 CF C6 CF C5 CF C4 CF C3 CF C2 CF C1 CF C0 w w w w w w w w w w w w w w w w Field Bits Type Description CFCx x 0 15 x w Clear Event Flag f...

Page 2194: ...0 19 18 17 16 0 CHENP7 0 CHENP6 0 CHENP5 0 CHENP4 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CHENP3 0 CHENP2 0 CHENP1 0 CHENP0 r rw r rw r rw r rw Field Bits Type Description CHENP0 CHENP1 CHENP2 CHENP3 CHENP4 CHENP5 CHENP6 CHENP7 2 0 6 4 10 8 14 12 18 16 22 20 26 24 30 28 rw Node Pointer for Channel x This bit field defines which service request output becomes activated if the ch...

Page 2195: ...1 0 CHENP10 0 CHENP9 0 CHENP8 r rw r rw r rw r rw Field Bits Type Description CHENP8 CHENP9 CHENP10 CHENP11 CHENP12 CHENP13 CHENP14 CHENP15 2 0 6 4 10 8 14 12 18 16 22 20 26 24 30 28 rw Node Pointer for Channel x This bit field defines which service request output becomes activated if the channel x event of kernel ADCy occurs while enabled by CHCTRx x 0 15 LCC 000B ADCy_SR0 is selected 001B ADCy_S...

Page 2196: ...sion results to minimize CPU load or to be more tolerant against interrupt latency An individual data valid flag VFR VFx for each result register indicates that new valid data has been stored in the corresponding result register and can be read out Due to different result handling mechanisms the conversion result can be represented in different ways Data reduction filter disabled The conversion re...

Page 2197: ...esult register it would change the status of the conversion result from valid new not yet read out to old already read out This would have an undesired impact on the application Therefore the read views with D deliver the same value as the read views without D but without clearing the valid bit As a result a debugger using read views with D can monitor the conversion results without influencing th...

Page 2198: ...rding to the CPU capability to read the formerly converted result If wait for read mode is enabled for a result register by setting bit WFR in register RCRx x 0 15 a request source does not generate a conversion request while the targeted result register contains valid data indicated by the valid flag VFx 1 or if a currently running conversion targets the same result register A new conversion requ...

Page 2199: ...dication flags can be cleared by SW by writing a 1 to the corresponding bit position in register EVFCR Figure 23 18 Result Event Interrupt Generation The service request output ADCy_SRx that is selected by the result event interrupt node pointer bit fields in registers RNPR0 or RNPR8 issues an interrupt each time the related result event is detected A service request output can be activated under ...

Page 2200: ...g bit FEN in registers RCRx x 0 15 In the example shown in Figure 23 19 the result registers have been configured to form two FIFO buffers with two buffer stages result registers 0 1 and 6 7 respectively one FIFO buffer with three buffer stages result registers 2 3 4 whereas result register 5 is used as normal result register without additional FIFO buffer functionality Figure 23 19 Result FIFO Bu...

Page 2201: ... stage This these result register s must not be enabled neither for wait for read mode nor for data reduction Result event interrupt generation is not supported Must not be read at a read view modifying the valid bit nor be the target of a conversion result Result register x FIFO buffer output This result register can be enabled for result event interrupt generation to inform the CPU that new data...

Page 2202: ...duction sequence of 4 accumulated conversion results is shown The data reduction is based on three rules Each time bit field DRC is 0 and a conversion targeting result register x is completed t1 t5 t9 the contents of bit field RCRx DRCTR is loaded into bit field DRC and the conversion result is stored in result register x Each time bit field DRC is not 0 and a conversion targeting result register ...

Page 2203: ...egister z to result register x by enabling the result FIFO mechanism for result register x see Figure 23 21 z x 1 In this case result register x is loaded with the final result elaborated by result register z when a data reduction sequence is finished The final result has to be read out from result register x before the next data reduction sequence is finished interval between t4 and t8 Figure 23 ...

Page 2204: ...ag VF indicates that a result register contains updated data and can be used to poll for new data The valid flag of a result register is cleared automatically if at least the low byte of register RESR0 is read whereas it is left unchanged when reading RESRD0 RESR0 Result Register 0 180H Reset Value 0000 0000H RESRD0 Result Register 0 for Debugging 1C0H Reset Value 0000 0000H 31 30 29 28 27 26 25 2...

Page 2205: ...t for data reduction The valid flag is automatically set when this bit field becomes 0 It can be cleared by SW by writing a 1 to the related bit position in register VFR 00B The final result is available in the result register The valid flag is automatically set when this bit field is set to 0 01B 1 more conversion result has to be added to obtain the final result in the result register 10B 2 more...

Page 2206: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VF DRC 0 CHNR 0 CRS 0 rh rh r rh r rh r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RESULT r rh Field Bits Type Description RESULT 13 0 rh Conversion Result This bit field contains the conversion result or respectively the result of the data reduction filter CRS 22 20 rh Converted Request Source This bit field indicates the request source that has request...

Page 2207: ...e in the result register 01B 1 more conversion result has to be added to obtain the final result in the result register 10B 2 more conversion results have to be added to obtain the final result in the result register 11B 3 more conversion results have to be added to obtain the final result in the result register VF 31 rh Valid Flag This bit indicates that bit field RESULT has been updated with val...

Page 2208: ... VF 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description VFx x 0 15 x rwh Valid Flag for Result Register x This bit indicates that the contents of the result register x is valid Writing a 0 has no effect whereas writing a 1 clears the written bit position and the bit field DRC in the related result register If a hardware event triggers the setting of a bit ...

Page 2209: ...ny conversion results are accumulated for data reduction see Section 23 2 15 5 It defines the reload value for bit field DRC 00B The data reduction filter is disabled The reload value for DRC is 0 so no accumulation is done 01B The data reduction filter is enabled The reload value for DRC is 1 so the accumulation is done over 2 conversions 10B The data reduction filter is enabled The reload value ...

Page 2210: ...egister x see Section 23 2 15 4 0B The FIFO functionality is disabled 1B The FIFO functionality is enabled WFR 6 rw Wait for Read Mode This bit enables the wait for read mode for result register x 0B The wait for read mode is disabled 1B The wait for read mode is enabled 0 3 2 31 7 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2211: ...Bits Type Description FRx x 0 15 x rwh Event Flag for Result Register x Flag FRx indicates that a result event of result register x has been detected Writing a 0 has no effect whereas writing a 1 sets the written bit position without generating an interrupt Bit FRx is cleared by writing EVFCR CFRx 1 0B An event of result register x has not yet been detected 1B An event of result register x has bee...

Page 2212: ...detected while the related interrupt was enabled Writing to this bit position has no effect Bit GFSx is cleared by writing EVFCR CFSx 1 0B An event of request source x has not yet been detected or the related interrupt was not enabled 1B An event of request source x has been detected while the related event interrupt was enabled 0 23 21 31 29 r Reserved Read as 0 should be written with 0 Field Bit...

Page 2213: ...egister 074H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 CF S4 CF S3 CF S2 CF S1 CF S0 r w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF R15 CF R14 CF R13 CF R12 CF R11 CF R10 CF R9 CF R8 CF R7 CF R6 CF R5 CF R4 CF R3 CF R2 CF R1 CF R0 w w w w w w w w w w w w w w w w Field Bits Type Description CFRx x 0 15 x w Clear Event Flag for Result Register x 0B No action 1B B...

Page 2214: ...0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SENP4 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SENP3 0 SENP2 0 SENP1 0 SENP0 r rw r rw r rw r rw Field Bits Type Description SENP0 SENP1 SENP2 SENP3 SENP4 2 0 6 4 10 8 14 12 18 16 rw Node Pointer for Request Source x This bit field defines which service request output becomes activated if the request source x event of kernel ADCy occurs whil...

Page 2215: ... RENP0 r rw r rw r rw r rw Field Bits Type Description RENP0 RENP1 RENP2 RENP3 RENP4 RENP5 RENP6 RENP7 2 0 6 4 10 8 14 12 18 16 22 20 26 24 30 28 rw Node Pointer for Result Register x This bit field defines which service request output becomes activated if the result register x event of kernel ADCy occurs while the interrupt generation is enabled for this event 000B ADCy_SR0 is selected 001B ADCy_...

Page 2216: ... RENP8 r rw r rw r rw r rw Field Bits Type Description RENP8 RENP9 RENP10 RENP11 RENP12 RENP13 RENP14 RENP15 2 0 6 4 10 8 14 12 18 16 22 20 26 24 30 28 rw Node Pointer for Result Register x This bit field defines which service request output becomes activated if the result register x event of kernel ADCy occurs while the interrupt generation is enabled for this event 000B ADCy_SR0 is selected 001B...

Page 2217: ...ltage divider Please refer to the AC DC chapter for the value of the resulting grounding resistor and its current capability Figure 23 22 Multiplexer Test Mode for CH7 In addition to the multiplexer test support for channel CH7 based on bit MTM7 one out of input channels listed below can also be enabled for the same function The additional channel number is selected by bit field GLOBCFG MTMCH and ...

Page 2218: ...xt conversion of the related analog ADC input channel In the example shown in Figure 23 23 and in the description below the analog input CH7 has been extended leading to additional analog inputs named CH70 to CH77 The channel number where the external multiplexer is connected to is defined by bit field EMUXCHNR Figure 23 23 External Analog Multiplexer If the external multiplexer is located far fro...

Page 2219: ...of EMSAMPLE The settling time is considered to be finished after the complete conversion of CH7 The external multiplexer control block supports different modes that are programmed by the bits in register EMCTR SW control without any HW interaction EMUXEN 0 The automatic control of the external multiplexer setting and of the sampling time is disabled Bit field EMUX is permanently updated with the v...

Page 2220: ... the external multiplexer control block triggers a new conversion request each time a conversion is started of the channel defined by EMUXCHNR while EMUX 0 In a scan request source the corresponding pending bit becomes set whereas in a sequential request source the content of the backup stage becomes valid V bit of backup stage becomes set With this setting all external multiplexer inputs are scan...

Page 2221: ...s do not lead to parallel conversions This leads to the following structure A synchronization master ADC kernel can request a conversion of an analog channel If this channel is selected for a synchronized conversion it is also requested in the connected slave ADC kernel s A synchronization slave ADC kernel reacts to incoming synchronized conversion requests from its master While no incoming master...

Page 2222: ...ct repeat mode in a synchronization slave see Section 23 2 7 2 Bit GLOBCTR ARBM has to be 0 for synchronization slaves The wait for read mode is supported for the master kernel whereas the setting is ignored in the slave kernels previous results may be overwritten The synchronization request issuing mechanism of the master to the slave kernels is based on bit field GLOBSTR ANON The information giv...

Page 2223: ...her channels Figure 23 25 Synchronization via ANON and Ready Signals The connections of the ADCx_ANON and ADCx_READY signals as well as the programming hints for register EMCTR are described in the implementation chapter see Section 23 3 ADC_ANON_sync ADC0 kernel kernel control GLOBCTR ANON ADC0_ANON SYNCTR STSEL 00 01 10 11 GLOBSTR ANON ADC1_ANON GLOBCTR ANON SYNCTR STSEL 00 01 10 11 C I1 C I1 C ...

Page 2224: ...control signal to really start the measurement preface time If the request source selected for equidistant sampling has been programmed with the highest priority no other request source can disturb the equidistant sampling The interpretation of the trigger signal REQTRx for equidistant sampling is enabled by selecting timer mode in the corresponding request source input register RSIRx TMEN 1 The f...

Page 2225: ...al 23 119 V1 1 2011 05 ADC V1 3 Figure 23 26 Timer Mode for Equidistant Sampling ADC_timer_mode equidistant sampling period ed REQTRx ed ed c c c c equidistant sampling period preface time preface time equidistant conversions lower priority conversions ...

Page 2226: ...d a write access occurs to one of them the write access is discarded the targeted register is not modified the written data is ignored and the error flag ACCERR is set The protected ADC registers are located in one of the following register groups registers not listed below can not be protected Register group 0 GLOBCTR Register group 1 GLOBCFG EMCTR RSIRx x 0 4 ALR0 Register group 2 ASENR RSPR0 RS...

Page 2227: ...r field CAIN is connected to the analog input CHx defined by BWDCFGR CHP before the sample phase starts The preparation phase length is identical to the sample phase length for this conversion If a channel is disabled for broken wire detection the preparation phase is omitted default setting Sample phase During this phase the capacitor field CAIN is connected to one of the analog inputs CHx via an...

Page 2228: ...t range Note The length of the complete analog to digital conversion is increased by the length of the preparation phase if the broken wire detection is enabled This influences the timing of conversion sequences The preparation phase is introduced as additional presample phase same behavior as the standard sampling phase but with the possibility to select a different channel number The analog part...

Page 2229: ...0 rwh r rw rw rw rw rw rw Field Bits Type Description RGx x 0 5 x rw Register Group x This bit enables disables write accesses to registers of register group x 0B Write actions to register group x are enabled and can modify the register contents 1B Write actions to register group x are disabled and do not modify the register contents ACCERR 15 rwh Access Error This flag indicates a violation of th...

Page 2230: ...SETEMUX 2 0 rw Setting of External Multiplexer If the external multiplexer control is disabled EMUX is loaded with the SETEMUX value If enabled the following two options are available Scan Mode disabled This bit field defines the input of the external multiplexer that will be selected for the next conversion of the channel selected by EMUXCHNR Bit field EMUX will be updated by SETEMUX at the begin...

Page 2231: ...1 at the end of the conversion of the channel selected by EMUXCHNR After reaching 0 it is reloaded with the value of bit field SETEMUX EMSAMPLE 15 8 rw External Multiplexer Sampling Time This bit field defines the alternative sample phase length in the case the external multiplexer setting has changed with the start of a conversion with enabled external multiplexer the value given by the selected ...

Page 2232: ...ANEN 22 rw Scan Enable This bit enables disables the automatic scan of the inputs of the external multiplexer for conversions of the channel selected by bit field EMUXCHNR taken into account only if EMUXEN 1 0B The scan mode is disabled Bit field EMUX is updated by bit field SETEMUX at the beginning of a conversion of the selected channel If bit EMUX is changed the value of EMSAMPLE is applied 1B ...

Page 2233: ...multiplexer 0B The external multiplexer control by HW is disabled Bit field EMUX is immediately updated under SW control by writing to SETEMUX The settings of SCANEN and TROEN are ignored 1B The external multiplexer control is enabled The update of EMUX is under HW control respecting the conversion timings 0 3 7 20 31 24 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2234: ...ronization group are started at the same time for parallel sampling although a kernel might be idle the master and all its connected slaves have to wait for all of them being ready SYNCTR Synchronization Control Register 048H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EVA LR3 EVA LR2 EVA LR1 0 STSEL r rw rw rw r rw Field Bits ...

Page 2235: ... be started if the synchronization master and all slaves of the conversion group indicate that they are ready to start a parallel conversion 0B The ready input R2 is not considered for the start of a parallel conversion of this conversion group 1B The ready input R2 is considered for the start of a parallel conversion of this conversion group EVALR3 6 rw Evaluate Ready Input R3 This bit defines if...

Page 2236: ...directed to another input by the alias feature BWDENR Broken Wire Detection Enable Register 224H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN 15 EN 14 EN 13 EN 12 EN 11 EN 10 EN 9 EN 8 EN 7 EN 6 EN 5 EN 4 EN 3 EN 2 EN 1 EN 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description ENx x 0 15 x rw Broken Wire ...

Page 2237: ...preparation phase BWDCFGR Broken Wire Detection Configuration Register 228H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CHP r rw Field Bits Type Description CHP 4 0 rw Channel Number for Preparation Phase This bit field defines which input channel is used for the preparation phase for the broken wire detection 0 15 5 r Reserved...

Page 2238: ...REQGTx_ 7 0 Each input vector contains 8 possible input signals but not all of them are necessarily connected Source 0 1 stage sequential source Source 1 Parallel source for up to 16 channels Source 2 4 stage sequential source Source 3 Parallel source for up to 16 channels Source 4 4 stage sequential source 23 3 2 Address Map The common KSCFG register of the ADC module can be accessed in the addre...

Page 2239: ...rnels All kernels support the feature set listed above and share a common ADC0_KSCFG register The kernels can be synchronized to each other for parallel sampling The channels CH4 CH5 CH6 and CH7 of ADC0 and the channels CH0 of all ADC kernels are always converted referring to the VAREF input of the corresponding ADC kernel For these channels the programmed alternative reference selection is not ta...

Page 2240: ...g Part from to Module or Pin Inputor Output Can be used to as VDDM VDDM I analog power supply 3 3V 5V VDDA VDDMF I analog power supply for comparator connected to FADC 3 3V supply VSSM VSSM I analog power ground VAREF VAREF I positive analog reference in 176 pin package combined with ADC1_VAREF VAGND VAGND I negative analog reference combined with other kernel CH0 AN0 I analog input channel 0 CH1 ...

Page 2241: ...ignals ARBCNT O Counting signal for arbiter rounds EMUXTR O Trigger output for scanning the external multiplexer inputs EMUX0 see port chapter O control of external analog multiplexer s EMUX1 see port chapter EMUX2 see port chapter Request Source 0 REQGT0_0 TRIG10 I GPTA REQGT0_1 TRIG12 I GPTA REQGT0_2 TRIG14 I GPTA REQGT0_3 PDOUT2 I ERU REQGT0_4 REQ0 I s P3 10 REQGT0_5 IRQ1 I s STM do not use for...

Page 2242: ...IG10 I GPTA REQGT1_1 TRIG12 I GPTA REQGT1_2 TRIG14 I GPTA REQGT1_3 PDOUT3 I ERU REQGT1_4 REQ0 I s P3 10 REQGT1_5 IRQ1 I s STM do not use for gating but for triggering REQGT1_6 0 I s not yet connected REQGT1_7 0 I s not yet connected REQTR1_0 TRIG03 I GPTA REQTR1_1 IOUT3 I ERU REQTR1_2 TRIG16 I GPTA REQTR1_3 ADC_SR6 I common service request output 6 of ADC module REQTR1_4 REQ1 I s P3 11 REQTR1_5 0 ...

Page 2243: ... I GPTA REQTR2_1 IOUT3 I ERU REQTR2_2 TRIG16 I GPTA REQTR2_3 ADC_SR6 I common service request output 6 of ADC module REQTR2_4 REQ5 I s P0 15 REQTR2_5 0 I s not yet connected REQTR2_6 ADC0_REQGT2 I s extend input selection for triggering by using gating inputs with ENGT 0X REQTR2_7 ADC0_SR7 I s service request output 7 of ADC0 REQTR2 O selected trigger signal for source 2 used as REQTRS for source ...

Page 2244: ...put selection for triggering by using gating inputs with ENGT 0X REQTR3_7 ADC0_SR7 I s service request output 7 of ADC0 REQTR3 O selected trigger signal for source 3 used as REQTRS for source 3 REQGT3 ADC0_REQTR3_6 O selected gating signal for source 3 Request Source 4 REQGT4_0 TRIG10 I GPTA REQGT4_1 TRIG12 I GPTA REQGT4_2 TRIG14 I GPTA REQGT4_3 PDOUT2 I ERU REQGT4_4 REQ0 I s P3 10 REQGT4_5 IRQ1 I...

Page 2245: ...ger signal for source 4 used as REQTRS for source 4 REQGT4 ADC0_REQTR4_6 O selected gating signal for source 4 1 In case of input signals the lines marked I don t contain synchronization stages whereas the lines marked I s contain synchronization stages so they can directly handle asynchronous input signals A signal connected to an input line marked I has to be delivered from a block located in th...

Page 2246: ...om to Module or Pin Inputor Output Can be used to as VDDM VDDM I analog power supply 3 3V 5V VDDA VDDMF I analog power supply for comparator taken from FADC 3 3V supply VSSM VSSM I analog power ground VAREF VAREF I positive analog reference in 176 pin package combined with ADC0_VAREF VAGND VAGND I negative analog reference combined with other kernel CH0 AN16 I analog input channel 16 CH1 AN17 I an...

Page 2247: ...ADC1 Signal of Digital Part from to Module or Pin Input 1 or Output Can be used to as Kernel Signals ARBCNT O Counting signal for arbiter rounds EMUXTR O Trigger output for scanning the external multiplexer inputs EMUX0 see port chapter O control of external analog multiplexer s EMUX1 see port chapter EMUX2 see port chapter Request Source 0 REQGT0_0 TRIG10 I GPTA REQGT0_1 TRIG12 I GPTA REQGT0_2 TR...

Page 2248: ...s REQTRS for source 0 REQGT0 ADC1_REQTR0_6 O selected gating signal for source 0 Request Source 1 REQGT1_0 TRIG10 I GPTA REQGT1_1 TRIG12 I GPTA REQGT1_2 TRIG14 I GPTA REQGT1_3 PDOUT3 I ERU REQGT1_4 REQ4 I s P0 14 REQGT1_5 IRQ1 I s STM do not use for gating but for triggering REQGT1_6 ADC0_SR7 I s ADC1 trigger by ADC0 REQGT1_7 0 I s not yet connected REQTR1_0 TRIG05 I GPTA REQTR1_1 IOUT3 I ERU REQT...

Page 2249: ...ating but for triggering REQGT2_6 ADC0_SR7 I s ADC1 trigger by ADC0 REQGT2_7 0 I s not yet connected REQTR2_0 TRIG06 I GPTA REQTR2_1 IOUT3 I ERU REQTR2_2 TRIG16 I GPTA REQTR2_3 ADC_SR6 I common service request output 6 of ADC module REQTR2_4 REQ1 I s P3 11 REQTR2_5 0 I s not yet connected REQTR2_6 ADC1_REQGT2 I s extend input selection for triggering by using gating inputs with ENGT 0X REQTR2_7 AD...

Page 2250: ... REQ1 I s P3 11 REQTR3_5 0 I s not yet connected REQTR3_6 ADC1_REQGT3 I s extend input selection for triggering by using gating inputs with ENGT 0X REQTR3_7 ADC1_SR7 I s service request output 7 of ADC1 REQTR3 O selected trigger signal for source 3 used as REQTRS for source 3 REQGT3 ADC1_REQTR3_6 O selected gating signal for source 3 Request Source 4 REQGT4_0 TRIG10 I GPTA REQGT4_1 TRIG12 I GPTA R...

Page 2251: ...e request output 7 of ADC1 REQTR4 O selected trigger signal for source 4 used as REQTRS for source 4 REQGT4 ADC1_REQTR4_6 O selected gating signal for source 4 1 In case of input signals the lines marked I don t contain synchronization stages whereas the lines marked I s contain synchronization stages so they can directly handle asynchronous input signals A signal connected to an input line marked...

Page 2252: ...ces of all kernels Note The ADC2 kernel is not implemented in the TC1784 but will be available in bigger devices such as TC1797 The following table indicates the service request connections for this case to allow a common approach for the interrupt generation Table 23 10 ADC Module Service Request Generation Module Service Request Output from ADC0 Kernel from ADC1 Kernel from ADC2 Kernel 1 1 Not a...

Page 2253: ...etely autonomously if it is configured as master ADC A slave ADC can be synchronized by the selected master ADC Note A master ADC can synchronize several slave ADCs whereas a slave ADC can only be synchronized by one master ADC Table 23 11 SYNCTR Setting for Kernel Synchronization Operating Mode SYNCTR EVALR3 SYNCTR EVALR2 SYNCTR EVALR1 SYNCTR STSEL ADC0 Kernel values to be programmed to ADC0_SYNC...

Page 2254: ... filter by data reduction is implemented to avoid expensive external filters Functional description of the FADC Kernel see Section 24 2 FADC kernel register descriptions see Section 24 3 TC1784 implementation specific details and registers of the FADC module including on chip interconnections service request control address decoding and clock control see Section 24 4 Note The FADC Kernel register ...

Page 2255: ... support for each channel Programmable gain of 1 2 4 or 8 for each channel Free running Channel Timers or triggered conversion modes Trigger and gating control for external signals Built in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable programmable digital anti aliasing and data reduction filter block with four independent...

Page 2256: ...t the input impedance differential or single ended measurement and to decouple the FADC input signal from the pins It is supplied by VDDIF VSSMF 3 3 V 5 V The VDDIF supply does not appear as supply pin in the pin list because it is internally connected to the VDDM supply of the ADC that is sharing the FADC input pins A channel amplifier with a settling time of about 5µs if its configuration is cha...

Page 2257: ...f the FADC have to be stable and noise free to ensure a high quality of the conversions MCA06432_m4n FAIN0N FAIN0P Analog Input Stages Rp Rn Channel Amplifier Stages gain A D A D Control conversion control Converter Stage CHNR VDDAF VSSAF FAIN2N FAIN2P Rp Rn FAIN1N FAIN1P Rp Rn VDDIF FAIN3N FAIN3P Rp Rn VSSMF VSSMF VDDMF VSSMF VDDMF VSSMF VDDMF VSSMF VDDMF ...

Page 2258: ...generation see Section 24 2 10 24 2 1 Analog Input Stage Configurations The analog input stage makes it possible to control the input impedance by selecting different configurations independently for each FADC channel x These combinations are shown in Figure 24 3 Figure 24 3 Analog Input Stage Configurations MCA06452 VFAREF 2 Rn Configuration 1 Single ended Measurement of VFAREF 2 FAINxN Rp Rp Rn ...

Page 2259: ...e is determined by Rn The positive input of the channel amplifier is connected to VFAREF 2 1 65 V with VFAREF 3 3 V If the voltage at the negative input FAINxN varies the FADC will deliver conversion results as follows gain 1 selected by ACRx GAIN 00B FAINxN 0 V FADC conversion result is 768 FAINxN 3 3 V FADC conversion result is 256 To cover the full range of the measurement result in this single...

Page 2260: ...epresentation The conversion result for FADC channel x is given by the following equations 24 1 The absolute value of the result VMx is limited to VFAREF The mapping of the conversion result VMx to the result RCHx ADRES is as follows For single ended measurements the following values are taken into account if ENPx 0 then VFAINxP VFAREFM if ENNx 0 then VFAINxN VFAREFM Note In Multiplexer Test Mode ...

Page 2261: ...mmed to enable trigger signals signal ECHTIMx set the conversion request flag CRFx becomes set indicating a valid request for FADC channel x The gating source input and gating mode selection logic generate an enable signal for channel x timer that determines whether any of the three conversion trigger signal sources is allowed to set the channel x conversion request flag CRFx It can select an inpu...

Page 2262: ...e trigger signal 10B When gating source input GSn 1 as selected by CFGRx GSEL the Channel Timer is enabled and the conversion request bit CRSR CRFx becomes set by hardware with each active trigger signal 11B When gating source input GSn 0 as selected by CFGRx GSEL the Channel Timer is enabled and the conversion request bit CRSR CRFx becomes set by hardware with each active trigger signal MCA06433_...

Page 2263: ...can be also set or cleared by software via bits in the Flag Modification Register FMR Writing a 1 to FMR SCRF sets CRFx Writing a 1 to FMR RCRF clears CRFx independently of FMR SCRF Table 24 2 Trigger Modes CFGRx TM Trigger Mode 00B No trigger signal generated 01B A conversion request trigger signal is generated on a rising edge of trigger source input TSn selected by CFGRx TSEL 10B A conversion r...

Page 2264: ...ed determines the frequency of channel x timer input clock fCTx While the Channel Timer is disabled CFGRx CTM 00B or if the gating condition is not met gating line ECHTIMx delivers 0 the channel x timer value is set to 04H This value ensures a fast conversion trigger after the gating becomes enabled but prevents unintended conversion starts in case of short pulses bouncing at the gating input Figu...

Page 2265: ... request flag CRSR CRFx x 0 3 is set the channels are converted according to a priority scheme as defined by the bit field GCR CRPRIO without respecting the status of the current filter sequences 24 2 6 2 Dynamic Priority Assignment If dynamic priority assignment is enabled GCR DPAEN 1 a channel that has the only active gate signal signal ECHTIMx in Figure 24 4 among the four channels gets the hig...

Page 2266: ... for the Channel Timers and other internal timings 24 2 6 4 Suspend Mode Behavior When a suspend idle mode request is generated for the FADC module via the fractional divider a currently running conversion is completely finished not aborted and if selected a filter calculation still takes place Thereafter no new conversion will be started and the state of the FADC module is frozen until the suspen...

Page 2267: ...on emulation chip the channel reassignment allows compatible SW usage with different channel wiring to pins The setting of the input stages incl calibration information is defined by register ACRx of the input channel that is requested no alias mapping I e the ACRx register of the actually converted channel is used as it is permanently conntected to its channel The result handling incl interrupts ...

Page 2268: ...ter blocks Each filter block allows selection of its input data source The input data sources are the conversion result registers of the four A D converter channels Filter blocks can also be concatenated block 0 and block 1 can be concatenated same for block 2 and block 3 When the result of a filter operation is stored in one of the final result registers a service request can be generated Each fi...

Page 2269: ...mediate result registers All result registers of the filter block can be read at any time Please note that only one intermediate result register is available in filter block 1 IRR11 and in filter block 3 IRR13 Figure 24 8 Filter Block Structure 24 2 7 2 Filter Block Operation A filter block can be used for data reduction or anti aliasing filtering of the conversion results n indicates the number o...

Page 2270: ...are added to build the final result in FRRn The number of intermediate results taking part in the moving average operation to build the final result is programmable the maximum is given by Filter block 0 FRR0 CRR0 IRR10 IRR20 IRR30 Filter block 1 FRR1 CRR1 IRR11 Filter block 2 FRR2 CRR2 IRR12 IRR22 IRR32 Filter block 3 FRR3 CRR3 IRR13 At the end of the final result cycle the contents of IRR2n are ...

Page 2271: ... intermediate results Filter blocks 1 and 3 operate with the following parameters Intermediate results are based on the final results of filter block 0 for filter block 1 and of filter block 2 for filter block 3 Filter block concatenation is enabled by FCRn INSEL 010B An intermediate cycle can contain a maximum of 8 conversion results A final result cycle can contain a maximum of 2 intermediate re...

Page 2272: ...ster Long Name Register Short Name Result Width Filter 0 Current Result Register CRR0 13 bit Filter 0 Intermediate Result Register 1 IRR10 Filter 0 Intermediate Result Register 2 IRR20 Filter 0 Intermediate Result Register 3 IRR30 Filter 0 Final Result Register FRR0 15 bit Filter 1 Current Result Register CRR1 18 bit Filter 1 Intermediate Result Register 1 IRR11 Filter 1 Final Result Register FRR1...

Page 2273: ...ng condition gating mode selection output at high level in Figure 24 4 in the corresponding neighbor channel is valid All neighbor channel trigger enable bits ENxy are located in the Neighbor Channel Trigger Register NCTR Index x indicates the number of the channel that starts a neighbor channel trigger Index y is the number of the neighbor channel to be triggered Figure 24 9 Neighbor Channel Trig...

Page 2274: ... in normal conversion mode without restrictions Figure 24 10 Analog Input and Channel Amplifier Configuration at Calibration Figure 24 10 shows the channel amplifier configuration as well as the analog input pin configurations that are selected during offset and gain calibration Note that in the calibration modes the impedance of the analog inputs depends on the settings of the ENN and ENP bits of...

Page 2275: ...set calibration value bitfield ACRx CALOFF where x is the calibrated channel and repeat the conversion s Increase CALOFF for results below 512 decrease CALOFF for results above 512 Note Bitfield CALOFF is a signed number composed of bitfields CALOFF3 and CALOFF 2 0 with a zero bit inbetween The calibration process is finished when the conversion result crosses the ideal value of 512 Use the offset...

Page 2276: ...l logic as shown in Figure 24 12 provides the following functionality Service Request Flag Set Clear Request Flag Control Bits Service Request Enable Bit Service Request Node Pointer Figure 24 12 Service Request Control Logic MCA06441_m Channel Conversion Requests Service Request Compressor Filter Block 0 calculation finished Channel 2 conversion finished SR0 SR1 SR2 SR3 Filter Block Requests Chan...

Page 2277: ...c shown in Figure 24 13 the inputs of one SRx OR gate are connected to all demultiplexer outputs with identical INP node pointer value Therefore one service request event can be only assigned to one of the four service request outputs but one service request output can be used by multiple service request events Figure 24 13 Service Request Compressor Logic Table 24 5 Service Request Control Status...

Page 2278: ...C Module in a specific micro controller the service request output signals SR 3 0 can either be connected to an interrupt node controlled by a service request control register or can be used as DMA request input of a DMA controller unit The TC1784 specific request output connections are described in the FADC implementation chapter ...

Page 2279: ...el Read access to defined register addresses U SV Write access to defined register addresses U SV Accesses to empty addresses reserved BE Table 24 6 Register Overview of FADC Short Name Description Offset Addr 1 Access Mode Reset Description See Read Write FADC Module Registers CLC Clock Control Register 000H U SV SV E Class 3 Page 24 30 FDR Fractional Divider Register 00CH U SV SV E Class 3 Page ...

Page 2280: ...trol Register 01CH U SV U SV Class 3 Page 24 42 reserved no BE has to be written with 0 050H ALR Alias Register 054H U SV SV E Class 3 Page 24 46 Channel Registers CFGRx Channel x Configuration Register x 0 3 020H x 4 U SV U SV Class 3 Page 24 48 ACRx Channel x Analog Control Reg x 0 3 030H x 4 U SV U SV Class 3 Page 24 52 RCHx Channel x Conversion Result Register x 0 3 040H x 4 U SV U SV Class 3 ...

Page 2281: ... 24 58 IRR11 Filter 1 Intermediate Result Register 1 088H U SV U SV Class 3 Page 24 60 FRR1 Filter 1 Final Result Register 094H U SV U SV Class 3 Page 24 62 SFRR1 Filter 1 Shifted Final Result Register 098H U SV U SV Class 3 Page 24 63 Filter 2 Registers FCR2 Filter 2 Control Register 0A0H U SV U SV Class 3 Page 24 55 CRR2 Filter 2 Current Result Register 0A4H U SV U SV Class 3 Page 24 58 IRR12 Fi...

Page 2282: ... SV U SV Class 3 Page 24 58 IRR13 Filter 3 Intermediate Result Register 1 0C8H U SV U SV Class 3 Page 24 60 FRR3 Filter 3 Final Result Register 0D4H U SV U SV Class 3 Page 24 62 SFRR3 Filter 3 Shifted Final Result Register 0D8H U SV U SV Class 3 Page 24 63 1 The absolute register address is calculated as follows Module Base Address Offset Address shown in this column Table 24 6 Register Overview o...

Page 2283: ... 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the suspend mode EDIS 3 rw Sleep Mode Enable Control...

Page 2284: ... Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in suspend mode DM 15 14 rw Divider Mode This bit field selects normal divider mode fractional divider mode and off state RESULT 25 16 rh Result Value Bit field...

Page 2285: ...Digital Converter FADC User s Manual 24 32 V1 1 2011 05 FADC V2 21 DISCLK 31 rwh Disable Clock Hardware controlled disable for fFADC signal 0 10 27 26 r Reserved Read as 0 Should be written with 0 Field Bits Type Description ...

Page 2286: ...19 18 17 16 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV 7 0 r Module Revision This bit field indicates the revision number of the module implementation depending on the design step The given value of 00H is a placeholder for the actual number Bits 3 0 refer to the version of the digital part and bits 7 4 indicate the version of the an...

Page 2287: ... x 0FCH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR 13 rh Service Request Flag CLRR 14 w Request Clear Bit SETR 15 w Request Set B...

Page 2288: ...6 5 4 3 2 1 0 0 BSY 3 BSY 2 BSY 1 BSY 0 0 CRF 3 CRF 2 CRF 1 CRF 0 r rh rh rh rh r rh rh rh rh Field Bits Type Description CRFx x 0 3 x rh Conversion Request Flag This bit monitors whether a conversion request is pending for channel x CRFx is set by hardware when a trigger event is detected while the gating condition delivers 1 CRFx is automatically cleared by hardware when a conversion of the chan...

Page 2289: ...1 0B A conversion has not been finished 1B A conversion has been finished Bits IRQx can be set cleared by software via bits FMR SIRQx and FMR RIRQx IRQFn n 0 3 20 n rh Interrupt Request Flag for Filter n This bit indicates that a filter sequence of filter n has been finished new final result is available since it has been cleared by software Interrupt requests can also be generated while IRQ is st...

Page 2290: ...21 20 19 18 17 16 S IRQ F3 S IRQ F2 S IRQ F1 S IRQ F0 S IRQ 3 S IRQ 2 S IRQ 1 S IRQ 0 R IRQ F3 R IRQ F2 R IRQ F1 R IRQ F0 R IRQ 3 R IRQ 2 R IRQ 1 R IRQ 0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 S CRF 3 S CRF 2 S CRF 1 S CRF 0 0 R CRF 3 R CRF 2 R CRF 1 R CRF 0 r w w w w r w w w w Field Bits Type Description RCRFx x 0 3 x w Clear Conversion Request Flag This bit allow...

Page 2291: ...x 0 3 24 x w Set Interrupt Request Flag This bit allows bit CRSR IRQx to be set by software 0B No operation 1B Bit CRSR IRQx is set and an interrupt is generated if CFGRx IEN 1 SIRQFn n 0 3 28 n w Set Interrupt Request Flag for Filter n This bit allows bit CRSR IRQFn to be set by software 0B No operation 1B Bit CRSR IRQFn is set and an interrupt is generated if FCRn IEN 1 0 7 4 15 12 r Reserved Re...

Page 2292: ... Description EN01 1 rw Enable Neighbor Channel Trigger 01 This bit enables the neighbor channel trigger for channel 1 when a conversion of channel 0 is started 0B No action 1B A trigger will be generated EN02 2 rw Enable Neighbor Channel Trigger 02 This bit enables the neighbor channel trigger for channel 2 when a conversion of channel 0 is started 0B No action 1B A trigger will be generated EN03 ...

Page 2293: ...tion 1B A trigger will be generated EN21 17 rw Enable Neighbor Channel Trigger 21 This bit enables the neighbor channel trigger for channel 1 when a conversion of channel 2 is started 0B No action 1B A trigger will be generated EN23 19 rw Enable Neighbor Channel Trigger 23 This bit enables the neighbor channel trigger for channel 3 when a conversion of channel 2 is started 0B No action 1B A trigge...

Page 2294: ...triggers 2 2 triggers 3 and 3 triggers 0 etc It is in the responsibility of the user to set these bits in an appropriate way EN32 26 rw Enable Neighbor Channel Trigger 32 This bit enables the neighbor channel trigger for channel 2 when a conversion of channel 3 is started 0B No action 1B A trigger will be generated 0 0 7 4 9 15 12 18 23 20 31 27 r Reserved Read as 0 Should be written with 0 Field ...

Page 2295: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RST F3 RST F2 RST F1 RST F0 RCD 0 RCT 3 RCT 2 RCT 1 RCT 0 r w w w w w r w w w w Field Bits Type Description RCTx x 0 3 x w Reload Channel Timer 0B Channel x Timer will not be changed 1B Channel x Timer will be loaded with its reload value RCD 8 w Reset Common Divider 0B The common divider will not be changed 1B The common divider will be cleared RSTFn n 0 3 9 n w...

Page 2296: ... Priority Assignment Enable If the dynamic priority assignment is enabled the priority bit field CRPRIO is automatically changed as a function of the gating input signals In this case the channel that is active while the other three channels are not active gets the highest priority 0B The dynamic priority assignment is disabled 1B The dynamic priority assignment is enabled RESWEN 19 rw Result Writ...

Page 2297: ...nalog part is enabled CALMODE 25 24 rw Calibration Mode This bit field enables the calibration for offset and gain for the channel selected by CALCH 00B No calibration process is running All channels are in normal mode default after reset 01B The analog channel selected by CALCH is in offset calibration mode The other channels are in normal mode 10B Reserved 11B Reserved CALCH 27 26 rw Calibration...

Page 2298: ...TC1784 Fast Analog to Digital Converter FADC User s Manual 24 45 V1 1 2011 05 FADC V2 21 0 7 4 15 13 23 22 31 28 r Reserved Read as 0 Should be written with 0 Field Bits Type Description ...

Page 2299: ...fines which channel is converted if a trigger for channel 0 occurs 00B Channel 0 will be converted default 01B Channel 1 will be converted 10B Channel 2 will be converted 11B Channel 3 will be converted ALIAS1 3 2 rw Alias of Channel 1 This bit field defines which channel is converted if a trigger for channel 1 occurs 00B Channel 0 will be converted 01B Channel 1 will be converted default 10B Chan...

Page 2300: ...ed if a trigger for channel 3 occurs 00B Channel 0 will be converted 01B Channel 1 will be converted 10B Channel 2 will be converted 11B Channel 3 will be converted default 0 16 rw Placeholder Bit This bit position is a placeholder for further extensions and should be written with 0 0 31 17 15 8 r Reserved Read as 0 Should be written with 0 Field Bits Type Description ...

Page 2301: ...22 21 20 19 18 17 16 IEN 0 INP 0 CTREL rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CTF CTM TM GM TSEL GSEL r rw rw rw rw rw rw Field Bits Type Description GSEL 2 0 rw Gating Selection This bit field selects the gating source input signal for channel x 000B Gating source input signal GSA selected 001B Gating source input signal GSB selected 010B Gating source input signal GSC selected 011B...

Page 2302: ...SH selected GM 7 6 rw Gating Mode This bit field determines the functionality of the gating enable signal It determines whether and under which condition the generation of conversion requests by trigger signals is possible 00B Conversion requests are disabled and the Channel Timer is stopped CRFx never becomes set by hardware 01B Conversion requests and the Channel Timer are always enabled CRFx be...

Page 2303: ... TSEL CTM 11 10 rw Channel Timer Mode This bit determines the operating mode of channel x timer 00B Channel x timer is switched off 01B Channel timer is permanently running 10B Channel timer is running only if ECHTIMx 1 11B Reserved A Channel Timer trigger event is generated each time the channel x timer value reaches 00H While the Channel Timer is not running CTM 00B or signal ECHTIMx 0 the Chann...

Page 2304: ... when a conversion of channel x is finished while CFGRx IEN is set 00B Service request output SR0 is selected 01B Service request output SR1 is selected 10B Service request output SR2 is selected 11B Service request output SR3 is selected IEN 31 rw Interrupt Enable This bit enables the generation of a service request when a conversion of channel x is finished 0B Channel x conversion service reques...

Page 2305: ... 0 0 ENN ENP GAIN r r rw r rw r rw rw rw Field Bits Type Description GAIN 1 0 rw Amplifier Gain This bit field determines the amplifier gain for channel x 00B The selected amplifier gain is 1 01B The selected amplifier gain is 2 10B The selected amplifier gain is 4 11B The selected amplifier gain is 8 ENP 2 rw Enable Positive Input This bit enables the voltage measurement on the FAINxP analog inpu...

Page 2306: ...log input FAINxN line is connected to the channel amplifier The lower half of the measuring range is available CALOFF 2 0 10 8 rw Calibrate Offset This bitfield determines the signed value applied for the offset calibration for channel x The calibrate offset value is composed by the most significant bit CALOFF3 sign and bitfield CALOFF 2 0 resulting in a 4 bit bitfield CALOFF 3 0 CALOFF3 12 rw 0 7...

Page 2307: ...RCHx x 0 3 Channel x Conversion Result Register 040H x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ADRES r rwh Field Bits Type Description ADRES 9 0 rwh AD Conversion Result This bit field contains the conversion result of channel x ADRES can only be overwritten by software if GCR RESWEN 1 0 31 10 r Reserved Read as 0 Should...

Page 2308: ...4 3 2 1 0 IEN 0 INP 0 INSEL 0 MAVL 0 ADDL rw r rw r rw r rw r rw Field Bits Type Description ADDL 2 0 rw Addition Length This bit field determines the number of filter input values that are added to obtain one intermediate result 000B Each filter input value is considered as intermediate result 001B 2 filter input values are added up 010B 3 filter input values are added up 011B 4 filter input valu...

Page 2309: ...ue FRRn FR CRRn CR 01B A moving average of 2 values is selected The final result is calculated by 2 values FRRn FR CRRn CR IRR1n IR 10B A moving average of 3 values is selected The final result is calculated by 3 values FRRn FR CRRn CR IRR1n IR IRR2n IR 11B A moving average of 4 values is selected The final result is calculated by 4 values FRRn FR CRRn CR IRR1n IR IRR2n IR IRR3n IR Bit combination...

Page 2310: ...nput value is the output value final result of filter block 2 011B Reserved 100B Channel 0 conversion result is taken as filter input value 101B Channel 1 conversion result is taken as filter input value 110B Channel 2 conversion result is taken as filter input value 111B Channel 3 conversion result is taken as filter input value INP 13 12 rw Interrupt Node Pointer This bit field selects which ser...

Page 2311: ...20 19 18 17 16 0 MAVS 0 AC 0 CR r rh r rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR rh Field Bits Type Description CR 18 0 rh Current Result This bit field significant bits 13 0 for filters 0 and 2 18 0 for filters 1 and 3 contains the right aligned current result value of filter 0 CR is cleared when writing GCR RSTFn 1 AC 26 24 rh Addition Count This bit field indicates the number of addition...

Page 2312: ...cates the end of a filter calculation operation Since the filter calculation is executed very fast in comparison to a conversion MAVS 0 can be interpreted only as a kind of calculation busy flag Therefore it is recommended to read a valid filter result from register FRRn only when the corresponding interrupt request flag CRSR IRQFn is set MAVS is reset when writing GCR RSTFn 1 0 23 19 27 31 30 r R...

Page 2313: ...000H IRRy2 y 1 3 Filter 2 Intermediate Result Register y 0A4H y 4H Reset Value 0000 0000H 31 13 12 0 0 IR r rh Field Bits Type Description IR 12 0 rh Intermediate Result This bit field contains the right aligned intermediate result IR is cleared when writing GCR RSTFn 1 0 31 13 rh Reserved Read as 0 Should be written with 0 IRR11 Filter 1 Intermediate Result Register 1 088H Reset Value 0000 0000H ...

Page 2314: ...s Manual 24 61 V1 1 2011 05 FADC V2 21 Field Bits Type Description IR 17 0 rh Intermediate Result This bit field contains the right aligned intermediate result IR is reset when writing GCR RSTFn 1 0 31 18 rh Reserved Read as 0 Should be written with 0 ...

Page 2315: ...nal Result Register 0B4H Reset Value 0000 0000H 31 15 14 0 0 FR r rh Field Bits Type Description FR 14 0 rh Final Result This bit field contains the right aligned final result FR is cleared when writing GCR RSTFn 1 0 31 15 rh Reserved Read as 0 Should be written with 0 FRR1 Filter 1 Final Result Register 094H Reset Value 0000 0000H FRR3 Filter 3 Final Result Register 0D4H Reset Value 0000 0000H 31...

Page 2316: ...ations for further treatment SFRR1 Filter 1 Shifted Final Result Register 098H Reset Value 0000 0000H SFRR3 Filter 3 Shifted Final Result Register 0D8H Reset Value 0000 0000H 31 15 14 0 0 FR r rh Field Bits Type Description FR 14 0 rh Final Result This bit field contains the right aligned final result from the corresponding final result register FRRn shifted right by 5 bit positions FR is cleared ...

Page 2317: ...FADC kernel register names described in this section are referenced in other parts of the TC1784 User s Manual by the module name prefix FADC_ Table 24 7 Registers Address Space FADC Module Module Base Address End Address Note FADC F010 0400H F010 05FFH Table 24 8 Registers Overview Register Short Name Register Long Name Offset Address Page Number intentionally left blank please refer to register ...

Page 2318: ...ule Figure 24 15 FADC Module Implementation and Interconnections Clock Control Address Decoder TC1784_FADC_impl VFAGND VDDAF 1 2V VDDMF 3 3V VFAREF VSSMF 0V Interrupt Control TS H A GS H A fFADC fCLC SR 1 0 FAIN2P FAIN2N FAIN3P FAIN3N DMA SR 3 0 FADC Module Kernel AN32 FAIN0P FAIN0N FAIN1P FAIN1N AN33 AN34 AN35 ADC1 Module Kernel AN28 CH12 CH13 CH14 CH15 AN29 AN30 AN31 VDDIF VDDM 3 3 5V VSSM 0V VS...

Page 2319: ...ed to the power supply of the ADC VDDMF VDDMF I analog power supply 3 3 V connected also to ADCx_VDDA VSSMF VSSMF I analog power ground VDDAF VDDAF I analog power supply 1 2V VSSAF VSSMF I analog power ground connected to VSSMF pin VFAREF VFAREF I positive analog reference VFAGND VFAGND I negative analog reference FAIN0P AN32 I analog input P channel 0 FAIN0N AN33 I analog input N channel 0 FAIN1P...

Page 2320: ...l Part in TC1784 FADC Signal of Digital Part from to Module or Pin Inputor Output Can be used to as Gating Inputs GSA REQ0 I P3 10 GSB REQ4 I P0 14 GSC PDOUT2 I ERU GSD PDOUT3 I ERU GSE TRIG11 I GPTA GSF TRIG13 I GPTA GSG TRIG15 I GPTA GSH TRIG17 I GPTA Trigger Inputs TSA REQ1 I P3 11 TSB REQ5 I P0 15 TSC IOUT2 I ERU TSD IOUT3 I ERU TSE TRIG00 I GPTA TSF TRIG02 I GPTA TSG TRIG04 I GPTA TSH TRIG06 ...

Page 2321: ... FADC User s Manual 24 68 V1 1 2011 05 FADC V2 21 Table 24 11 FADC Service Request Connections in TC1784 Service Request Signal Connected to Service Request Node FADC_SR 0 FADC_SRC0 FADC_SR 1 FADC_SRC1 FADC_SR 2 FADC_SRC2 FADC_SR 3 FADC_SRC3 ...

Page 2322: ... clock that is used in the FADC as the clock for the channel timer and other internal timings such as the conversion timing The fractional divider registers FADC_FDR controls the frequency of fFADC and allows it to be enabled disabled independently of fCLC Figure 24 16 FADC Clock Generation The following formulas define the frequency of fFADC 24 2 24 3 Equation 24 2 is valid for FADC_FDR DM 01B no...

Page 2323: ...Rx 23 103 RESR0 23 98 RESRD0 23 98 RESRDx 23 100 RESRx 23 100 RNPRx 23 109 RSIRx 23 29 RSPRx 23 48 SRCx 23 28 SYNCTR 23 128 VFR 23 102 ASC Asynchronous mode 16 4 16 8 Data frames 16 5 Baud rate generation 16 12 16 16 Asynchronous modes 16 13 Synchronous mode 16 16 Block diagram Asynchronous modes 16 4 Synchronous mode 16 9 DMA request outputs 16 40 Error detection 16 17 Features 1 27 16 2 Implemen...

Page 2324: ...114 Interfaces 19 109 Interrupt control 19 116 Module clock generation 19 111 MultiCAN Bit timing 19 21 Block diagram 19 14 Clock generation 19 17 Interrupt structure 19 16 Message acceptance filtering 19 34 Message object data handling 19 41 Message object FIFO 19 48 Message object functionality 19 47 Message object interrupts 19 37 Message object lists 19 26 Node control 19 20 Node interrupts 19...

Page 2325: ...4 Bus Switch Priorities of DMA Move En gines 11 24 Channel operation 11 7 Channel operation modes 11 12 Channel request control 11 11 Channel reset operation 11 17 Circular buffer 11 20 Control Registers Offset addresses 11 49 Debug capabilities 11 28 Definition of terms 11 5 DMA Principle 11 6 Error conditions 11 16 Features 11 4 Implementation diagram 11 101 Interrupts 11 31 Channel interrupts 1...

Page 2326: ...xtual conventions 1 1 E EBU Address region selection 12 18 Asynchronous accesses Demultiplexed read cycles 12 35 Signals 12 30 Wait control 12 41 Registers ADDRSELx 12 52 BUSRAPx 12 59 BUSRCONx 12 54 12 57 BUSWAPx 12 62 CLC 12 48 EXTBOOT 12 51 MODCON 12 49 Offset addresses 12 45 Overview 12 45 USERCON 12 65 EBU_ADDRSEL0 12 52 EEPROM emulation 5 15 Emergency stop output control 3 146 Register SCU_E...

Page 2327: ...controller control 20 84 20 109 Communication controller status 20 111 20 133 CREL 20 162 CUST1 20 17 CUST3 20 20 Customer registers 20 16 EIER 20 61 EIES 20 56 EILS 20 48 EIR 20 37 ENDN 20 164 ESIDnn nn 01 015 20 129 FCM 20 140 FRF 20 137 FRFM 20 139 FSR 20 145 GTUC01 20 99 GTUC02 20 100 GTUC03 20 101 GTUC04 20 102 GTUC05 20 103 GTUC06 20 104 GTUC07 20 105 GTUC08 20 106 GTUC09 20 107 GTUC10 20 10...

Page 2328: ...SUCC3 20 93 SWINIT 20 123 T1C 20 79 Test registers 20 23 TEST1 20 23 TEST2 20 28 20 31 20 33 20 34 TINT0SRC 20 275 TINT1SRC 20 275 TOC 20 77 TXRQ1 20 150 TXRQ2 20 151 TXRQ3 20 152 TXRQ4 20 153 WRDSnn nn 01 64 20 165 WRHS 20 166 WRHS2 20 169 WRHS3 20 170 Symbol processing 20 5 System universal control 20 5 Transient buffer 20 4 ESR Registers ESRCFG0 3 78 ESRCFG1 3 78 SCU_IOCR 3 79 External request ...

Page 2329: ... 53 Flash status definition 5 46 Handling Errors During Operation 5 79 Handling Errors During Startup 5 84 Interrupt control 5 78 Margin Check Control 5 61 Margin control 5 60 Operating modes 5 28 Operational overview 5 17 Page addresses 5 42 Pages 5 14 Physical and logical sectors 5 14 Program Flash features 1 21 Program quality check 5 19 Program verify 5 19 Programming control 5 18 Protection c...

Page 2330: ...4 Programming hints 21 158 Pseudo code description 21 126 21 155 Registers Address ranges 21 295 Signal generation cells SGC Global timer cell 21 55 Global timers 21 38 Local timer cell 21 67 GPTA0 Registers CKBCTR 21 182 CLC 21 288 DBGCTR 21 292 DCMCAVk 21 175 DCMCOVk 21 175 DCMCTRk 21 173 DCMTIMk 21 174 FDR 21 289 FPCCTRk 21 168 FPCSTAT 21 167 FPCTIMk 21 170 GIMCRHg 21 213 GIMCRLg 21 211 GTCCTRk...

Page 2331: ... Control Registers Offset ad dresses 4 18 Registers CON 4 20 LFI_ID 4 19 Overview 4 18 LMB 4 3 Basic operation 4 5 Default master 4 7 Features 4 3 Terms 4 3 Transaction types 4 3 LMB BCU LBCU Control Registers Offset ad dresses 4 8 Registers LBCU_ID 4 10 LBCU_LEADDR 4 13 LBCU_LEATT 4 11 LBCU_LEDATH 4 14 LBCU_LEDATL 4 14 LBCU_SRC 4 15 LMB External Bus Unit see EBU Local Memroy Bus 4 3 LTCA2 Registe...

Page 2332: ... 137 22 148 Transfer window map 22 150 Naming conventions 22 4 Receiver I O line control 22 54 Registers AER 22 92 AER1 22 92 ARR 22 93 ARR0 22 93 ARR1 22 93 FDR 22 81 GINTR 22 85 Offset addresses 22 79 OICR 22 88 Overview 22 78 RADRR 22 121 RCR 22 116 RDATAR 22 122 RIER 22 123 RINPR 22 128 RISR 22 126 RPxBAR 22 120 RPxSTATR 22 119 SCR 22 86 TCBAR 22 109 TCR 22 95 TDRAR 22 107 TIER 22 110 TINPR 22...

Page 2333: ...60 USR 18 39 Upstream channel 18 21 Baud rate 18 25 Block diagram 18 21 Data frame protocol 18 22 Data reception 18 23 18 24 Input control 18 30 Parity checking 18 22 Sampling 18 26 O OCDS Cerberus 15 10 Communication mode 15 11 Features 15 10 Multi core break switch 15 11 Registers 15 14 RW mode 15 10 Triggered transfers 15 11 Components 15 4 JTAG interface 15 13 Registers 15 14 OCDS level 1 15 5...

Page 2334: ...CP_SRC3 10 89 PCP_SRC4 10 90 PCP_SRC5 10 90 PCP_SRC6 10 90 PCP_SRC7 10 90 PCP_SRC8 10 90 PCP_SRC9 10 91 PCP_SSR 10 77 Peripheral control processor see PCP PLL 3 7 3 15 Features 3 7 3 15 Functionality 3 7 3 16 PMI Features 2 72 Registers 2 76 PMI_CON0 2 77 PMI_CON1 2 78 PMI_CON2 2 79 PMI_ID 2 82 PMI_STR 2 81 PMI Program memory interface 2 72 PMU 5 1 Block diagram 1 18 5 2 Boot ROM 5 3 Data access o...

Page 2335: ...nctions 9 2 Port 1 9 28 Port 2 9 37 Port 3 9 43 Port 4 9 52 Port 5 9 56 Port 6 9 63 Port 7 9 67 9 84 Port 8 9 74 Port 9 9 80 Registers 9 5 Input output control registers 3 78 9 8 Power Management Register PMCSR 3 113 Power management 3 111 Idle mode 3 112 Mode definitions 3 111 Sleep mode 3 113 Processor subsystem Core debug registers 2 56 CPU Block diagram 2 3 CSFRs 2 17 Execution unit 2 5 Featur...

Page 2336: ...CU_ID 3 177 SCU_MANID 3 178 SCU_RTID 3 178 Registers SCU_DTSCON 3 128 SCU_DTSSTAT 3 129 Sleep mode 3 113 SSC Baud rate generation 17 14 17 48 Baud rate generation formulas 17 49 Block diagram 17 4 Chip select generation 17 17 Continuous transfer 17 10 DMA request outputs 17 46 Error detection 17 20 Full duplex operation 17 6 Half duplex operation 17 9 Interrupts 17 20 Module implementation 17 43 D...

Page 2337: ...2 14 12 STM_TIM3 14 12 STM_TIM4 14 12 STM_TIM5 14 13 STM_TIM6 14 13 Resolutions and ranges 14 4 T temperature measurement 3 127 Tuning Protection 5 9 W Watchdog Timer Period calculation 3 135 Watchdog timer 3 130 3 145 During power saving modes 3 138 Endinit function 3 131 Features 3 130 Modify access to WDT_CON0 3 134 Operating modes Disable mode 3 136 Normal mode 3 136 Prewarning mode 3 136 Time...

Page 2338: ...2 ADC_QINRx 23 74 ADC_QMRx 23 65 ADC_QSRx 23 68 ADC_RCRx 23 103 ADC_RESR0 23 98 ADC_RESRD0 23 98 ADC_RESRDx 23 100 ADC_RESRx 23 100 ADC_RNPRx 23 109 ADC_RSIRx 23 29 ADC_RSPRx 23 48 ADC_SYNCTR 23 128 ADC_VFR 23 102 ADC0_CLC 23 25 ADC0_KSCFG 23 26 ADC0_SRCx 23 28 ASC module registers 16 19 ASC0 register address map 16 41 ASC0_BG 16 27 16 41 ASC0_CLC 16 33 16 41 ASC0_CON 16 22 16 41 ASC0_ESRC 16 39 1...

Page 2339: ...CAN_NFCRx 19 84 CAN_NIPRx 19 78 CAN_NPCRx 19 80 CAN_NSRx 19 74 CAN_PANCTR 19 59 CAN_SRCm 19 118 CBS_COMDATA 15 16 CBS_ICTSA 15 16 CBS_ICTTA 15 16 CBS_INTMOD 15 16 CBS_IOSR 15 16 CBS_JDPID 15 16 CBS_MCDBBS 15 16 CBS_MCDBBSS 15 16 CBS_MCDSSG 15 16 CBS_MCDSSGC 15 16 CBS_OCNTRL 15 16 CBS_OEC 15 16 CBS_OSTATE 15 16 CBS_SRC 15 16 CCDIER 2 35 CCPIER 2 35 COMPAT 2 18 2 23 CPM0 2 32 CPM1 2 32 CPM2 2 32 CPM...

Page 2340: ...1 54 DMA_INTCR 11 78 DMA_INTSR 11 74 DMA_ME0AENR 11 82 DMA_ME0ARR 11 84 DMA_ME0PR 11 81 DMA_ME0R 11 81 DMA_ME1AENR 11 82 DMA_ME1ARR 11 84 DMA_ME1PR 11 81 DMA_ME1R 11 81 DMA_MESR 11 79 DMA_MLI0SRC0 11 52 11 124 DMA_MLI0SRC1 11 52 11 124 DMA_MLI0SRC2 11 52 11 124 DMA_MLI0SRC3 11 52 11 124 DMA_OCDSR 11 55 DMA_SADR0x 11 98 DMA_SADR1x 11 98 DMA_SHADR0x 11 100 DMA_SHADR1x 11 100 DMA_SRC0 11 52 11 123 DM...

Page 2341: ...12 54 EBU_BUSRCON2 12 54 EBU_BUSRCON3 12 54 EBU_BUSWAP0 12 62 EBU_BUSWAP1 12 62 EBU_BUSWAP2 12 62 EBU_BUSWAP3 12 62 EBU_BUSWCON0 12 57 EBU_BUSWCON1 12 57 EBU_BUSWCON2 12 57 EBU_BUSWCON3 12 57 EBU_CLC 12 48 EBU_EXTBOOT 12 51 EBU_ID 12 65 EBU_MODCON 12 49 EBU_USERCON 12 65 EICR0 3 97 EICR1 3 100 EIFR 3 104 ERAY_ACS 20 11 20 126 ERAY_CCEV 20 10 20 116 ERAY_CCSV 20 10 20 111 ERAY_CLC 20 8 20 264 ERAY_...

Page 2342: ... 20 275 ERAY_NDAT1 20 12 20 154 ERAY_NDAT1SRC 20 13 20 275 ERAY_NDAT2 20 12 20 155 ERAY_NDAT3 20 12 20 156 ERAY_NDAT4 20 12 20 157 ERAY_NDIC1 20 12 20 266 ERAY_NDIC2 20 12 20 267 ERAY_NDIC3 20 12 20 268 ERAY_NDIC4 20 13 20 269 ERAY_NEMC 20 9 20 94 ERAY_NMVx x 1 3 20 11 20 133 ERAY_OBCM 20 14 20 187 ERAY_OBCR 20 15 20 190 ERAY_OBUSYSRC 20 13 20 275 ERAY_OCV 20 11 20 120 ERAY_OSIDnn nn 01 15 20 11 2...

Page 2343: ...ASH0_MARD 5 63 FLASH0_MARP 5 62 FLASH0_PROCON0 5 69 FLASH0_PROCON1 5 71 FLASH0_PROCON2 5 73 FLASH1_FSR 5 46 FMR 3 104 FPU_ID 2 33 2 34 FPU_TRAP_CON 2 33 FPU_TRAP_OPC 2 33 FPU_TRAP_PC 2 33 FPU_TRAP_SRC1 2 33 FPU_TRAP_SRC2 2 33 FPU_TRAP_SRC3 2 33 G GPTA0_CKBCTR 21 182 GPTA0_CLC 21 288 GPTA0_DBGCTR 21 292 GPTA0_DCMCAVk 21 175 GPTA0_DCMCOVk 21 175 GPTA0_DCMCTRk 21 173 GPTA0_DCMTIMk 21 174 GPTA0_EDCTR ...

Page 2344: ... 4 19 LTCA2_LIMCRH 21 267 LTCA2_LIMCRL 21 266 LTCA2_LTCCTR31 21 256 LTCA2_LTCCTRk 21 247 LTCA2_LTCXR31 21 258 LTCA2_LTCXRk 21 258 LTCA2_MRACTL 21 259 LTCA2_MRADIN 21 261 LTCA2_MRADOUT 21 261 LTCA2_OMCRH 21 264 LTCA2_OMCRL 21 263 LTCA2_SRCk 21 294 LTCA2_SRSC2 21 224 LTCA2_SRSC3 21 226 LTCA2_SRSS2 21 225 LTCA2_SRSS3 21 227 M MCHK_ID 11 129 MCHK_IRx 11 130 MCHK_RRx 11 130 MCHK_WR 11 131 Memory Checke...

Page 2345: ...ATR 22 98 22 151 MLI1 register address map 22 154 MLI1_AER 22 92 MLI1_AER0 22 92 22 157 MLI1_AER1 22 92 22 157 MLI1_ARR 22 93 MLI1_ARR0 22 93 22 157 MLI1_ARR1 22 93 22 157 MLI1_FDR 22 154 MLI1_GINTR 22 157 MLI1_ID 22 154 MLI1_OICR 22 157 MLI1_RADRR 22 156 MLI1_RCR 22 155 MLI1_RDATAR 22 156 MLI1_RIER 22 156 MLI1_RINPR 22 157 MLI1_RISR 22 156 MLI1_RP0BAR 22 156 MLI1_RP0STATR 22 156 MLI1_RP1BAR 22 15...

Page 2346: ...6 9 6 10 OVC_RABRx 6 11 6 13 6 15 Overlay memory control registers 6 8 P P0_ESR 9 19 P0_IN 9 20 P0_IOCR0 9 8 P0_IOCR12 9 11 P0_IOCR4 9 9 P0_IOCR8 9 10 P0_OMR 9 17 P0_OUT 9 16 P0_PDR 9 27 P1_ESR 9 19 P1_IN 9 20 P1_IOCR0 9 8 P1_IOCR12 9 11 P1_IOCR4 9 9 P1_IOCR8 9 10 P1_OUT 9 16 P1_PDR 9 35 P2_ESR 9 19 P2_IN 9 20 P2_IOCR0 9 8 P2_IOCR12 9 11 P2_IOCR4 9 9 P2_IOCR8 9 10 P2_OMR 9 17 P2_OUT 9 16 P2_PDR 9 ...

Page 2347: ...10 87 PCP_SRC10 10 91 PCP_SRC11 10 91 PCP_SRC2 10 89 PCP_SRC3 10 89 PCP_SRC4 10 90 PCP_SRC5 10 90 PCP_SRC6 10 90 PCP_SRC7 10 90 PCP_SRC8 10 90 PCP_SRC9 10 91 PCP_SSR 10 77 PCXI 2 17 PDRR 3 105 PIEAR 2 35 2 43 PIETR 2 35 2 42 PMI_CON0 2 76 2 77 PMI_CON1 2 76 2 78 PMI_CON2 2 76 2 79 PMI_ID 2 76 2 82 PMI_STR 2 76 2 81 PMU0_ID 5 8 PMU0_OVRCON 5 5 PSW 2 17 2 19 R RSTCNTCON 3 72 S SBCU control registers...

Page 2348: ... 39 SSC module registers 17 28 SSC0 register address map 17 59 SSC0_BR 17 41 17 59 SSC0_CLC 17 50 17 59 SSC0_CON 17 31 17 59 SSC0_EFM 17 36 17 59 SSC0_ESRC 17 58 17 60 SSC0_FDR 17 51 17 59 SSC0_ID 17 28 17 59 SSC0_PISEL 17 29 17 59 SSC0_RB 17 42 17 59 SSC0_RSRC 17 58 17 60 SSC0_SSOC 17 38 SSC0_SSOTC 17 39 17 59 SSC0_STAT 17 34 17 59 SSC0_TB 17 42 17 59 SSC0_TSRC 17 58 17 59 SSC1 register address m...

Page 2349: ...TM_CLC 14 9 14 22 STM_CMCON 14 15 14 22 STM_CMP0 14 14 14 22 STM_CMP1 14 14 14 22 STM_ICR 14 17 14 22 STM_ID 14 10 14 22 STM_ISRR 14 19 14 22 STM_SRC0 14 20 14 22 STM_SRC1 14 20 14 22 STM_TIM0 14 11 14 22 STM_TIM1 14 11 14 22 STM_TIM2 14 12 14 22 STM_TIM3 14 12 14 22 STM_TIM4 14 12 14 22 STM_TIM5 14 13 14 22 STM_TIM6 14 13 14 22 SWEVT 2 57 SWRSTCON 3 75 SYSCON 2 17 T TR0EVT 2 57 TR1EVT 2 57 W WDT_...

Page 2350: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG Doc_Number ...

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