Infineon Technologies TC1784, User Manual

Page: 2125 / 2350

TC1784
Analog to Digital Converter (ADC)
User´s Manual 23-19 V1.1, 2011-05
ADC, V1.3
QBUR4 Queue 4 Backup
Register 0CC
H
U, SV U, SV Class 3 Page 23-72
QINR4 Queue 4 Input Register 0CC
H
U, SV U, SV Class 3 Page 23-74
Channel Registers (available in the address range of each kernel)
CHCTRx
(x = 0 -15) Channel x Control
Register 100
H
+
x * 4
U, SV U, SV Class 3 Page 23-81
INPCRx
(x = 0 -3) Input Class x Register 050
H
+
x * 4
U, SV U, SV Class 3 Page 23-83
ALR0 Alias Register 0 210
H
U, SV U, SV Class 3 Page 23-84
LCBRx
(x = 0 - 3) Limit Check Boundary
Register x 0F0
H
+
x * 4
U, SV U, SV Class 3 Page 23-85
CHFR Channel Flag Register 060
H
U, SV U, SV Class 3 Page 23-86
CHFCR Channel Flag Clear
Register 064
H
U, SV U, SV Class 3 Page 23-87
CHENPR0 Channel Event Node
Pointer Register 0
068
H
U, SV U, SV Class 3 Page 23-88
CHENPR8 Channel Event Node
Pointer Register 8
06C
H
U, SV U, SV Class 3 Page 23-89
Result Registers (available in the address range of each kernel)
RESR0 Result Register 0 180
H
U, SV U, SV Class 3 Page 23-98
RESRx
(x = 1 - 15) Result Register x 180
H
+
x * 4
U, SV U, SV Class 3 Page 23-100
RESRD0 Result Register 0
for Debugging 1C0
H
U, SV U, SV Class 3 Page 23-98
RESRDx
(x = 1 - 15) Result Register x
for Debugging 1C0
H
+
x * 4
U, SV U, SV Class 3 Page 23-100
Table 23-2 Register Overview of ADC (cont’d)
Short
Name Description Offset
Addr.
1)
Access Mode Reset Description
See
Read Write