Infineon Technologies TC1784, User Manual

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-3 V1.1, 2011-05
DMA, V3.03
11.2 DMA Controller Kernel Description
The DMA Controller of the TC1784 transfers data from data source locations to data
destination locations without intervention of the CPU or other on-chip devices. One data
move operation is controlled by one DMA channel. Eight DMA channels are provided in
one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Blocks
to the two On Chip Bus interfaces and a DMA Peripheral interface. In the TC1784, the
two On Chip Bus interfaces are connected to the System Peripheral Bus and the
LMB Bus. The DMA Peripheral interface provides a connection to the Cerberus module,
Micro Link Interface module and other DMA-related devices (Memory Checker module
in the TC1784). Clock control, address decoding, DMA request wiring, and DMA
interrupt service request control are implementation-specific and are managed outside
the DMA controller kernel.
The index “m” in the following block diagram refers to the DMA Sub-Block number
(m = 0-1).
Figure 11-1 DMA Block Diagram
Interrupt
Request
Nodes
MCB06149
Clock
Control
f
DMA
SR[15:0]
DMA Controller
Arbiter/
Switch
Control
Bus
Switch
FP
I B
us
In
te
rf
ac
e
LM
B
B
us
In
te
rf
a
ce
P
er
iph
er
a
l
In
te
rf
ac
e
Cerberus
MLI0
System
Peripheral
Bus
LMB Bus
DMA
Requests
of
On-chip
Periph.
Units
Address
Decoder
DMA Interrupt Control
CH0n_OUT
DMA
Channels
00-07
DMA Sub-Block m
Request
Selection/
Arbitration
Transaction
Control Unit
Memory
Checker