Infineon Technologies TC1784, User Manual

Page: 1900 / 2350

TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-248 V1.1, 2011-05
GPTA
®
v5, V1.14
PEN 4 rw ILM = 1: LTC Prescaler Enable
0
B
LTC Prescaler Mode is disabled
1
B
LTC Prescaler Mode with LTC prescaler clock
LTCPRE is enabled
FED 5 rw ILM = 0: Input Falling Edge Select
0
B
Timer is not updated by a falling edge
1
B
Timer is updated by a falling edge on the LTCkIN input
line
AIL 5 rw ILM = 1: Active Input Level Select
0
B
Input signal is active high
1
B
Input signal is active low
SLO 6 rwh Select Line Output
0
B
State of select line output SO is 0
1
B
State of select line output SO is 1
SLO is bit protected (see Page 21-167 ).
CUDCLR 7 w Coherent Update Disable
0
B
No effect
1
B
Coherent update disabled (bit CUD is cleared)
If bits CUD and CUDCLR are both written with 1, bit CUD will
be set. CUDCLR is always read as 0.
ILM 8 rw Input Line Mode
0
B
Input line is operating in Edge Sensitive Mode.
1
B
Input line is operating in Level Sensitive Mode.
In case of full speed GPTA
®
v5 module clock selection as
input clock, Level Sensitive Mode must be selected. In this
case the Edge Sensitive Mode will not produce any event.
CUD 9 rwh Coherent Update Enable
0
B
Select output SO is not toggled on timer reset overflow
1
B
Select output SO is toggled on next timer reset
overflow
When CUD is set by software (writing CUD and CUDCLR
both with 1), it remains set until the next timer reset overflow
(LTCk reset event) occurs and is cleared by hardware
afterwards. CUD can be reset by software by writing bit
CUDCLR with 1 and CUD with 0.
CEN 10 rh Cell Enable
0
B
LTCk is currently disabled for local events
1
B
LTCk is currently enabled for local events
Field Bits Type Description