Infineon Technologies TC1784, User Manual

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-32 V1.1, 2011-05
GPTA
®
v5, V1.14
Steady Input Signal Example
In the following example, the input signal’s period length is 13
f
GPTA
clock periods, which
should be subdivided into three equally spaced sections. The reload value to be stored
in PLLREV.REV register is calculated to 0A
H
(10 = 13 - 3). PLLMTI.MTI is loaded with
03
H
(number of output pulses) and its 2-complement representation (FFFD
H
) is written
into PLLSTP.STP.
After a reset, a state machine driven by the GPTA
®
v5 module clock, updates the delta
register PLLDTR with the reload value. Afterwards, the PLLSTP register’s contents are
continuously added to the delta register value (
Figure 21-20 ). In fact, the difference
between both values is computed and stored in the PLLDTR register again, because the
PLLSTP register has been loaded with a negative value (2-complement data format).
When the PLLDTR register has been decremented to a negative value, the reload
register contents are added to Delta register’s current contents.
A rising edge detected on the selected input signal triggers the counter register PLLCNT
to load the number of requested output pulses from PLLMTI. When a negative content
of the PLLDTR register is detected, the microtick counter is decremented by one. In
Automatic Mode (AEN = 1), the output pulse generation is stopped when the microtick
counter reaches zero.
The period length of a single output pulse varies between four and five
f
GPTA
clocks; the
maximum period length variation of output pulses is restricted to one
f
GPTA
clock. The
total period length of all three output pulses, generated by one PLL loop corresponds to
the input signal period width (5 + 4 + 4 = 13
f
GPTA
clocks).
Figure 21-20 Digital PLL Steady State Simulation
MCT05929_mod
PLL Input
Signal
-1
-3
-2
-1
-3
-2
-1
2
1
0
3
2
1
3
0
4
5
6
3
4
5
6 6
7 7
8 8
9 9
Ticks
PLL Output
Signal
PLLDTR
Content
9