Infineon Technologies TC1784, User Manual

Page: 2126 / 2350

TC1784
Analog to Digital Converter (ADC)
User´s Manual 23-20 V1.1, 2011-05
ADC, V1.3
VFR Valid Flag Register 200
H
U, SV U, SV Class 3 Page 23-102
RCRx
(x = 0 - 15) Result Control Register
x 140
H
+
x * 4
U, SV U, SV Class 3 Page 23-103
EVFR Event Flag Register 070
H
U, SV U, SV Class 3 Page 23-105
EVFCR Event Flag Clear
Register 074
H
U, SV U, SV Class 3 Page 23-107
EVNPR Source Event Node
Pointer Register 078
H
U, SV U, SV Class 3 Page 23-108
RNPR0 Result Node Pointer
Register 0 208
H
U, SV U, SV Class 3 Page 23-109
RNPR8 Result Node Pointer
Register 8 20C
H
U, SV U, SV Class 3 Page 23-110
Additional Feature Registers (available in the address range of each kernel)
APR Access Protection
Register 218
H
U, SV SV, E Class 3 Page 23-123
EMCTR External Multiplexer
Control Register 220
H
U, SV U, SV Class 3 Page 23-124
SYNCTR Synchronization Control
Register 048
H
U, SV U, SV Class 3 Page 23-128
BWDENR Broken Wire Detection
Enable Register 224
H
U, SV U, SV Class 3 Page 23-130
BWDCFG
R Broken Wire Detection
Configuration Register 228
H
U, SV U, SV Class 3 Page 23-131
1) The absolute register address is calculated as follows:
Module Base A Offset Address (shown in this column)
Table 23-2 Register Overview of ADC (cont’d)
Short
Name Description Offset
Addr.
1)
Access Mode Reset Description
See
Read Write