Infineon Technologies TC1784, User Manual

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TC1784
Micro Link Interface (MLI)
User´s Manual 22-97 V1.1, 2011-05
MLI, V2.0
MDP [13:10] rw Maximum Delay for Parity Error
This bit field determines a window for the transmitter in
number of TCLK clock periods where a TREADY low-
to-high signal transition signal is considered as
“correctly received” condition (see
Page 22-22 ).
0000
B
Zero clock periods selected (not useful)
0001
B
1 clock period selected
…
B
…
1110
B
14 clock periods selected
1111
B
15 clock periods selected
NO 14 rw No Optimized Method
This bit field enables/disables the address prediction
for read or Write Frames (see
Page 22-47 ).
0
B
Optimized method (address prediction) enabled.
1
B
Optimized method (address prediction) disabled.
TP 15 rw Type of Parity
This bit will determines the type of parity used in frame
transmissions. For correct data transfers, TP = 0 has to
be programmed. The value TP = 1 can be selected to
force parity errors to analyze the propagation delay
(see
Page 22-26 ).
0
B
Even parity is selected.
1
B
Odd parity selected.
TDEL [19:16] rw Transmission Delay
This bit field defines a delay in cycles of
f
SYS
of the
transmitter between the reception of the rising edge of
RREADY and the next possible frame start (see
Page 22-51 ).
0000
B
No transmission delay selected
0001
B
One
f
SYS
cycle delay selected
...
B
...
1110
B
Fourteen
f
SYS
cycles delay selected
1111
B
Fifteen
f
SYS
cycles delay selected
0 2, 3,
[31:20] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description