Infineon Technologies TC1784, User Manual

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-88 V1.1, 2011-05
DMA, V3.03
CHMODE 20 rw Channel Operation Mode
CHMODE determines the reset condition for control bit
TRSR.HTREmn of DMA channel mn.
0
B
Single Mode operation is selected for DMA
channel mn. After a transaction, DMA channel mn
is disabled for further hardware requests
(TRSR.HTREmn is reset by hardware)
TRSR.HTREmn must be set again by software for
starting a new transaction.
1
B
Continuous Mode operation is selected for DMA
channel mn. After a transaction, bit
TRSR.HTREmn remains set
CHDW [22:21] rw Channel Data Width
CHDW determines the data width for the read and write
moves of DMA channel mn.
00
B
8-bit (byte) data width for moves selected
01
B
16-bit (half-word) data width for moves selected
10
B
32-bit (word) data width for moves selected
11
B
Reserved
PATSEL [25:24] rw Pattern Select
This bit field selects the mode of the pattern detection
logic. Depending on the channel data width, PATSEL
selects different pattern detection configurations.
If pattern detection is enabled (PATSEL not equal 00
B
),
the pattern detection interrupt line will be activated on
the selected pattern match.
8-bit channel data width (CHDW = 00
B
):
Selected pattern detection configuration see Table 11-4
on Page 11-41 .
16-bit channel data width (CHDW = 01
B
):
Selected pattern detection configuration see Table 11-5
on Page 11-42 .
32-bit channel data width (CHDW = 10
B
):
Selected pattern detection configuration see Table 11-6
on Page 11-44 .
Field Bits Type Description