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TC1784
Analog to Digital Converter (ADC)
User´s Manual
23-95
V1.1, 2011-05
ADC, V1.3
Result register features for each FIFO buffer:
•
Result register z (
FIFO buffer input
):
This result register can be enabled for data reduction. The wait-for-read mode is
supported to avoid data loss if the FIFO is full. Result event interrupt generation is not
supported. Must not be read at a read view modifying the valid bit.
•
Result register y (
intermediate buffer stage
):
This/these result register(s) must not be enabled neither for wait-for-read mode, nor
for data reduction. Result event interrupt generation is not supported. Must not be
read at a read view modifying the valid bit, nor be the target of a conversion result.
•
Result register x (
FIFO buffer output
):
This result register can be enabled for result event interrupt generation to inform the
CPU that new data can be read out from this register location. Data reduction and
wait-for-read are not supported and have to be disabled. Must not be the target of a
conversion result.
If enabled, a result interrupt is generated for each data word in the FIFO.
Summary of Contents for TC1784
Page 1: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 3: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 950: ...TC1784 Direct Memory Access Controller DMA User s Manual 11 132 V1 1 2011 05 DMA V3 03 ...
Page 1949: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 297 V1 1 2011 05 GPTA v5 V1 14 ...
Page 2350: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG Doc_Number ...