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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual
21-5
V1.1, 2011-05
GPTA
®
v5, V1.14
21.2.1
Functionality of GPTA0
The General Purpose Timer Array (GPTA0) provides a set of hardware cells required for
high-speed digital signal processing:
•
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
•
Phase Discrimination Logic cells (PDL) decode the direction information output by a
rotation tracking system.
•
Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
•
A Digital Phase Locked Loop cell (PLL) generates a programmable number of
GPTA
®
v5 unit ticks during an input signal’s period.
•
Global Timer cells (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
•
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
•
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
•
On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or
gating signals to integrated peripherals.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA
®
v5 cells.
Clock Generation Cells
•
Filter and Prescaler Cell (FPC)
– Six independent cells
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA
®
v5 unit clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA
®
v5 unit clock, prescaled GPTA
®
v5 unit clock, DCM clock, compensated or
uncompensated PLL clock.
–
f
GPTA
/2 maximum input signal frequency in Filter Modes
•
Phase Discriminator Logic (PDL)
– Two independent cells
– Two operating modes (2- and 3- sensor signals)
Summary of Contents for TC1784
Page 1: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 3: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 950: ...TC1784 Direct Memory Access Controller DMA User s Manual 11 132 V1 1 2011 05 DMA V3 03 ...
Page 1949: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 297 V1 1 2011 05 GPTA v5 V1 14 ...
Page 2350: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG Doc_Number ...