Infineon Technologies TC1784, User Manual

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TC1784
FlexRay™ Protocol Controller (E-Ray)
User´s Manual 20-230 V1.1, 2011-05
E-Ray, V3.13
When the Host writes the number of the target Message Buffer in the Message RAM to
IBRH in the Input Buffer Command Request register
IBCR , IBF Host and IBF Shadow
are swapped (see Figure 20-12 ).
Figure 20-12 Double Buffer Structure Input Buffer
In addition the bits in the Input Buffer Command Mask and Input Buffer Command
Request registers are also swapped to keep them attached to the respective IBF section
(see
Figure 20-13 ).
Figure 20-13 Swapping of IBCM and IBCR Bit
With this write operation the IBSYS bit in the Input Buffer Command Request register is
set to 1. The Message Handler then starts to transfer the contents of IBF Shadow to the
Message Buffer in the Message RAM selected by IBRS.
While the Message Handler transfers the data from IBF Shadow to the target Message
Buffer in the Message RAM, the Host may write the next message to IBF Host. After the
transfer between IBF Shadow and the Message RAM has completed, the IBSYS bit is
set back to 0 and the next transfer to the Message RAM may be started by the Host by
writing the respective target Message Buffer number to IBRH in the Input Buffer
Command Request register.
If a write access to IBRH occurs while IBSYS is 1, IBSYH is set to 1. After completion of
the ongoing data transfer from IBF Shadow to the Message RAM, IBF Host and IBF
Shadow are swapped, IBSYH is reset to 0, IBSYS remains set to 1, and the next transfer
Host
Message
RAM
E-Ray
IBF
IBF
Sha
dow
IBF = Input Buffer
Host
IBCM IBCR
swap swap
1 0 2
17 16 18
1 0 2 4 3 5
20 19 21 17 16 18 31
15 6
22