Infineon Technologies TC1784, User Manual

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TC1784
LMB External Bus Unit
User´s Manual 12-4 V1.1, 2011-05
EBUT13L-A, V1.16
12.3.4 Read/Write Control Lines, RD, RD/WR
Two lines are provided to trigger the read (RD) and write (RD/WR) operations of external
devices. While some read/write devices require both signals, there are devices with only
one control input. The RD/WR line is then used for these devices. This line will go to an
active-low level on a write, and will stay inactive high on a read. The external device
should only evaluate this signal in conjunction with an active chip select. Thus, an active
chip select in combination with a high level on the RD/WR line indicates a read access
to this device.
12.3.5 Address Valid, ADV
The address valid signal, ADV, validates the address lines A[20:16] and AD[15:0]. It can
be used to latch these addresses externally.
12.3.6 Byte Controls, BC[1:0]
The byte control signals BC[1:0] select the appropriate byte lanes of the data bus for both
read and write accesses.
Table 12-2 shows the activation on access to a 16-bit or 8-bit
external device. Please note that this scheme supports little-endian devices.
Signals BCx can be programmed for different timing. The available modes cover a wide
range of external devices, such as RAM with separate byte write-enable signals, and
RAM with separate byte chip select signals. This allows external devices to connect
without any external “glue” logic.
Table 12-2 Byte Control Pin Usage
Width of External Device BC1 BC0
16-bit device
with byte write capability D[15:8] D[7:0]
8-bit device inactive
(high) D[7:0]
Table 12-3 Byte Control Signal Timing Options
Mode EBU_BUSCONx.
BCGEN Description
Chip Select Mode 00
B
BCx signals have the same timing as the
generated chip select CS.