Infineon Technologies TC1784, User Manual

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TC1784
Peripheral Control Processor (PCP)
User´s Manual 10-72 V1.1, 2011-05
PCP, V2.09
PCP_ICR
PCP Interrupt Control Register
(20
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RES
P
ONE
CYC PARBCYC PIPN
r rw rw rh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES IE CPPN
r rh rh
Field Bits Type Description
RES [31:27] r Reserved
Read as 0; should be written with 0.
PONECYC 26 rw Clocks per Arbitration Cycle Control
This bit determines the number of clocks per arbitration
cycle.
0
B
Two clocks per arbitration cycle (default)
1
B
One clock per arbitration cycle
PARBCYC [25:24] rw Number of Arbitration Cycles Control
This bit field controls the number of arbitration cycles
used to determine the request with the highest priority.
It follows the same coding scheme as described for the
CPU interrupt arbitration.
00
B
Four arbitration cycles (default)
01
B
Three arbitration cycles
10
B
Two arbitration cycles
11
B
One arbitration cycle
PIPN [23:16] rh Pending Interrupt Priority Number
This read-only field is updated by the PICU at the end
of each arbitration process, and indicates the priority
number of a pending request. PIPN is set to 00
H
when
no request is pending and at the beginning of a new
arbitration process.
RES [15:9] r Reserved
Read as 0; should be written with 0.