Infineon Technologies TC1784, User Manual

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TC1784
Micro Link Interface (MLI)
User´s Manual 22-143 V1.1, 2011-05
MLI, V2.0
22.5.10 Module Clock Generation
The module clock generation configuration for the two MLI modules is shown in
Figure 22-59 .
Figure 22-59 Clock Configuration of the MLI Modules
The DMA controller and the two MLI modules (MLI0 and MLI1) are supplied from a
common module clock
f
DMA
, that has the frequency of the system clock
f
SYS
(=
f
FPI
) and
is controlled via the DMA_CLC clock control register. The MLI modules do not have its
own clock control registers. Its module clocks
f
MLI0
and
f
MLI1
are derived from
f
DMA
by two
separate fractional divider registers, MLI0_FDR and MLI1_FDR (description see
Page 22-81 ).
Output signal CAN_INT_O15 of the MultiCAN module can be used for external clock
enable control of the fractional divider.
•
f
DMA
This is the module clock used inside the MLI kernels for control purposes such as for
clocking of control logic and register operations. The clock control register DMA_CLC
makes it possible to enable/disable
f
DMA
under certain conditions. DMA_CLC is
described in the DMA chapter of this document.
•
f
MLI0
and
f
MLI1
This clock is the module clock used in the MLI kernels as base for the shift clock and
therefore determines the baud rate of the synchronous serial data transmission. The
fractional divider registers MLI0_FDR and MLI1_FDR control the frequencies of
f
MLI0
and
f
MLI1
. This configuration makes it possible to enable/disable the module clocks
f
MLI0
and
f
MLI1
independently of
f
DMA
.
DMA Clock
Control
(DMA_CLC)
MCA05909_mod
f
MLI0
f
DMA
(=
f
CLC
)
MLI0
Module
Kernel
MLI1
Module
Kernel
MLI0_FDR MLI1_FDR
f
MLI1
f
SYS
=
f
FPI
ECEN
MultiCAN
Module
ECEN