Infineon Technologies TC1784, User Manual

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TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-43 V1.1, 2011-05
Buses, V1.9
TAG [27:24] rwh FPI Bus Master Tag Number Signals
This bit field indicates the FPI Bus master TAG
number (definitions see
Table 4-15 ).
OPC [31:28] rwh FPI Bus Operation Code Signals
The FPI Bus operation codes are defined in
Table 4-11 .
1) In the TC1784, aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave
generates an error acknowledge.
Table 4-14 FPI Bus Read/Write Error Indication
RD WR FPI Bus Cycle
0 0 FPI Bus error occurred at the read transfer of a read-modify-write
transfer.
0 1 FPI Bus error occurred at a read cycle of a single transfer.
1 0 FPI Bus error occurred at a write cycle of a single transfer or at the
write cycle of a read-modify-write transfer.
1 1 Does not occur.
SBCU_EADD
SBCU Error Address Capture Register (024
H
) Reset Value: 0000 0000
H
31 0
FPIADR
rwh
Field Bits Type Description
FPIADR [31:0] rwh Captured FPI Bus Address
This bit field holds the 32-bit FPI Bus address that has
been captured at an FPI Bus error. Note that if multiple
bus errors occurred, only the address of the first bus
error is captured.
Field Bits Type Description