Infineon Technologies TC1784, User Manual

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TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-7 V1.1, 2011-05
Buses, V1.9
4.3.2.1 LMB Bus Default Master
When no LMB master is requesting the LMB, it is granted to the LMB default master. This
means, if the default master needs the LMB in the next cycle, it can enter the address
cycle without running through a request/grant cycle.
4.3.3 LMB Bus Error Handling
When an error occurs on LMB, the LMB controller captures and stores data about the
erroneous condition and generates a service request if enabled to do so. The error
conditions that force an error capture event are:
•
Un-implemented Address: No LMB slave responds to an address target
• Error Acknowledge: An LMB slave responds with an error to a transaction
When a transaction causes an error, the address and data phase signals of the
transaction causing the error are captured and stored in the following registers:
•
The LMB Error Address Register (LEADDR) stores the LMB address that has been
captured during the last erroneous LMB transaction.
• The LMB Error Data Registers (LEDATL/LEDATH) stores the LMB data bus
information that has been captured during the last erroneous LMB transaction.
• The LMB Error Attribute Register (LEATT) stores status information of the bus error
event.
If more than one LMB transaction generates a bus error, only the first bus error is
captured. After a bus error was captured, the capture mechanism must be released
again by software.
If a write transaction from the PCP or DMA on the SPB that is forwarded by the LFI
module to the LMB causes a bus error on the LMB Bus, the originating masters are not
informed about this bus error because these write transactions are finished on SPB
when the error happens on LMB. With each bus error-capture event, a service request
is generated and interrupt can be generated if enabled and configured in the
corresponding service request register.