Infineon Technologies TC1784, User Manual

Page: 591 / 2350

TC1784
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
User´s Manual 9-15 V1.1, 2011-05
Ports, V1.1
Pad Driver Mode Register
This is the general description of the PDR register. Each port contains its own specific
PDR register, described additionally at each port, that can contain between one and
eight PDx fields. Each field controlls a number of pins, normally four, but in general
between one and sixteen.
Px_PDR
Port x Pad Driver Mode Register(F000 0C40
H
+x*100
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 PD7 0 PD6 0 PD5 0 PD4
r rw r rw r rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 PD3 0 PD2 0 PD1 0 PD0
r rw r rw r rw r rw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for Px.[3:0]
(Class A1 or A2 pads; coding see Page 9-14 )
PD1 [6:4] rw Pad Driver Mode for Px.[7:4]
(Class A1 or A2 pads; coding see Page 9-14 )
PD2 [10:8] rw Pad Driver Mode for Px.[11:8]
(Class A1 or A2 pads; coding see Page 9-14 )
PD3 [14:12] rw Pad Driver Mode for Px.[15:12]
(Class A1 or A2 pads; coding see Page 9-14 )
PD4 [2:0] rw Pad Driver Mode for Px.[19:16]
PD5 [6:4] rw Pad Driver Mode for Px.[23:20]
PD6 [10:8] rw Pad Driver Mode for Px.[27:24]
PD7 [14:12] rw Pad Driver Mode for Px.[31:28]
0 3, 7, 11,
15, 19,
23, 27, 31 r Reserved
Read as 0; should be written with 0.