Infineon Technologies TC1784, User Manual

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TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-6 V1.1, 2011-05
Buses, V1.9
4.3 Local Memory Bus Controller Unit
The LMB in the TC1784 has an LMB Bus Control Unit (LBCU).
4.3.1 Basic Operation
The LBCU handles the cycle sequences of the transfers which have been requested by
the LMB master devices. The LBCU is also able to detect bus protocol violations and
addressing of un-implemented addresses. In case of a bus error, the LBCU captures all
relevant data like bus address, bus data and bus status information in register where the
information can be analyzed by software.
4.3.2 LMB Bus Arbitration
All LMB master devices requesting the LMB will participate in an arbitration round.
Arbitration rounds are performed in each cycle that precedes a possible address cycle.
Each LMB master device has a fixed priority as shown in
Table 4-2 .
For all the masters requesting the LMB during any one cycle, the granted master is the
one with the highest priority.
Table 4-2 Priority of Master LMB Agents
Priority LMB Master Comment
Highest
Lowest
DMA, high priority DMA Requests from modules:
- Cerberus high priority
1)
- DMA channels with high priority
2)
1) Priority of Cerberus transaction at the On Chip Busses is defined by the register bit IOCONF.FPI_PRIO. The
register is defined in the OCDS chapter.
2) Priority of a DMA channel is defined by the corresponding CHCRmn.DMAPRIO bits. The registers are defined
in the DMA chapter.
LFI Bridge –
DMA, medium priority DMA Requests from modules:
- DMA Channel medium priority
2)
Data Memory Interface (DMI) Default Master
Program Memory Interface (PMI) –
DMA, low priority DMA requests from modules:
- Cerberus low priority
1)
- DMA channels low priority
2)
- MLI