Infineon Technologies TC1784, User Manual

Page: 164 / 2350

TC1784
CPU Subsystem
User´s Manual 2-74 V1.1, 2011-05
CPU, V3.03
• If the fetch request is made within a scratchpad RAM line, the 64-bit instruction
packet is returned to the CPU in a single cycle.
• If the fetch request is made to the end of a scratchpad RAM line, such that 64-bits
would span two scratchpad RAM lines, then only the instruction half-words up to the
end of the scratchpad RAM line are returned to the CPU.
Note that the CPU Fetch Unit can only read from the scratchpad RAM and can never
write to it.
The scratchpad RAM may also be accessed from the LMB Slave interface by another
bus master, such as the Data Memory Interface (DMI). The scratchpad RAM may be
both read and written from the LMB. In the TC1784, the PMI LMB Slave interface
supports all LMB transaction types.
2.14.4 Instruction Cache
The TC1784 contains up to 16 Kbyte of Instruction Cache (ICACHE). The ICACHE is a
two-way set-associative cache with a Least-Recently-Used (LRU) replacement
algorithm, and is organized as 512 cache lines, with 256-bits per line. Each ICACHE line
has a single associated valid bit.
CPU program fetch accesses which target a cacheable memory segment (and where the
ICACHE is not bypassed) target the ICACHE. If the requested address and its
associated instruction are found in the cache (Cache Hit), the instruction is passed to the
CPU Fetch Unit without incurring any wait states. If the address is not found in the cache
(Cache Miss), the PMI cache controller issues a cache refill sequence and wait states
are incurred whilst the cache line is refilled. The CPU fetch interface will generate
unaligned accesses (16-bit aligned), which will normally result in 64-bits of instruction
being returned to the CPU. If the fetch request is made within a ICACHE line, no matter
the alignment, and a cache hit occurs, then the 64-bit instruction packet is returned to
the CPU. If the fetch request is made to the end of a ICACHE line, such that 64-bits
would span two ICACHE lines, then only the instruction half-words up to the end of the
ICACHE line are returned to the CPU.
Instruction Cache Refill Sequence
Instruction Cache refills are performed using a critical double-word first strategy with
cache line wrapping such that the refill size is always 4 double-words. ICACHE refills are
always performed in 64-bit quantities. A refill sequence will always affect only one cache
line. There is no prefetching of the next cache line.
ICACHE refills are therefore implemented using an LMB Burst Transfer 4 (BTR4)
transfers. The Instruction Cache supports instruction streaming, meaning that it can
deliver available instruction half-words to the CPU Fetch Unit whilst the refill operation is
ongoing.