Infineon Technologies TC1784, User Manual

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TC1784
Peripheral Control Processor (PCP)
User´s Manual 10-125 V1.1, 2011-05
PCP, V2.09
10.18.35 ST, Store
This section describes the ST instructions of the PCP.
ST.F Syntax ST.F Rb, [Ra], Size
Description Store the contents of register Rb to the address location
specified by the contents of register Ra. When the Size is byte
or half-word, the data is stored with the internal LSB (bit 0)
properly aligned to the correct FPI Bus byte or half-word lane.
Operation FPI[R[a]] = R[b]
Flags None
ST.IF Syntax ST.IF [Ra], #offset5, Size
Description Store the contents of R0 to the address location specified by
the addition of the contents of register Ra and the value
specified by imm5. When the Size is byte or half-word, the
data is stored with the internal LSB (bit 0) properly aligned to
the correct FPI Bus byte or half-word lane.
Operation FPI[R[a] + zero_ext(imm5)] = R[0]
Flags None
ST.P Syntax ST.P Rb, [Ra], cc_A
Description If condition CONDCA is true, then store the contents of Rb to
the PRAM address location specified by the addition of the
contents of the PRAM Data Pointer, shifted left by six bits, and
the zero-extended 6-bit value Ra[5:0]. If condition CONDCA
is false, no operation is performed.
Operation if (CONDCA = True) then PRAM[(DPTR<<6) +
zero_ext(R[a][5:0])] = R[b] else NOP
Flags None
ST.PI Syntax ST.PI Rb, [#offset6]
Description Store the contents of register Rb to the PRAM location
specified by the addition of the contents of the PRAM Data
Pointer, shifted left by six bits, and the zero-extended 6-bit
value offset6.
Operation PRAM[(DPTR<<6) + zero_ext(offset6)] = R[b]
Flags None