Infineon Technologies TC1784, User Manual

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TC1784
CPU Subsystem
User´s Manual 2-88 V1.1, 2011-05
CPU, V3.03
2.15.7 DMI Registers
Two Control Registers and two Trap Flag registers are implemented in the DMI. These
registers and their bits are described in this section.
Figure 15 DMI Registers
Access to DMI control registers must only be made with double-word aligned word
accesses. An access not conforming to this rule, or an access that does not follow the
specified privilege mode (Supervisor mode, Endinit-protection), or a write access to a
read-only register, will lead to a bus error if the access was from the LMB Bus, or to a
trap, flagged in DMI_STR/DMI_ATR register in case of a CPU load/store access.
Table 20 DMI Registers
Short Name Description Offset
Address Access Mode Reset
Read Write
DMI_ID DMI Identification Register FC08
H
U, SV,
32 SV,
32 Class 3 Reset
0008 C0XX
H
DMI_CON DMI Control Register FC10
H
U, SV,
32 SV, E,
32 Class 3 Reset
0800 0802
H
DMI_STR DMI Synchronous Trap Flag
Register FC18
H
U, SV,
32
1)
1) Reading these registers in supervisor mode returns the contents and then clears the register. Reading it in
user mode only returns the contents of the register; it is not cleared. No error will be reported in this case.
SV,
32 Class 3 Reset
0000 0000
H
DMI_ATR DMI Asynchronous Trap
Flag Register FC20
H
U, SV,
32
1)
SV,
32 Class 3 Reset
0000 0000
H
DMI_CON
MCA06081
DMI_ID
DMI_STR
Control Registers Trap Flag Registers
DMI_ATR