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TC1784
Fast Analog to Digital Converter (FADC)
User´s Manual
24-62
V1.1, 2011-05
FADC, V2.21
24.3.4.4 Final Result Registers
The Final Result Registers FRRn hold the final results of filter block n. The data width
being different for the filter block 0 and 2 from the one from data blocks 1 and 3, two
different register layouts are necessary.
FRR0
Filter 0 Final Result Register
(074
H
)
Reset Value: 0000 0000
H
FRR2
Filter 2 Final Result Register
(0B4
H
)
Reset Value: 0000 0000
H
31
15 14
0
0
FR
r
rh
Field
Bits
Type Description
FR
[14:0]
rh
Final Result
This bit field contains the right-aligned final result.
FR is cleared when writing GCR.RSTFn = 1.
0
[31:15]
rh
Reserved
Read as 0. Should be written with 0.
FRR1
Filter 1 Final Result Register
(094
H
)
Reset Value: 0000 0000
H
FRR3
Filter 3 Final Result Register
(0D4
H
)
Reset Value: 0000 0000
H
31
20 19
0
0
FR
r
rh
Field
Bits
Type Description
FR
[19:0]
rh
Final Result
This bit field contains the right-aligned final result.
FR is cleared when writing GCR.RSTFn = 1.
0
[31:20]
rh
Reserved
Read as 0. Should be written with 0.
Summary of Contents for TC1784
Page 1: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 3: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Page 950: ...TC1784 Direct Memory Access Controller DMA User s Manual 11 132 V1 1 2011 05 DMA V3 03 ...
Page 1949: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 297 V1 1 2011 05 GPTA v5 V1 14 ...
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