Infineon Technologies TC1784, User Manual

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TC1784
Controller Area Network Controller (MultiCAN)
User´s Manual 19-22 V1.1, 2011-05
MLI, V2.0
Calculation of the bit time:
To compensate phase shifts between clocks of different CAN controllers, the CAN
controller must synchronize on any edge from the recessive to the dominant bus level.
If the hard synchronization is enabled (at the start of frame), the bit time is restarted at
the synchronization segment. Otherwise, the re-synchronization jump width T
SJW
defines
the maximum number of time quanta, a bit time may be shortened or lengthened by one
re-synchronization. The value of SJW is defined by bit field NBTRx.SJW.
The maximum relative tolerance for
f
CAN
depends on the Phase Buffer Segments and
the re-synchronization jump width.
A valid CAN bit timing must be written to the CAN Node Bit Timing Register NBTR before
resetting the INIT bit in the Node Control Register, i.e. before enabling the operation of
the CAN node.
The Node Bit Timing Register may be written only if bit CCE (Configuration Change
Enable) is set in the corresponding Node Control Register.
19.3.5.2 Bitstream Processor
Based on the message objects in the message buffer, the Bitstream Processor
generates the remote and Data Frames to be transmitted via the CAN bus. It controls the
CRC generator and adds the checksum information to the new remote or Data Frame.
After including the SOF bit and the EOF field, the Bitstream Processor starts the CAN
t
q
= (BRP + 1) /
f
CAN
if DIV8 = 0
= 8
×
(BRP + 1) /
f
CAN
if DIV8 = 1
T
Sync
= 1
× t
q
T
Seg1
= (TSEG1 + 1)
× t
q
(min. 3
t
q
)
T
Seg2
= (TSEG2 + 1)
×
t
q
(min. 2
t
q
)
bit time = T
Sync
+ T
Seg1
+ T
Seg2
(min. 8
t
q
)
T
SJW
= (SJW + 1)
×
t
q
T
Seg1
≥
T
SJW
+ T
prop
T
Seg2
≥
T
SJW
d
f
CAN
≤
min (T
b1
, T
b2
) / 2
×
(13
×
bit time - T
b2
) AND
d
f
CAN
≤
T
SJW
/ 20
×
bit time