Infineon Technologies TC1784, User Manual

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TC1784
FlexRay™ Protocol Controller (E-Ray)
User´s Manual 20-226 V1.1, 2011-05
E-Ray, V3.13
20.6.9.2 NULL Frame reception
The Payload Segment of a received NULL Frame is not copied into the matching receive
buffer. If a NULL Frame has been received, the Header Section of the matching
Message Buffer is updated from the received NULL Frame. The NULL Frame indication
bit in the Header Section 3 of the respective Message Buffer is reset (NFI = 0) and the
respective MBC flag in the Message Buffer Status Changed 1,2,3,4 registers is set.
In case that bit ND and / or MBC were already set before this event because the Host
did not read the last received message, bit MLST in the Message Buffer Status register
of the respective Message Buffer is also set.
20.6.10 FIFO Function
A group of the Message Buffers can be configured as a cyclic First-In-First-Out (FIFO).
The group of Message Buffers belonging to the FIFO is contiguous in the register map
starting with the Message Buffer referenced by FFB and ending with the Message Buffer
referenced by LCB in the Message RAM Configuration register. Up to 128 Message
Buffers can be assigned to the FIFO.
20.6.10.1 Description
Every valid incoming message not matching with any dedicated receive buffer but
passing the programmable FIFO filter is stored into the FIFO. In this case Frame ID,
payload length, receive cycle count, and the status bits of the addressed FIFO Message
Buffer are overwritten with Frame ID, payload length, receive cycle count, and the status
from the received message and can be read by the Host for message identification. Bit
RFNE in the Status Service Request Register shows that the FIFO is not empty, bit RFF
in the Status Service Request Register is set when the last available Message Buffer
belonging to the FIFO is written, bit RFO in the Error Service Request Register shows
that a FIFO overrun has been detected. If enabled, service requests are generated.
There are two index registers associated with the FIFO. The PUT Index Register (PIDX)
is an index to the next available location in the FIFO. When a new message has been
received it is written into the Message Buffer addressed by the PIDX register. The PIDX
register is then incremented and addresses the next available Message Buffer. If the
PIDX register is incremented past the highest numbered Message Buffer of the FIFO,
the PIDX register is loaded with the number of the first (lowest numbered) Message
Buffer in the FIFO chain. The GET Index Register (GIDX) is used to address the next
Message Buffer of the FIFO to be read. The GIDX register is incremented after transfer
of the contents of a Message Buffer belonging to the FIFO to the Output Buffer. The PUT
Index Register and the GET Index Register are not accessible by the Host.
The FIFO is completely filled when the PUT index (PIDX) reaches the value of the GET
index (GIDX). When the next message is written to the FIFO before the oldest message
has been read, both PUT index and GET index are incremented and the new message