Infineon Technologies TC1784, User Manual

Page: 419 / 2350

TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-51 V1.1, 2011-05
Buses, V1.9
Field Bits Type Description
OPC [3:0] rw Opcode for Signal Status Debug Trigger
This bit field determines the type (opcode) of an
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS0 = 1).
0000
B
Trigger on single byte transfer selected
0001
B
Trigger on single half-word transfer
selected
0010
B
Trigger on single word transfer selected
0100
B
Trigger on 2-word block transfer selected
0101
B
Trigger on 4-word block transfer selected
0110
B
Trigger on 8-word block transfer selected
1111
B
Trigger on no operation selected
Other bit combinations are reserved.
SVM 4 rw SVM Signal for Status Debug Trigger
This bit determines the mode of an FPI Bus
transaction for which a signal status debug trigger
event is generated (if enabled by
DBCNTL.ONBOS1 = 1).
0
B
Trigger on User Mode selected
1
B
Trigger on Supervisor Mode selected
WR 8 rw Write Signal for Status Debug Trigger
This bit determines the state of the WR signal of an
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS2 = 1).
0
B
Trigger on a single write transfer or write cycle
of an atomic transfer selected
1
B
No operation or read transaction selected
RD 12 rw Write Signal for Status Debug Trigger
This bit determines the state of the RD signal of an
FPI Bus transaction for which a signal status debug
trigger event is generated (if enabled by
DBCNTL.ONBOS3 = 1).
0
B
Trigger on a single read transfer or read cycle
of an atomic transfer selected
1
B
No operation or write transfer selected