Infineon Technologies TC1784, User Manual

Page: 2124 / 2350

TC1784
Analog to Digital Converter (ADC)
User´s Manual 23-18 V1.1, 2011-05
ADC, V1.3
CRPR1 Conversion Request 1
Pending Register 094
H
U, SV U, SV Class 3 Page 23-56
CRMR1 Conversion Request 1
Mode Register 098
H
U, SV U, SV Class 3 Page 23-57
Request Source 2 Registers (available in the address range of each kernel)
QMR2 Queue 2 Mode Register 0A0
H
U, SV U, SV Class 3 Page 23-65
QSR2 Queue 2 Status Register 0A4
H
U, SV U, SV Class 3 Page 23-68
Q0R2 Queue 2 Register 0 0A8
H
U, SV U, SV Class 3 Page 23-70
QBUR2 Queue 2 Backup
Register 0AC
H
U, SV U, SV Class 3 Page 23-72
QINR2 Queue 2 Input Register 0AC
H
U, SV U, SV Class 3 Page 23-74
Request Source 3 Registers (available in the address range of each kernel)
CRCR3 Conversion Request 3
Control Register 0B0
H
U, SV U, SV Class 3 Page 23-54
CRPR3 Conversion Request 3
Pending Register 0B4
H
U, SV U, SV Class 3 Page 23-56
CRMR3 Conversion Request 3
Mode Register 0B8
H
U, SV U, SV Class 3 Page 23-57
Request Source 4 Registers (available in the address range of each kernel)
QMR4 Queue 4 Mode Register 0C0
H
U, SV U, SV Class 3 Page 23-65
QSR4 Queue 4 Status Register 0C4
H
U, SV U, SV Class 3 Page 23-68
Q0R4 Queue 4 Register 0 0C8
H
U, SV U, SV Class 3 Page 23-70
Table 23-2 Register Overview of ADC (cont’d)
Short
Name Description Offset
Addr.
1)
Access Mode Reset Description
See
Read Write