Infineon Technologies TC1784, User Manual

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TC1784
CPU Subsystem
User´s Manual 2-59 V1.1, 2011-05
CPU, V3.03
2.13 CPU Instruction Timing
This section gives information on CPU instruction timing by execution unit. The Integer
Pipeline and Load/Store Pipeline are always present, and the Floating Point Unit (FPU)
is optional. The Load/Store unit implements the optional TLB instructions.
Definition of Terms:
•
Repeat Rate
Assuming the same instruction is being issued sequentially, repeat is the minimum
number of clock cycles between two consecutive issues. There may be additional delays
described elsewhere due to internal pipeline effects when issuing a different subsequent
instruction.
• Result Latency
The number of clock cycles from the cycle when the instruction is issued to the cycle
when the result value is available to be used as an operand to a subsequent instruction
or written into a GPR. Result latency is not meaningful for instructions that do not write
a value into a GPR.
• Address Latency
The number of clocks cycles from the cycle when the instruction is issued to the cycle
when the addressing mode updated value is available as an operand to a subsequent
instruction or written into an Address Register.
• Flow Latency
The number of clock cycles from the cycle when the instruction is issued to the cycle
when the next instruction (located at the target location or the next sequential instruction
if the control change is conditional) is issued.