PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MEMORY SUBSYSTEM
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Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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MEMORY SUBSYSTEM
OVERVIEW
The S3C6400X Memory Subsystem includes seven memory controllers, one SROM controller, two OneNAND
controllers, one NAND Flash controller, one CF controller, and two DRAM controllers. Static memory controllers
and 16-bit DRAM controller share memory port 0 by using EBI.
FEATURE
Memory Subsystem features of S3C6400X are as follows
Memory Subsystem has one 64-bit AXI slave interface, one 32-bit AXI slave interface, one 32-bit AHB
Master interface, two 32-bit AHB slave interfaces, one for data transfer and the other for SFR setting, and
one APB interface for DMC SFR setting.
Memory Subsystem gets booting method and CS selection information from the System Controller.
Internal AHB data bus connects 32-bit AHB slave data bus with SROMC, two OneNANDC and NFCON.
Internal AHB SFR bus connects 32-bit AHB slave SFR bus with SROMC, two OneNANDC, CFCON and
NFCON.
Internal AHB master bus is used for CFCON.
DMC0 uses 32-bit AXI slave interface and APB interface.
DMC1 uses 64-bit AXI slave interface and APB interface.
Memory port 0 is shared by using EBI (External Bus Interface).
Memory port 1 is used only by DMC1.
Option for using either NAND Flash or OneNAND is supported.
Independent port for CFCON is supported.
When CFCON uses EBI, XhiIRQn and XirSBDW pins are used as output enable (MP0_nDOEN[0]) for level
shifter on data path.
Xm0CSn[1:0] in memory port 0 are dedicated for SROMC.
Xm0CSn[7:6] in memory port 0 are dedicated for DMC0.