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PRELIMINARY 

S3C6400X RISC MICROPROCESSOR

 

 

 USB2.0 HS OTG 

 

26-9 

Preliminary product information describe products that are in development,

 

for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.

HCINT4 0x588 

R/W 

Host 

Channel 

4 Interrupt Register 

0x0000_0000 

HCINTMSK4 0x58C 

R/W 

Host 

Channel 

4 Interrupt Mask Register 

0x0000_0000 

HCTSIZ4 

0x580 

R/W 

Host Channel 4 Transfer Size Register 

0x0000_0000 

HCDMA4 

0x584 

R/W 

Host Channel 4 DMA Address Register 

0x0000_0000 

HCCHAR5 

0x5A0 

R/W 

Host Channel 5 Characteristics Register 

0x0000_0000 

HCSPLT5 0x5A4 

R/W 

Host 

Channel 

5 Spilt Control Register 

0x0000_0000 

HCINT5 0x5A8 

R/W 

Host 

Channel 

5 Interrupt Register 

0x0000_0000 

HCINTMSK5 0x5AC 

R/W 

Host 

Channel 

5 Interrupt Mask Register 

0x0000_0000 

HCTSIZ5 0x5B0 

R/W 

Host 

Channel 

5 Transfer Size Register 

0x0000_0000 

HCDMA5 0x5B4 

R/W 

Host 

Channel 

5 DMA Address Register 

0x0000_0000 

HCCHAR6 

0x5C0 

R/W 

Host Channel 6 Characteristics Register 

0x0000_0000 

HCSPLT6 0x5C4 

R/W 

Host 

Channel 

6 Spilt Control Register 

0x0000_0000 

HCINT6 0x5C8 

R/W 

Host 

Channel 

6 Interrupt Register 

0x0000_0000 

HCINTMSK6 0x5CC 

R/W 

Host 

Channel 

6 Interrupt Mask Register 

0x0000_0000 

HCTSIZ6 0x5D0 

R/W 

Host 

Channel 

6 Transfer Size Register 

0x0000_0000 

HCDMA6 0x5D4 

R/W 

Host 

Channel 

6 DMA Address Register 

0x0000_0000 

HCCHAR7 

0x5E0 

R/W 

Host Channel 7 Characteristics Register 

0x0000_0000 

HCSPLT7 0x5E4 

R/W 

Host 

Channel 

7 Spilt Control Register 

0x0000_0000 

HCINT7 0x5E8 

R/W 

Host 

Channel 

7 Interrupt Register 

0x0000_0000 

HCINTMSK7 0x5EC 

R/W 

Host 

Channel 

7 Interrupt Mask Register 

0x0000_0000 

HCTSIZ7 0x5F0 

R/W 

Host 

Channel 

7 Transfer Size Register 

0x0000_0000 

HCDMA7 0x5F4 

R/W 

Host 

Channel 

7 DMA Address Register 

0x0000_0000 

HCCHAR8 

0x600 

R/W 

Host Channel 8 Characteristics Register 

0x0000_0000 

HCSPLT8 

0x604 

R/W 

Host Channel 8 Spilt Control Register 

0x0000_0000 

HCINT8 0x608 

R/W 

Host 

Channel 

8 Interrupt Register 

0x0000_0000 

HCINTMSK8 0x60C 

R/W 

Host 

Channel 

8 Interrupt Mask Register 

0x0000_0000 

HCTSIZ8 

0x610 

R/W 

Host Channel 8 Transfer Size Register 

0x0000_0000 

HCDMA8 

0x614 

R/W 

Host Channel 8 DMA Address Register 

0x0000_0000 

HCCHAR9 

0x620 

R/W 

Host Channel 9 Characteristics Register 

0x0000_0000 

HCSPLT9 

0x624 

R/W 

Host Channel 9 Spilt Control Register 

0x0000_0000 

HCINT9 0x628 

R/W 

Host 

Channel 

9 Interrupt Register 

0x0000_0000 

HCINTMSK9 0x62C 

R/W 

Host 

Channel 

9 Interrupt Mask Register 

0x0000_0000 

HCTSIZ9 

0x630 

R/W 

Host Channel 9 Transfer Size Register 

0x0000_0000 

HCDMA9 

0x634 

R/W 

Host Channel 9 DMA Address Register 

0x0000_0000 

HCCHAR10 

0x640 

R/W 

Host Channel 10 Characteristics Register 

0x0000_0000 

HCSPLT10 

0x644 

R/W 

Host Channel 10 Spilt Control Register 

0x0000_0000 

HCINT10 0x648 

R/W 

Host 

Channel 

10 Interrupt Register 

0x0000_0000 

HCINTMSK10 0x64C R/W 

Host 

Channel 

10 Interrupt Mask Register 

0x0000_0000 

Summary of Contents for S3C6400X

Page 1: ...S3C6400X USER S MANUAL Preliminary_Revision 0 2 Oct 2007 ...

Page 2: ...tions intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harml...

Page 3: ... and associated errata are not yet available Specifications and information herein are subject to change without notice DOCUMENT REVISION HISTORY The following table shows the revision history for this document Version Date Revision Descriptions 0 1 June 05 2007 Initial Release 0 2 Oct 12 2007 Chapter 1 3 4 6 7 8 9 10 11 14 15 16 17 22 26 31 32 33 36 38 41 Modified ...

Page 4: ...he Flash ROM DRAM port supports NOR Flash NAND Flash OneNAND CF ROM type external memory and mobile DDR DDR mobile SDRAM and SDRAM To reduce total system cost and enhance overall functionality the S3C6400 includes many hardware peripherals such as a Camera Interface TFT 24 bit true color LCD controller System Manager power management etc 4 channel UART 32 channel DMA 4 channel Timers General Purpo...

Page 5: ...e in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice FEATURES This section summarizes the features of the S3C6400 Figure 1 1 is an overall block diagram of the S3C6400 Figure 1 1 S3C6400 block diagram ...

Page 6: ...oding of VC1 video up to 30fps SD z 2D Graphics Acceleration with BitBlit and Rotation z AC 97 audio codec interface and PCM serial audio interface z 1 2 4bpp Palletized or 16bpp 24bpp Non Palletized Color TFT support up to 1024x1024 z I2S and I2C interface support z Dedicated IrDA port for FIR MIR and SIR z Flexibly configurable GPIOs z port USB 2 0 OTG supporting high speed 480Mbps on chip trans...

Page 7: ...res of ARM1176JZF S processor include z TrustZone security extensions z High speed Advanced Microprocessor Bus Architecture AMBA Advanced Extensible Interface AXI level two interfaces supporting prioritized multiprocessor implementations z Integer unit with integral EmbeddedICE RT logic z Eight stage pipeline z Branch prediction with return stack z Low interrupt latency configuration z External co...

Page 8: ...6 data bus o Address range support max 26 bits 128MB o Support byte and half word access OneNAND Flash interface o x16 data bus NAND Flash Boot Loader o System can be booted from NAND when system initialization begins o Reset of memory area is used for storing user data o Supports both SLC and MLC NAND Flash memory CF interface o Compatible with CF and CompactFlash Spec Rev 3 0 SDRAM Interface o x...

Page 9: ...and 14x14mm Package o OneDRAM 512Mb NAND Flash 2Gb and mobile DDR 512Mb on one package 491 FBGA and 14x14mm Package Memory MCP can be directly connected to the application processor in the same manner as connecting discrete memory components 16 bit OneNAND Flash Interface 32 bit Mobile DDR Interface 1 1 4 Multimedia Acceleration The S3C6400 microprocessor provides the following Multimedia Accelera...

Page 10: ... Error resilience tools o MPEG 4 resync Marker and data partitioning with RVLC o MPEG 4 AVC FMO and ASO o Bit rate control CBR and VBR Decoding tools o Support all features of the standards Pre post rotation mirroring o 8 mirroring rotation modes Performance o Full duplex VGA 30fps encoding decoding o Half duplex 720x480 30fps 720x576 25fps encoding decoding 1 1 4 3 JPEG Codec Compression decompre...

Page 11: ...n or zooming in out Color space conversion from YCbCr to RGB and from RGB to YCbCr Dedicated local interface for display Dedicated scaler for TV Encoder 1 1 7 3 TV NTSC PAL Video Encoder with Image Enhancer Support NTSC M PAL B D G H I compliant video format Macrovision for anti taping Version 7 1 L1 Support YCbCr 4 2 0 4 2 2 16 18 24bit RGB source format Built in the MIE Mobile Image Enhancer Eng...

Page 12: ... to the USB 2 0 protocol Rev2 0 Configures as OTG device only USB 1 1 device OTG mini host only or USB 1 1 mini host Supports high speed 480Mbps full speed 12Mbps and low speed 1 5Mbps 1 1 9 2 USB Host 2 port USB Host Complies with OHCI Rev 1 0 Compatible with the USB Specification version 1 1 Supports full speed up to 12Mbps 1 1 10 IrDA v1 1 The S3C6400 microprocessor provides the following IrDA ...

Page 13: ...Full Duplex 1 1 11 4 MIPI HSI A uni direction high speed serial interface Supports Tx and Rx 128 Byte 32 bit x 32 Tx FIFO 256 Byte 32 bit x 64 Rx FIFO TX PCLK bps RX up to 100Mbps 1 1 12 Modem Interface The S3C6400 microprocessor provides the following Modem Interface features 1 1 12 1 Parallel Modem Chip Interface Asynchronous direct and indirect 16bit SRAM style interface i80 interface On chip 8...

Page 14: ...or Interrupt based operation 1 1 16 System Peripherals The S3C6400 microprocessor provides the following System Peripherals features 1 1 16 1 DMA controller 4 General DMAs embedded 2 master ports per DMA 8 channel supported per each DMA totally 32 channel is supported Supports memory to memory peripheral to memory memory to peripheral and peripheral to peripheral Burst transfer mode to enhance the...

Page 15: ...MA based or interrupt based operation Programmable duty cycle frequency and polarity Dead zone generation Support external clock source 1 1 16 6 16 bit Watchdog Timer Interrupt request or system reset at time out 1 1 16 7 RTC Real Time Clock Full clock features msec sec min hour day week month year 32 768 KHz operation Alarm interrupt Time tick interrupt 1 1 17 System Management The S3C6400 microp...

Page 16: ...mation herein are subject to change without notice Electrical Characteristics Operating Conditions o Supply Voltage for Logic Core VDD_INT 1 0V VDD_ARM depends on Operation Frequency o External Memory Interface 1 8 2 5V o External I O Interface 1 8 2 5 3 3V Operational Frequency o 400Mhz VDD_ARM 1 0V o 533Mhz VDD_ARM 1 1V o Max 667MHz TBD V Package 424 Pin FBGA For Small Form Factor application PO...

Page 17: ... in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Pin Assignments A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE A1 INDEX MARK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ...

Page 18: ...8 VDDARM B9 VDDM1 C9 XM1DATA7 A9 XM1DATA6 B10 XM1DATA13 C10 VDDARM A10 XM1DATA9 B11 VDDARM C11 XM1DATA14 A11 XM1DATA12 B12 XM1DATA16 C12 XM1DATA10 A12 XM1DATA18 B13 XM1DATA17 C13 XM1DATA19 A13 XM1SCLK B14 XM1DQS2 C14 VDDM1 A14 XM1SCLKN B15 XM1DATA22 C15 XM1DATA20 A15 XMMCDATA1_4 GHP6 B16 XMMCDATA1_2 GP H4 C16 XMMCDATA1_6 GPH8 A16 XMMCCMD1 GPH1 B17 VDDMMC C17 XMMCDATA1_1 GPH3 A17 XMMCCDN0 GPG6 B18 ...

Page 19: ...1 XM1DATA11 F24 XM1DATA25 H7 XM0ADDR4 D12 XM1DATA8 F25 XM1DATA26 H8 VSSIP D13 VDDI G1 XM0ADDR11 GPO11 H9 XMMCDATA1_7 GPH9 D14 XM1DQM2 G2 XM0ADDR10 GPO10 H10 XMMCDATA1_3 GPH5 D15 XM1DATA21 G3 VDDM0 H11 XMMCDATA1_0 GPH2 D16 XM1DATA23 G4 XM0ADDR7 GPO7 H12 XSPICLK1 GPC5 D17 XSPICS1 GPC7 G8 XM1DQM1 H13 XMMCDATA0_1 GPG3 D18 VDDI G9 XM1DQS1 H14 XSPICLK0 GPC1 D19 XURXD2 GPB0 G10 VDDM1 H15 XUCTSN1 GPA6 D20...

Page 20: ...LK GPp1 M25 XHIDATA17 GPL14 J12 VSSIP L4 XM0OEN N1 XM0DATA1 J13 VSSPERI L7 XM0DATA10 N2 XM0DATA0 J14 XURXD3 GPB2 L8 XM0DATA12 N3 XM0DATA3 J15 XURXD1 GPA4 L9 VSSIP N4 XM0DATA6 J18 VDDI L17 VDDI N7 XM0CSN0 J19 VDDM1 L18 XM1CSN1 N8 XM0CSN5 GPO3 J22 XM1ADDR9 L19 XM1ADDR4 N9 VSSIP J23 XM1ADDR2 L22 XM1RASN N17 XHIDATA16 GPL13 J24 XM1ADDR1 L23 XM1CSN0 N18 XHIDATA14 GPK14 J25 XM1ADDR6 L24 XM1CASN N19 VDDU...

Page 21: ...DHI T23 XHIDATA3 GPK3 V8 XOM3 P25 XHIDATA8 GPK8 T24 XHIDATA2 GPK2 V9 XNRESET R1 VDDM0 T25 XHIDATA0 GPK0 V10 XEINT1 GPN1 R2 XM0CSN3 GPO1 U1 XM0SCLKN GPQ3 V11 XEINT6 GPN6 R3 XM0CSN1 U2 XM0RASN GPQ0 V12 XEINT12 GPN12 R4 XM0WAITN GPP2 U3 XM0WENDMC GPQ7 V13 XVVD3 GPI3 R7 XM0INTATA GPP8 U4 XM0INTSM1_FREN GPP 6 V14 XVVD8 GPI8 R8 XM0RDY0_ALE GPP3 U7 XM0CDATA GPP14 V15 XVVD12 GPI12 R9 VSSIP U8 VSSMEM V16 X...

Page 22: ...DDEPLL AC5 VSSDAC W13 XEINT14 GPN14 AB2 VDDMPLL AC6 XDACOUT0 W14 XVVD1 GPI1 AB3 XM0OEATA GPP13 AC7 XDACCOMP W15 XVVD6 GPI6 AB6 VSSMEM AC8 XUSBREXT W16 XVVD11 GPI11 AB7 VSSOTG AC9 VDDOTG W17 XVVD14 GPI14 AB8 VSSOTGI AC10 VDDOTGI W18 XVVD22 GPJ6 AB9 XRTCXTI AC11 VDDRTC W22 XVVSYNC GPJ9 AB10 XJTRSTN AC12 XJTDO W23 XHIADR3 GPL3 AB11 XJTCK AC13 XOM2 W24 XHIADR1 GPL1 AB12 XJTDI AC14 VSSPERI W25 XHIIRQN ...

Page 23: ... AD1 NC_G AE2 NC_H AD2 XADCAIN2 AE3 XADCAIN4 AD3 XADCAIN3 AE4 XADCAIN6 AD4 XADCAIN5 AE5 XDACOUT1 AD5 VSSADC AE6 XDACIREF AD6 VDDDAC AE7 XDACVREF AD7 XUSBXTI AE8 VSSOTG AD8 XUSBXTO AE9 XUSBDM AD9 XUSBVBUS AE10 XUSBDP AD10 XUSBID AE11 XUSBDRVVBUS AD11 VDDOTG AE12 XJTMS AD12 XRTCXTO AE13 XJRTCK AD13 XOM0 AE14 XOM4 AD14 XPWRRGTON AE15 XNBATF AD15 XNWRESET AE16 VDDI AD16 XNRSTOUT AE17 XEINT0 GPN0 AD17 ...

Page 24: ...DDR 10 6 O O O O O ADDR 5 h0 5 h0 ADDR ADDR GPO 10 6 EINT7 10 6 Xm0ADDR 15 11 O O O O O ADDR 5 h0 5 h0 5 h0 ADDR GPO 15 11 EINT7 15 11 Xm0OEn O O O O O nOE nOE 1 b1 nIORD_CF 1 b1 Xm0WEn O O O O O nWE nWE 1 b1 nIOWR_CF 1 b1 Xm0ADRVALID O IO I nADDRVALID GPP 0 EINT8 0 Xm0SMCLK O IO I SMCLK GPP 1 EINT8 1 Xm0DATA 15 0 IO IO IO IO IO DATA DATA DATA DATA DATA Xm0WAITn I I IO I RDY IORDY GPP 2 EINT8 2 Xm...

Page 25: ...Memory port 0 SROM OneNAND NAND Flash Chip Select support up to 2 memory bank nCS 1 0 O Memory port 0 SROM Chip Select support up to 2 memory bank nBE 1 0 O Memory port 0 SROM Byte Enable WAITn I Memory port 0 SROM Wait nOE O Memory port 0 SROM OneNAND Output Enable nWE O Memory port 0 SROM OneNAND Write Enable ADDRVALID O Memory port 0 OneNAND Address Valid SMCLK O Memory port 0 OneNAND Clock RDY...

Page 26: ...etection DQM 1 0 O Memory port 0 DRAM Data Mask RAS O Memory port 0 DRAM Row Address Strobe CAS O Memory port 0 DRAM Column Address Strobe SCLK O Memory port 0 DRAM Clock SCLKn O Memory port 0 DRAM Inverted Clock of Xm0SCLK SCKE O Memory port 0 DRAM Clock Enable DQS 1 0 IO Memory port 0 DRAM Data Strobe WEn O Memory port 0 DRAM Write Enable AP O Memory port 0 DRAM Auto Precharge DRAM mDDR and mSDR...

Page 27: ... Half Data bus Xm1DATA 31 16 IO Xm0ADDR 26 16 of SROMC Xm1DATA 31 16 can be used as Memory port 1 DRAM Upper Half Data bus by System Controller setting Xm1DQM 3 0 O Memory port 1 DRAM Data Mask Xm1DQS 3 0 IO Memory port 1 DRAM Data Strobe 1 1 18 2 Serial Communication UART IrDA CF I O Function Signal 0 1 2 3 4 5 6 0 1 2 3 4 5 6 XuRXD 0 I IO I XuRXD 0 GPA 0 EINT1 0 XuTXD 0 O IO I XuTXD 0 GPA 1 EINT...

Page 28: ... send input signal XuRTSn 1 O UART 1 request to send output signal XuRXD 2 I UART 2 receive data input XuTXD 2 O UART 2 transmits data output XuRXD 3 I UART 3 receive data input XuTXD 3 O UART 3 transmits data output XirSDBW O IrDA transiver control signal Shutdown and bandwidth control XirRXD I IrDA Rx data XirTXD O IrDA Tx data ADDR_CF 2 0 O CF card address EINT1 12 0 I External Interrupt 1 IIC ...

Page 29: ...SPI chip select only for slave mode XspiMISO 1 IO SPI MISO 1 SPI master data input line XspiCLK 1 IO SPI CLK 1 SPI clock for channel 1 XspiMOSI 1 IO SPI MOSI 1 SPI master data output line XspiCS 1 IO SPI chip select only for slave mode ADDR_CF 2 0 O CF card address EINT2 7 0 I External Interrupt 2 XmmcCMD2 IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 XmmcCLK2 O CLOCK SD SDIO MMC card i...

Page 30: ...ck XpcmEXTCLK 1 I optional reference clock divided internally to generate PCM timing and XpcmDCLK XpcmFSYNC 1 O PCM Sync indicating start of word XpcmSIN 1 I PCM Serial Data Input XpcmSOUT 1 O PCM Serial Data Output Xi2sLRCK 1 0 IO IIS bus channel select clock Xi2sCDCLK 1 0 O IIS CODEC system clock Xi2sCLK 1 0 IO IIS bus serial clock Xi2sDI 1 0 I IIS bus serial data input Xi2sDO 1 0 O IIS bus seri...

Page 31: ...5 XEINT 0 I IO XEINT 0 XkpROW 0 GPN 0 XEINT 1 I IO XEINT 1 XkpROW 1 GPN 1 XEINT 2 I IO XEINT 2 XkpROW 2 GPN 2 XEINT 3 I IO XEINT 3 XkpROW 3 GPN 3 XEINT 4 I IO XEINT 4 XkpROW 4 GPN 4 XEINT 5 I IO XEINT 5 XkpROW 5 GPN 5 XEINT 6 I IO XEINT 6 XkpROW 6 GPN 6 XEINT 7 I IO XEINT 7 XkpROW 7 GPN 7 XEINT 8 I O IO XEINT 8 ADDR_CF 0 GPN 8 XEINT 9 I O IO XEINT 9 ADDR_CF 1 GPN 9 XEINT 10 I O IO XEINT 10 ADDR_CF...

Page 32: ...A DATA_CF 3 DATA_CF 3 GPK 3 XhiDATA 4 IO I IO IO IO XhiDATA 4 XhtxREADY DATA_CF 4 DATA_CF 4 GPK 4 XhiDATA 5 IO O IO IO IO XhiDATA 5 XhtxWAKE DATA_CF 5 DATA_CF 5 GPK 5 XhiDATA 6 IO O IO IO IO XhiDATA 6 XhtxFLAG DATA_CF 6 DATA_CF 6 GPK 6 XhiDATA 7 IO O IO IO IO XhiDATA 7 XhtxDATA DATA_CF 7 DATA_CF 7 GPK 7 XhiDATA 15 8 IO I IO IO XhiDATA 15 8 XkpROW 7 0 DATA_CF 15 8 GPK 15 8 XhiDATA 16 IO I IO IO Xhi...

Page 33: ...d to indicate to the receiver that the transmitter is willing to start a transmission Application to Modem XhtxFLAG O Application to Modem XhtxDATA O Bit transmission in both directions occurs over a two wire DATA FLAG serial interface The bits are transmitted sequentially starting with the most significant bit of the physical layer frame The DATA line always reflects the value being transmitted a...

Page 34: ...XciYDATA 4 I IO I XciYDATA 4 GPF 9 EINT4 9 XciYDATA 5 I IO I XciYDATA 5 GPF 10 EINT4 10 XciYDATA 6 I IO I XciYDATA 6 GPF 11 EINT4 11 XciYDATA 7 I IO I XciYDATA 7 GPF 12 EINT4 12 Signal I O Description XciCLK O Master Clock to the Camera processor A XciHREF I Horizontal Sync driven by the Camera processor A XciPCLK I Pixel Clock driven by the Camera processor A XciVSYNC I Vertical Sync driven by th...

Page 35: ...l for RGB interface XvSYS_Wen i80 Write Enable control XvVSYNC O O IO XvVSYNC Vertical synchronous signal for RGB interface XvSYS_CSn_sub i80 Sub LCD Chip select control XvHSYNC O O IO XvHSYNC Horizontal synchronous signal for RGB interface XvSYS_CSn_main i80 Main LCD Chip select control XvVDEN O O IO XvVDEN Data enable signal for RGB interface XvSYS_RS i80 Register Status Signal control 2 ch DAC ...

Page 36: ...I GPH 3 XmmcDAT1 1 EINT6 3 XmmcDAT1 2 IO IO O I GPH 4 XmmcDAT1 2 EINT6 4 XmmcDAT1 3 IO IO O I GPH 5 XmmcDAT1 3 EINT6 5 XmmcDAT1 4 IO IO IO O O I GPH 6 XmmcDAT1 4 XmmcDAT2 0 ADDR_CF 0 EINT6 6 XmmcDAT1 5 IO IO IO O O I GPH 7 XmmcDAT1 5 XmmcDAT2 1 ADDR_CF 1 EINT6 7 XmmcDAT1 6 IO IO IO O O I GPH 8 XmmcDAT1 6 XmmcDAT2 2 ADDR_CF 2 EINT6 8 XmmcDAT1 7 IO IO IO O O I GPH 9 XmmcDAT1 7 XmmcDAT2 3 EINT6 9 Sig...

Page 37: ...nternal osc circuit XXTO O Crystal output for internal osc circuit XEXTCLK I External clock source JTAG Signal I O Description XjTRSTn I XjTRSTn TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used XjTRSTn pin must be at L or low active pulse Note Whenever Reset operates XjTRSTn pin must be low acti...

Page 38: ...r MPLL core 1 0 VDDAPLL P Power for APLL core 1 0 VDDEPLL P Power for EPLL core 1 0 VDDOTG P Power for USB OTG PHY 3 3 VDDOTGI P Internal power for USB OTG PHY 1 0 VDDMMC P IO power for SDMMC 1 8 3 3 VDDHI P IO power for Host I F 1 8 3 3 VDDLCD P IO power for LCD 1 8 3 3 VDDPCM P IO power for PCM Audio I F I2S AC97 1 8 3 3 VDDEXT P IO power for external I F UART I2C Camera I F USB Host etc 1 8 3 3...

Page 39: ...rein are subject to change without notice VSSOTGI G Internal Ground for USB OTG PHY VSSPERI G IO ground for USB HOST SDMMC Host I F LCD PCM External I F and System Controller VSSAPLL G Ground for APLL core VSSMPLL G Ground for MPLL core VSSEPLL G Ground for EPLL core VSSADC G Ground for ADC core VSSDAC G Ground for DAC core Note 1 IO stands for input output 2 AI AO stands for analog input output 3...

Page 40: ...information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 2 MEMORY MAP 2 1 MEMORY SYSTEM BLOCK DIAGRAM Figure 2 1 Address Map ...

Page 41: ...and can be mapped to boot image area when internal ROM booting is selected Address range of internal SRAM is from 0x0C00_0000 to 0x0FFF_FFFF but real storage is only 4KB This region can be read and written and can be mapped to boot image area when NAND Flash booting is selected Address range of static memory area is from 0x1000_0000 to 0x3FFF_FFFF SROM SRAM NOR Flash asyncronous NOR interface devi...

Page 42: ...al ROM Mirrored Region 0x0800_0000 0x0BFF_FFFF 64MB Internal ROM 0x0C00_0000 0x0FFF_FFFF 64MB Stepping Stone Boot Loader 0x1000_0000 0x17FF_FFFF 128MB SMC Bank 0 0x1800_0000 0x1FFF_FFFF 128MB SMC Bank 1 0x2000_0000 0x27FF_FFFF 128MB SMC Bank 2 0x2800_0000 0x2FFF_FFFF 128MB SMC Bank 3 0x3000_0000 0x37FF_FFFF 128MB SMC Bank 4 0x3800_0000 0x3FFF_FFFF 128MB SMC Bank 5 0x4000_0000 0x47FF_FFFF 128MB Mem...

Page 43: ...FFFF TZIC1 0x7120_0000 0x712F_FFFF INTC0 0x7130_0000 0x713F_FFFF INTC1 0x7140_0000 0x71FF_FFFF Reserved 0x7200_0000 0x72FF_FFFF Reserved 0x7300_0000 0x7300_0FFF ETB Memory 0x7310_0000 0x731F_FFFF ETB Registers 0x7320_0000 0x73FF_FFFF Reserved 0x7400_0000 0x740F_FFFF Indirect Host I F 0x7410_0000 0x741F_FFFF Direct Host I F 0x7420_0000 0x742F_FFFF Reserved 0x7430_0000 0x743F_FFFF USB Host 0x7440_00...

Page 44: ...0x79FF_FFFF Reserved 0x7A00_0000 0x7AFF_FFFF Reserved 0x7B00_0000 0x7BFF_FFFF Reserved 0x7C00_0000 0x7C0F_FFFF USB OTG 0x7C10_0000 0x7C1F_ FFFF USB OTG SFR 0x7C20_0000 0x7C2F_ FFFF SD MMC Controller 0 High Speed CE ATA 0x7C30_0000 0x7C3F_ FFFF SD MMC Controller 1 High Speed CE ATA 0x7C40_0000 0x7C4F_ FFFF SD MMC Controller 2 High Speed CE ATA 0x7C50_0000 0x7C5F_ FFFF Reserved 0x7D00_0000 0x7D0F_FF...

Page 45: ...0x7E00_7000 0x7E00_7FFF HIS RX 0x7E00_8000 0x7E00_8FFF Reserved 0x7E00_9000 0x7E00_9FFF Reserved 0x7E00_A000 0x7E00_AFFF Keypad I F 0x7E00_B000 0x7E00_BFFF ADC Touch Screen 0x7E00_C000 0x7E00_CFFF ETM 0x7E00_D000 0x7E00_DFFF Key 0x7E00_E000 0x7E00_EFFF Chip ID 0x7E00_F000 0x7E00_FFFF System Controller 0x7F00_0000 0x7F00_0FFF TZPC 0x7F00_1000 0x7F00_1FFF AC97 0x7F00_2000 0x7F00_2FFF I2S Ch0 0x7F00_...

Page 46: ...ssary for a certain application For example if a timer is not required the user can disconnect the clock to the timer to reduce power IDLE mode disconnects the ARMCLK only to CPU core while it supplies the clock to all peripherals By using IDLE mode the power consumption due to CPU core can be reduced STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLL s The power consu...

Page 47: ...rollers through 64 bit AXI bus to meet bandwidth requirements Media co processors which include MFC Multi Format Codec JPEG Camera interface TV encoder and etc are divided into five power domains The five power domain can be controlled independently to reduce unwanted power consumption when the IP s are not required for an application program Scaler MFC JPEG Cam I F AHB I 2D TV Enc AHB P LCD ROT P...

Page 48: ...le Specifications and information herein are subject to change without notice CLOCK ARCHITECTURE Figure 3 2 shows the block diagram of the clock generation module The clock source selects between an external crystal XXTIpll and external clock XEXTCLK The clock generator consists of three PLL s Phase Locked Loop which generate high frequency clock signals up to 1 4GHz Figure 3 2 The block diagram o...

Page 49: ...mainly classified into six categories according to the boot device The boot device can be among NAND SROM NOR OneNAND MODEM Internal ROM The additional characteristics can be selected when the boot device is NAND as shown Table 3 1 When NAND Flash device is used XSELNAND pin must be 1 whether is used as boot device or storage device When OneNAND Flash device is used XSELNAND must be 0 whether it i...

Page 50: ...Pre Divider P Fin P P 5 0 S 2 0 S 2 0 AVBBD C1 DVSS10D Figure 3 3 PLL block diagram APLL MPLL only Clock selection between PLL s and input reference clock Figure 3 4 shows the clock generation logic S3C6400X has three PLL s which are APLL for ARM operating clock MPLL for main operating clock and EPLL for special purpose The operating clocks are divided into three groups The first is ARM clock whic...

Page 51: ...between AHB and APB has high dependency to synchronize data transmission Figure 3 5 shows the part of bus clock generation to meet the requirements of bus system clocks APLL 1 0 1 0 EXTCLK XTIpll MPLL 1 0 0 1 HCLKx2 MUXMPLL MUXAPLL SYNCMUX HCLK PCLK DIVPCLK CLKJPEG DIVCLKJPEG CLKSECUR DIVCLKSECUR DIVHCLKX2 DIVHCLK CLK_DIV0 11 9 CLK_DIV0 8 CLK_DIV0 15 12 CLK_DIV0 27 24 CLK_DIV0 19 18 HCLK_GATE 29 2...

Page 52: ...cy APLL MPLL DIVARM DIVHCLKX2 DIVHCLK DIVPCLK DIVCLKJPEG DIVCLKSECUR 266MHz 266MHz 0 266MHz 0 266MHz 1 133MHz 3 66MHz 3 66MHz 3 66MHz 400MHz 266MHz 0 400MHz 0 266MHz 1 133MHz 3 66MHz 3 66MHz 3 66MHz 533MHz 266MHz 0 533MHz 0 266MHz 1 133MHz 3 66MHz 3 66MHz 3 66MHz 667MHz 266MHz 0 667MHz 0 266MHz 1 133MHz 3 66MHz 3 66MHz 3 66MHz The divider for ARM independently uses the output clock of APLL and the...

Page 53: ...addition to HCLK and PCLK The additional clock is generated as shown in Figure 3 8 Figure 3 8 MFC clock generation The source clock is selected between HCLKX2 and MOUTEPLL The operating clock is divided using HCLKX2 The operating frequency of HCLKX2 is fixed as 266MHz by default Therefore CLK_DIV0 31 28 must be 4 b0001 to generate 133MHz When MFC is not required full performance there are two way ...

Page 54: ...F clock generation Clock generation for display POST LCD and scaler Figure 3 10 shows the clock generator for display blocks Usually LCD controller requires image post processor and scaler logic The operating clocks can be independently controlled with this clock generator CLKLCD and CLKPOST are connected to LCD controller and post processor respectively within domain F CLKSCALER is connected to s...

Page 55: ... MPLL 1 0 DIVMPLL 1 0 EXTCLK XTIpll MUXMPLL CLKAUDIO0 DIVAUDIO0 SCLK_GATE 8 CLK_DIV2 11 8 CLKAUDIO1 DIVAUDIO1 SCLK_GATE 9 CLK_DIV2 15 12 CLK_SRC 1 CLK_SRC 2 CLK_DIV0 4 1 0 2 3 4 1 0 2 3 4 MUXAUDIO0 MUXAUDIO1 IISCDCLK0 PCMCDCLK IISCDCLK1 CLK_SRC 9 7 CLK_SRC 12 10 Figure 3 11 Audio clock generation Clock generation for UART SPI and MMC Figure 3 12 shows the clock generator for UART SPI and MMC There...

Page 56: ...ebugging purpose For more information please refer to CLK_OUT register section LOW POWER MODE OPERATION S3C6400X supports low power application through low power mode operation as shown in Table 3 3 There are four power states which are normal state retention state power gating state and power off state All internal logics including F Fs and memory are running at normal state Retention state reduc...

Page 57: ... including internal registers CPSR SPSR and etc before going to DEEP STOP mode NORMAL IDLE mode In NORMAL mode ARM1176 core media co processors and all peripherals can operate fully Typical system bus operating frequency is up to 133MHz The clock to each media co processors and peripherals can be stopped selectively by software to reduce power consumption The ON OFF clock gating of the individual ...

Page 58: ...on MCR p15 0 Rd c7 c0 4 3 SYSCON requests bus controller to finish current AHB bus transaction 4 AHB bus controller sends acknowledge to SYSCON after current bus transaction is completed 5 SYSCON requests DOMAIN V to finish current AXI bus transaction 6 AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed 7 SYSCON requests external memory controllers to enter i...

Page 59: ...tained during DEEP STOP mode Thus the boot code copying period can be ignored Figure 3 16 shows the status at DEEP STOP mode The black boxes denote power gating blocks and eliminate leakage current during DEEP STOP mode while top module retains the previous states as STOP mode DOMAIN V DOMAIN I DOMAIN P DOMAIN F MEMSYS DOMAIN X DOMAIN T DOMAIN M DOMAIN S ARM11 PERIPHERAL AXI 64b AXI 32b APB 32b Fi...

Page 60: ...6 AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed 7 SYSCON requests external memory controllers to enter into self refresh mode since the contents in the external memory must be preserved during SLEEP mode 8 The memory controllers send acknowledges when they are self refresh mode 9 SYSCON changes clock source from PLL output to external oscillator if PLL i...

Page 61: ...tal and complete reset that is used when you do not require information in system any more It fully initializes all system z Warm reset It is generated by asserting XnWRESET XnWRESET is used to initialize S3C6400X and preserve current hardware status z Watchdog reset It is generated by a special hardware block i e watchdog timer When the system is hanged due to an unpredictable software error the ...

Page 62: ... requests AHB bus controller to finish current AHB bus transactions 2 AHB bus controllers send acknowledges to SYSCON after current bus transactions are finished 3 SYSCON request DOMAIN V to finish current AXI bus transaction 4 AXI bus controller sends acknowledge to SYSCON after the current bus transaction is finished 5 SYSCON requests external memory controllers to enter into self refresh mode s...

Page 63: ...N GPMDAT GPMPUD GPNCON GPNDAT GPNPUD GPOCON GPOPUD GPPCON GPPPUD GPQCON GPQPUD EINT0CON0 EINT0CON1 EINT0FLTCON0 EINT0FLTCON1 EINT0FLTCON2 EINT0FLTCON3 EINT0MASK EINT0PEND SPCONSLP SLPEN X X X X O Others O O O O O MISC There are several registers to control S3C6400X S3C6400X consists of several AHB buses and one AXI components Several master IP are connected in on AHB buses Generally bus utilizatio...

Page 64: ...put frequency for EPLL 0x0020_0102 EPLL_CON1 0x7E00_F018 R W Control PLL output frequency for EPLL 0x0000_9111 CLK_SRC 0x7E00_F01C R W Select clock source 0x0000_0000 CLK_DIV0 0x7E00_F020 R W Set clock divider ratio 0x0105_1000 CLK_DIV1 0x7E00_F024 R W Set clock divider ratio 0x0000_0000 CLK_DIV2 0x7E00_F028 R W Set clock divider ratio 0x0000_0000 CLK_OUT 0x7E00_F02C R W Select clock output 0x0000...

Page 65: ...er stable counter 0x0000_0001 RESERVED 0x7E00_F82C RESERVED MTC_STABLE 0x7E00_F830 R W MTC stable counter 0xFFFF_FFFF RESERVED 0x7E00_F834 0x7E00_F8FC RESERVED OTHERS 0x7E00_F900 R W Others control register 0x0000_801E RST_STAT 0x7E00_F904 R Reset status register 0x0000_0001 WAKEUP_STAT 0x7E00_F908 R W Wakeup status registers 0x0000_0000 BLK_PWR_STAT 0x7E00_F90C R Block power status register 0x000...

Page 66: ...quency for EPLL 0x0000_9111 A PLL requires locking period when input frequency is changed or frequency division multiplication values are changed PLL_LOCK register specifies this locking period which is based on PLL s source clock During this period output will be masked 0 APLL_LOCK MPLL_LOCK EPLL_LOCK BIT DESCRIPTION RESET VALUE RESERVED 31 16 RESERVED 0x0000 PLL_LOCKTIME 15 0 Required period to ...

Page 67: ...V 63 SDIV 0 SDIV 5 FVCO MDIV X FIN PDIV 750MHz FVCO 1400MHz FOUT 24MHz FOUT 1400MHz FIN 10Mhz FIN 20Mhz FIN MHz Target FOUT MHz MDIV PDIV SDIV 12 266 532 6 2 12 400 400 6 1 12 533 533 6 1 12 667 667 6 1 EPLL_CON0 BIT DESCRIPTION RESET VALUE ENABLE 31 PLL enable control 0 disable 1 enable 0 RESERVED 30 24 RESERVED 0x00 MDIV 23 16 PLL M divide value 0x20 RESERVED 15 14 RESERVED 0x0 PDIV 13 8 PLL P d...

Page 68: ...ithout notice NOTE1 The output frequency is calculated by using the following equation FOUT MDIV KDIV 216 X FIN PDIV X 2SDIV where MDIV PDIV SDIV for APLL and MPLL must meet the following conditions MDIV 13 MDIV 255 PDIV 1 PDIV 63 KDIV 0 KDIV 65535 SDIV 0 SDIV 5 FVCO MDIV KDIV 216 X FIN PDIV 250MHz FVCO 600MHz FOUT 16MHz FOUT 600MHz FIN 10Mhz FIN 20Mhz FIN MHz FOUT MHz MDIV PDIV SDIV KDIV 12 36 24...

Page 69: ... 00 MOUTEPLL 01 DOUTMPLL 10 FINEPLL 0x0 IRDA_SEL 25 24 Control MUXIRDA which is the source clock of IRDA 00 MOUTEPLL 01 DOUTMPLL 10 FINEPLL 11 48MHz 0x0 MMC2_SEL 23 22 Control MUXMMC2 which is the source clock of MMC2 00 MOUTEPLL 01 DOUTMPLL 10 FINEPLL 11 27MHz 0x0 MMC1_SEL 21 20 Control MUXMMC1 which is the source clock of MMC1 00 MOUTEPLL 01 DOUTMPLL 10 FINEPLL 11 27MHz 0x0 MMC0_SEL 19 18 Contro...

Page 70: ...zation data and associated errata are not yet available Specifications and information herein are subject to change without notice MFCCLK_SEL 4 Control MUXMFC which is the source clock of MFC 0 RESERVED 3 RESERVED 0 EPLL_SEL 2 Control MUXEPLL 0 FINEPLL 1 FOUTEPLL 0 MPLL_SEL 1 Control MUXMPLL 0 FINMPLL 1 FOUTMPLL 0 APLL_SEL 0 Control MUXAPLL 0 FINAPLL 1 FOUTAPLL 0 ...

Page 71: ...CROPROCESSOR 3 26 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice ...

Page 72: ...z 133MHz and 66MHz respectively NAND SECUR JPEG operating clock cannot exceed 66MHz MFC and CAM operating clock cannot exceed 133MHz This operating clock condition must be met through CLK_DIV0 configuration User software must be care for the clock divider controlled by CLK_DIV0 Since the output frequency will be varying during the clock ratio changing period as shown in Figure 3 6 CLK_DIV0 BIT DES...

Page 73: ...12 LCD clock divider ratio CLKLCD CLKLCDIN LCD_RATIO 1 0x0 MMC2_RATIO 11 8 MMC2 clock divider ratio CLKMMC2 CLKMMC2IN MMC2_RATIO 1 0x0 MMC1_RATIO 7 4 MMC1 clock divider ratio CLKMMC1 CLKMMC1IN MMC1_RATIO 1 0x0 MMC0_RATIO 3 0 MMC0 clock divider ratio CLKMMC0 CLKMMC0IN MMC0_RATIO 1 0x0 CLK_DIV2 controls SPI AUDIO UART and IrDA clocks CLK_DIV2 BIT DESCRIPTION RESET VALUE RESERVED 31 24 RESERVED 0x0 I...

Page 74: ...2C R W Select clock output 0x0000_0000 CLK_OUT BIT DESCRIPTION RESET VALUE RESERVED 31 20 RESERVED 0x000 DIVVAL 19 16 Divide ratio Divide ratio DIVVAL 1 If this field has not 0 DCLKCMP has no meanng Therefore DOUT is always 50 duty ratio when DIVVAL 0 0x0 RESERVED 15 RESERVED 0 CLKSEL 14 12 000 FOUTAPLL 2 001 FOUTEPLL 010 HCLK 011 CLK48M 100 CLK27M 101 RTC 110 TICK 111 DOUT 0x0 DCLKCMP 11 8 This f...

Page 75: ...K_UHOST 29 Gating HCLK for UHOST 0 mask 1 pass 1 HCLK_SECUR 28 Gating HCLK for security sub system 0 mask 1 pass 1 HCLK_SDMA1 27 Gating HCLK for SDMA1 0 mask 1 pass 1 HCLK_SDMA0 26 Gating HCLK for SDMA0 0 mask 1 pass 1 HCLK_IROM 25 Gating HCLK for IROM 0 mask 1 pass 1 HCLK_DDR1 24 Gating HCLK for DDR1 0 mask 1 pass 1 HCLK_DDR0 23 Gating HCLK for DDR0 0 mask 1 pass 1 HCLK_MEM1 22 Gating HCLK for DM...

Page 76: ... 0 mask 1 pass 1 PCLK_HSIRX 20 Gating PCLK for HSI receiver 0 mask 1 pass 1 PCLK_HSITX 19 Gating PCLK for HSI transmitter 0 mask 1 pass 1 PCLK_GPIO 18 Gating PCLK for GPIO 0 mask 1 pass 1 PCLK_IIC 17 Gating PCLK for IIC 0 mask 1 pass 1 PCLK_IIS1 16 Gating PCLK for IIS1 0 mask 1 pass 1 PCLK_IIS0 15 Gating PCLK for IIS0 0 mask 1 pass 1 PCLK_AC97 14 Gating PCLK for AC97 0 mask 1 pass 1 PCLK_TZPC 13 G...

Page 77: ...ck for SPI 0 mask 1 pass 1 SCLK_DAC27 19 Gating special clock for DAC 0 mask 1 pass 1 SCLK_TV27 18 Gating special clock for TV encoder 0 mask 1 pass 1 SCLK_SCALER27 17 Gating special clock for scaler27 0 mask 1 pass 1 SCLK_SCALER 16 Gating special clock for scaler 0 mask 1 pass 1 SCLK_LCD27 15 Gating special clock for LCD controller 0 mask 1 pass 1 SCLK_LCD 14 Gating special clock for LCD controll...

Page 78: ...bus 0x0000_0000 AHB_CON2 0x7E00_F108 R W Configure AHB R S1 S0 bus 0x0000_0000 The arbitration method for each AHB bus can be configured using PRIOR_TYPE_name field as follows z 00 Fixed priority type Its priority is defined using FIX_PRIOR_name field z 01 Last grant lowest Last granted master has lowest arbitration value z 10 Rotation When the priority type filed selects the fixed priority 00 the...

Page 79: ...YPE_P 21 20 Arbitration type for AHB P 0 RESERVED 19 RESERVED 0 FIX_PRIOR_P 18 16 Fixed priority order for AHB P 0x0 DISABLE_HLOCK_X 15 Control HLOCK for X block 0 disable 1 enable 0 RESERVED 14 RESERVED 0 PRIOR_TYPE_X 13 12 Arbitration type for AHB X 0 RESERVED 11 RESERVED 0 FIX_PRIOR_X 10 8 Fixed priority order for AHB X 0x0 DISABLE_HLOCK_F 7 Control HLOCK for F block 0 disable 1 enable 0 RESERV...

Page 80: ...1 26 24 Fixed priority order for AHB M1 0x0 RESERVED 23 22 RESERVED 0x0 PRIOR_TYPE_M0 21 20 Arbitration type for AHB M0 0 RESERVED 19 RESERVED 0 FIX_PRIOR_M0 18 16 Fixed priority order for AHB M0 0x0 DISABLE_HLOCK_T 15 Control HLOCK for T block 0 disable 1 enable 0 RESERVED 14 RESERVED 0 PRIOR_TYPE_T1 13 12 Arbitration type for AHB T1 0 RESERVED 11 RESERVED 0 FIX_PRIOR_T1 10 8 Fixed priority order...

Page 81: ... Control HLOCK for R block 0 disable 1 enable 0 RESERVED 22 16 RESERVED 0 DISABLE_HLOCK_S 15 Control HLOCK for S block 0 disable 1 enable 0 RESERVED 14 RESERVED 0 PRIOR_TYPE_S1 13 12 Arbitration type for AHB S1 0 RESERVED 11 RESERVED 0 FIX_PRIOR_S1 10 8 Fixed priority order for AHB S1 0x0 RESERVED 7 6 RESERVED 0x0 PRIOR_TYPE_S0 5 4 Arbitration type for AHB S0 0 RESERVED 3 RESERVED 0 FIX_PRIOR_S0 2...

Page 82: ...r PCM output 0 SDMA1 1 DMA1 0 SPI1_RX 21 DMA selection for SPI1 Rx 0 SDMA1 1 DMA1 0 SPI1_TX 20 DMA selection for SPI1 Tx 0 SDMA1 1 DMA1 0 I2S1_RX 19 DMA selection for I2S1 Rx 0 SDMA1 1 DMA1 0 I2S1_TX 18 DMA selection for I2S1 Tx 0 SDMA1 1 DMA1 0 PCM1_RX 17 DMA selection for PCM1 Rx 0 SDMA1 1 DMA1 0 PCM1_TX 16 DMA selection for PCM1 Tx 0 SDMA1 1 DMA1 0 HSI_RX 15 DMA selection for HSI Rx 0 SDMA0 1 D...

Page 83: ...sociated errata are not yet available Specifications and information herein are subject to change without notice Software reset control register REGISTER ADDRESS R W DESCRIPTION RESET VALUE SW_RST 0x7E00_F114 R W Generate software reset 0x0000_0000 SW_RST BIT DESCRIPTION RESET VALUE RESERVED 31 16 RESERVED 0x0000 SWRESET 15 0 Generate software reset when the value is 0x6400 0x0000 ...

Page 84: ...on and pass 0x0000_0000 PRODUCT_ID 0x7E00_FA1C R Product ID 0x3640_0202 SYS_ID BIT DESCRIPTION RESET VALUE RESERVED 31 8 RESERVED 0x0000_00 Revision 7 4 Specification revision 0x0 Pass 3 0 Layout revision 0x0 PRODUCT_ID BIT DESCRIPTION RESET VALUE PRODUCT CODE 31 12 Product code number 0x36400 0x3_6400 S W VERSION 11 8 Software version 0x2 REVISION 7 0 Layout revision 0x02 Note PRODUCT_ID register...

Page 85: ..._CFG BIT DESCRIPTION RESET VALUE RESERVED 31 15 RESERVED 0x0000_0 INDEP_CF 14 Use CF interface independently 0 Use memory port 0 shared by EBI 1 Use independent CF interface 0 RESERVED 13 RESERVED 0 BUS_WIDTH 12 Select initial state of SROMC CS0 memory bus width 0 8 bit data width 1 16 bit data width If NOR booting OM 4 1 0101 is selected this setting is ignored and 16 bit data width is selected E...

Page 86: ...lexing of memory port 0 Setting for MP0_CS_SEL 0 and MP0_CS_SEL 2 are ignored Distinguishing OneNANDC and NFCON is done by XSELNAND pin value instead of MP0_CS_SEL 0 and MP0_CS_SEL 2 When XSELNAND is 0 OneNANDC is selected When XSELNAND is 1 NFCON is selected When NAND booting OM 4 3 00 is selected the setting values of MP0_CS_SEL 1 and MP0_CS_SEL 3 as well as XSELNAND setting are ignored and Xm0C...

Page 87: ...0x00 I_BLOCK Camera and JPEG 0x01 F_BLOCK Display 0x02 P_BLOCK POST 0x03 V_BLOCK MFC 0x04 X_BLOCK HSMMC and OTG 0x05 T_BLOCK Host I F 0x06 M_BLOCK DMA 0x07 S_BLOCK Security 0x08 ARMI ARM Core Instruction 0x09 ARMRW ARM Core Data 0x0A ARMD ARM Core DMA 0x0B CF CFCON 0000 MEM_CFG_STAT BIT DESCRIPTION RESET VALUE RESERVED 31 16 RESERVED 0x0000_00 CFG_PRI_TYPE 15 Current EBI priority scheme See the EB...

Page 88: ... OneNANDC CS0 11 Internal ROM XOM dependent CFG_ADDR_EXPAN D 4 Show whether Xm1DATA 31 16 pins are used for SROMC address field or not 0 Xm1DATA 31 16 pins are used for DMC1 upper halfword data field data 31 16 1 Xm1DATA 31 16 pins are used for SROMC upper 10 bit address field address 25 16 0 CFG_ADV_FLASH 3 Show whether initial setting of NAND flash is advanced flash or not 0 Normal NAND flash 1 ...

Page 89: ...ake up source 0 use as a wakeup source 1 disable 0 MMC1_WAKEUP_MASK 15 MMC1 wake up source 0 use as a wakeup source 1 disable 0 MMC0_WAKEUP_MASK 14 MMC0 wake up source 0 use as a wakeup source 1 disable 0 HSI_WAKEUP_MASK 13 HSI wake up source 0 use as a wakeup source 1 disable 0 TS_WAKEUP_MASK 12 Touch screen wake up source 0 use as a wakeup source 1 disable 0 TICK_WAKEUP_MASK 11 RTC TICK wake up ...

Page 90: ...affects on NORMAL mode Thus this field must clear when EINT is used as a normal external interrupt source 0x00_0000 NORMAL_CFG BIT DESCRIPTION RESET VALUE RESERVED 31 DO NOT CHANGE 1 IROM 30 0 LP mode OFF 1 active mode ON 1 RESERVED 29 17 DO NOT CHANGE 0x1FFF DOMAIN_ETM 16 0 LP mode OFF 1 active mode ON 1 DOMAIN_S 15 0 LP mode OFF 1 active mode ON 1 DOMAIN_F 14 0 LP mode OFF 1 active mode ON 1 DOM...

Page 91: ...is field must be 0 before entering STOP mode 1 RESERVED 7 2 DO NOT CHANGE 0x00 PLL_EN 1 Control PLL operation in STOP mode 0 disable 1 enable 0 OSC_EN 0 Control X tal oscillator pad in STOP mode 0 disable 1 enable 0 SLEEP_CFG BIT DESCRIPTION RESET VALUE RESERVED 31 1 RESERVED 0x0000_0000 OSC_EN 0 Control X tal oscillator pad in SLEEP mode 0 disable 1 enable 0 Note1 ETMocks must be power ON before ...

Page 92: ...28 R W Power stable counter 0x0000_0001 MTC_STABLE 0x7E00_F830 R W MTC stable counter 0xFFFF_FFFF OSC_FREQ BIT DESCRIPTION RESET VALUE RESERVED 31 4 RESERVED 0x0000 OSC_FREQ_VALUE 3 0 Oscillator frequency scale counter OSC_FREQ_VALUE oscillator_frequency 200ns 0xF OSC_STABLE BIT DESCRIPTION RESET VALUE RESERVED 31 4 RESERVED 0x0000_000 OSC_CNT_VALUE 3 0 Oscillation pad stable counter value Value C...

Page 93: ...bilization counter for domain S 0xF DOMAIN_F 19 16 Memory power stabilization counter for domain F 0xF DOMAIN_P 15 12 Memory power stabilization counter for domain P 0xF DOMAIN_I 11 8 Memory power stabilization counter for domain I 0xF DOMAIN_V 7 4 Memory power stabilization counter for domain V 0xF DOMAIN_TOP 3 0 Memory power stabilization counter for domain TOP 0xF MTC_STABLE represents the numb...

Page 94: ...N until software clear it using this field 0 CLEAR_BATF_INT 12 Clear interrupt caused by battery fault when this bit is set 0 RESERVED 11 7 DO NOT CHANGE 0x00 SYNCMUXSEL 6 SYNCMUX selection 0 MOUTMPLL 1 DOUTAPLL 0 RESEVED 5 3 DO NOT CHANGE 0x3 SPNIDEN 2 Secure privileged non invasive debug enable This field enables and disables non invasive debug in the secure world of ARM1176 If it is 1 non invas...

Page 95: ...nWRESET This field is not set when the wakeup source of SLEEP mode is XnWRESET 0 HW_RESET 0 External reset by XnRESET 1 WAKEUP_STAT BIT DESCRIPTION RESET VALUE RESERVED 31 12 RESERVED 0x0000_0 MMC2_WAKEUP 11 Wake up by MMC2 This is cleared by writing 1 0 MMC1_WAKEUP 10 Wake up by MMC1 This is cleared by writing 1 0 MMC0_WAKEUP 9 Wake up by MMC0 This is cleared by writing 1 0 HSI_WAKEUP 8 Wake up b...

Page 96: ...rata are not yet available Specifications and information herein are subject to change without notice BLK_PWR_STAT BIT DESCRIPTION RESET VALUE RESERVED 31 7 RESERVED 0x0000_000 BLK_ETM 6 Block ETM power ready 1 BLK_S 5 Block S power ready 1 BLK_F 4 Block F power ready 1 BLK_P 3 Block P power ready 1 BLK_I 2 Block I power ready 1 BLK_V 1 Block V power ready 1 BLK_TOP 0 Block TOP power ready 1 ...

Page 97: ... to change without notice Information register REGISTER ADDRESS R W DESCRIPTION RESET VALUE INFORM0 0x7E00_FA00 R W Information register 0 0x0000_0000 INFORM1 0x7E00_FA04 R W Information register 1 0x0000_0000 INFORM2 0x7E00_FA08 R W Information register 2 0x0000_0000 INFORM3 0x7E00_FA0C R W Information register 3 0x0000_0000 INFORMn BIT DESCRIPTION RESET VALUE INFORM 31 0 User defined information...

Page 98: ...CONTROLLER 3 53 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTE ...

Page 99: ... 32 bit AHB slave interfaces one for data transfer and the other for SFR setting and one APB interface for DMC SFR setting Memory Subsystem gets booting method and CS selection information from the System Controller Internal AHB data bus connects 32 bit AHB slave data bus with SROMC two OneNANDC and NFCON Internal AHB SFR bus connects 32 bit AHB slave SFR bus with SROMC two OneNANDC CFCON and NFCO...

Page 100: ...rface EBIREQ EBIGNT and EBIBACKOFF all active HIGH EBIREQ signals are asserted by memory controllers to indicate that they require external bus access The respective arbitrated EBIGNT is issued to the highest priority memory controller EBIBACKOFF is output by the EBI to signal that the memory controller must complete the current transfer and release the bus The EBI arbitration scheme keeps track o...

Page 101: ...it 16 bit Non shared control Non shared control Non shared control 11 bit upper address Port 1 AXI_SPINE 64 bit 16 bit OneNAND EBI EBI4 CS 7 0 Address 15 0 Data 15 0 Shared Control EBI3 EBI0 EBI1 EBI2 Slave Decoder AHB Decoder 32 bit AHB Master port 1 64 bit AXI Slave port 1 32 bit AXI Slave port 1 32 bit AHB Slave port 2 32 bit APB port 2 AXI_PERI 32 bit CFCON S Control NFCON S S Control EBI DMC0...

Page 102: ...e Advanced NAND Flash 0 Normal NAND 1 Advanced NAND Address Cycle In normal NAND 0 3 cycles 1 4 cycles In advanced NAND 0 4 cycles 1 5 cycles NAND Flash data bus Width 8 bit Page Size selection In normal NAND 0 256 byte 1 512 byte In advanced NAND 0 1 kbyte 1 2 kbyte z Port information SROM data bus width Can be changed by SROM Controller SFR setting 0 8 bit 1 16 bit Address Expand 0 Use Xm1DATA 3...

Page 103: ...d Xm0CSn 2 and Xm0CSn 3 are used as NFCON CS0 and NFCON CS1 In this case XSELNAND must be set to 1 When OneNAND booting XOM 4 1 0110 is selected the setting values of MP0_CS_SEL 1 and MP0_CS_SEL 3 setting are ignored Xm0CSn 2 and Xm0CSn 3 are used as OneNANDC CS0 and OneNANDC CS1 In this case XSELNAND must be set to 0 MP0_CS_SEL 5 4 3 2 1 0 XSELNAND Xm0CSn 0 x SROMC CS0 Xm0CSn 1 x SROMC CS1 1 x SR...

Page 104: ...7 DMC0 SROMC OneNANDC CS0 OneNANDC CS1 NFCON CFCON 1 DMC0 OneNANDC CS0 OneNANDC CS1 SROMC NFCON CFCON 2 DMC0 OneNANDC CS1 NFCON SROMC OneNANDC CS0 CFCON 3 DMC0 NFCON SROMC OneNANDC CS0 OneNANDC CS1 CFCON 4 DMC0 CFCON SROMC OneNANDC CS0 OneNANDC CS1 NFCON 5 SROMC DMC0 OneNANDC CS0 OneNANDC CS1 NFCON CFCON z Bus information MP0_QOS_OVERRIDE 15 0 Set QoS override ID to DMC0 QOS_OVERRIDE0 in System Co...

Page 105: ...rnal bus and is immediately granted because no other devices are requesting the bus If a higher priority device requests the bus when a lower priority device is in control of the external bus then the EBIBACKOFF signals the lower priority device to release the bus as soon as possible Figure 4 4 shows an example of this In Figure 4 4 a higher priority device requests the bus shortly after a device ...

Page 106: ...ibe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice MEMCLK1 MEMCLK2 EBIREQ1 EBIGNT1 EBICLK EBIREQ2 EBIBACKOFF1 EBIGNT2 EBIBACKOFF2 Figure 4 4 EBIBACKOFF signal ...

Page 107: ...resh NOP and MRS EMRS to SDRAM By writing command to memc_cmd register DRAM Controller can enter into states like Config Ready and Low_power DRAM Controller supports power down in three ways The DRAM Controller can automatically place the SDRAM into either the pre charge power down or active power down state by de asserting DMC0_CKE or DMC1_CKE when the SDRAM has been inactive for a number of cloc...

Page 108: ...ort extended MRS EMRS set z For Memory Port 1 CKE can be controlled separately z For Memory Port 1 Not supports 16bit SDR SDRAM mobile SDR SDRAM BLOCK DIAGRAM Following figure 5 1 shows the block diagram of PL340 DRAM Controller AXI domain APB domain Memory domain APB slave interface AMBA 3 0 APB interface Memory interface Pad interface External memory interface to SDRAM AXI slave interface Arbite...

Page 109: ...re zero when reset If the value is one Xm0CKE and Xm1CKE are one when reset Table 5 1 Memory Port 0 Pin Description Signal Type Description Xm0SCLK Input Memory clock Xm0SCLKn Input Memory clock negative Xm0CKE Input Clock enable per chip Xm0CSn 6 7 Input Chip select per chip active low Xm0RAS Input Row address strobe active low Xm0CAS Input Column address strobe active low Xm0WEndmc Input Write e...

Page 110: ...y command Program mem_cmd in direct_cmd to 2 b00 which makes DRAM Controller issue Prechargeall memory command Program mem_cmd in direct_cmd to 2 b11 which makes DRAM Controller issue Autorefresh memory command Program mem_cmd in direct_cmd to 2 b11 which makes DRAM Controller issue Autorefresh memory command If memory type is mobile SDR SDRAM o Program mem_cmd to 2 b10 in direct_cmd which makes D...

Page 111: ... characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice command Program mem_cmd in direct_cmd to 2 b11 which makes DRAM Controller issue Autorefresh memory command Program mem_cmd in direct_cmd to 2 b00 which makes DRAM Controller issue Prechargeall memory command ...

Page 112: ...sive monitors 11 10 The number of exclusive access monitor resources 10 2 monitors 10 Reserved 9 Read always zero 0 Memory chips 8 7 The maximum number of different chip selects that DRAM controller can supports 11 4 chips However S3C6400X uses only two chip select signals per DRAM controller 11 Memory type 6 4 The type of SDRAM that DRAM controller supports 100 Support SDR SDRAM normal or mobile ...

Page 113: ... Undefined Write as Zero Chip number 21 20 Bits mapped to external memory chip address bits Memory command 19 18 Determine the command required 00 Prechargeall 01 Autorefresh 10 MRS or EMRS 11 NOP Bank address 17 16 Bits mapped to external memory bank address bits when command is MRS or EMRS access 15 14 Undefined Write as Zero Address_13_to_ 0 13 0 Bits mapped to external memory address bits 13 0...

Page 114: ...RID 4 1 010 ARID 5 2 011 ARID 6 3 100 ARID 7 4 101 111 Reserved 000 Memory burst 17 15 Encodes the number of data accesses that are performed to the SDRAM for each Read and Write command 000 Burst 1 001 Burst 2 010 Burst 4 011 Burst 8 100 Burst 16 101 111 Reserved This value must also be programmed into SDRAM mode register using the DIRECTCMD register and must match it 010 Stop_mem_clock 14 When e...

Page 115: ... 9 bits 010 10 bits 011 11 bits 100 12 bits 101 7 bits 110 6 bits 111 Reserved 000 REFRESH PERIOD REGISTER Register Address R W Description Reset Value P0REFRESH 0x7E000010 R W 16 bit DRAM controller refresh period register 0xA60 P1REFRESH 0x7E001010 R W 32 bit DRAM controller refresh period register 0xA60 PnREFRESH Bit Description Initial State 31 15 Read undefined Write as Zero Refresh perod 14 ...

Page 116: ...x1 P1T_DQSS 0x7E001018 R W 32 bit DRAM controller t_DQSS register 0x1 PnT_DQSS Bit Description Initial State 31 2 Read undefined Write as Zero t_DQSS 1 0 Write to DQS in memory clock cycles 1 T_MRD REGISTER Register Address R W Description Reset Value P0T_MRD 0x7E00001C R W 16 bit DRAM controller t_MRD register 0x02 P1T_MRD 0x7E00101C R W 32 bit DRAM controller t_MRD register 0x02 PnT_MRD Bit Desc...

Page 117: ...t DRAM controller t_RCD register 0x1D P1T_RCD 0x7E001028 R W 32 bit DRAM controller t_RCD register 0x1D PnT_RCD Bit Description Initial State 31 6 Read undefined Write as Zero scheduled_RCD 5 3 Set the RAS to CAS minimum delay in aclk cycles 3 011 t_RCD 2 0 Set the RAS to CAS minimum delay in memory clock cycles 101 T_RFC REGISTER Register Address R W Description Reset Value P0T_RFC 0x7E00002C R W...

Page 118: ... W 32 bit DRAM controller t_RRD register 0x2 PnT_RRD Bit Description Initial State 31 4 Read undefined Write as Zero t_RRD 3 0 Set Active bank x to Active bank y delay in memory clock cycles 0x2 T_WR REGISTER Register Address R W Description Reset Value P0T_WR 0x7E000038 R W 16 bit DRAM controller t_WR register 0x3 P1T_WR 0x7E001038 R W 32 bit DRAM controller t_WR register 0x3 PnT_WR Bit Descripti...

Page 119: ...6 bit DRAM controller t_XSR register 0x0A P1T_XSR 0x7E001044 R W 32 bit DRAM controller t_XSR register 0x0A PnT_XSR Bit Description Initial State 31 8 Read undefined Write as Zero t_XSR 7 0 Set the exit self refresh command time in memory clock cycles 0x0A T_ESR REGISTER Register Address R W Description Reset Value P0T_ESR 0x7E000048 R W 16 bit DRAM controller t_ESR register 0x14 P1T_ESR 0x7E00104...

Page 120: ... The width of the external memory 00 16 bit 01 32 bit 10 64 bit 11 128 bit 00 01 Bank bits 5 4 Encodes the number of bit of the AXI address that comprise the bank address 00 2 bits 01 1 bit 10 0 bit 11 reserved 00 Reserved 3 Read as Zero Write as Zero 0 DQM init 2 State of DQM when memory reset is de asserted 0 Clock config 1 0 The clock scheme supports 00 AXI clock and memory clock are asynchrono...

Page 121: ...R W 32 bit DRAM controller chip_ n _cfg register 0x0FF00 Pn_chip_ n _cfg Bit Description Initial State 31 17 Read undefined Write as Zero BRC_RBC 16 Selects the memory organization as decoded from the AXI address 0 Row Bank Column organization 1 Bank Row Column organization 0 Address match 15 8 Comparison value for AXI address bits 31 24 to determine which chip is selected 0xFF Address mask 7 0 Th...

Page 122: ...e without notice USER_CONFIG REGISTER Register Address R W Description Reset Value P0_user_cfg 0x7E000304 W 16 bit DRAM controller user_cfg register 0x00 P1_user_cfg 0x7E001304 W 32 bit DRAM controller user_cfg register 0x00 Pn_user_cfg Bit Description Initial State 31 8 Read undefined Write as Zero DQS 3 delay 7 6 Selects input dqs 3 delay 0 DQS 2 delay 5 4 Selects input dqs 2 delay 0 DQS 1 delay...

Page 123: ...e S3C6400 SROM Controller SROMC supports external 8 16 bit NOR Flash PROM SRAM memory From now on we refer to controller as SROM Controller S3C6400 SROM Controller supports 6 bank memory of maximum 128 MB size only FEATURE S3C6400 SROM Controller features include Supports SRAM various ROMs and NOR flash memory Supports only 8 or 16 bit data bus Address space Up to 128MB per Bank Supports 6 banks F...

Page 124: ...M SROM DECODER SFR CONTROL STATE MACHINE SROM I F SINGAL GENERATER AHB I F for SROM SFR AHB I F for SROM MEM SROM MEM I F DATA PATH Figure 6 1 SROM Controller Block Diagram SROM CONTROLLER FUNCTION DESCRIPTION SROM Controller support SROM interface for Bank0 to Bank5 In case of OneNAND boot SROM controller cannot control Bank2 and Bank3 because its mastership is on OneNAND Controller In case of NA...

Page 125: ...nge without notice nWAIT PIN OPERATION If the WAIT operation corresponding to each memory bank is enabled the nOE duration will be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 nOE will be deasserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE tRC Tacs Tcos Tacc 4 HCLK ADDR nGCS nOE nWAIT DATA R De...

Page 126: ...PROGRAMMABLE ACCESS CYCLE HCLK ADDR nGCS DATA R Tacs Tacc Tcoh Tcah ADDRESS 0 DATA 0 nOE Tcos Tacp DATA 1 ADDRESS 1 Tacs 2 cycle Tacp 2 cycle Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 6 3 SROM Controller Read Timing Block Diagram HCLK ADDR nGCS DATA W Tacs Tacc Tcoh Tcah ADDRESS nWE Tcos DATA Tacs 2 cycle Tacp don t care Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 6...

Page 127: ...idth5 20 Data bus width control for Memory Bank5 0 8 bit 1 16 bit 0 ByteEnable4 19 nWBE nBE for UB LB control for Memory Bank4 0 Not using UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is dedicated nBE 1 0 0 WaitEnable4 18 Wait enable control for Memory Bank4 0 WAIT disable 1 WAIT enable 0 Reserved 17 Reserved 0 DataWidth4 16 Data bus width control for Memory Bank4 0 8 bit 1 16 b...

Page 128: ...LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is dedicated nBE 1 0 0 WaitEnable1 6 Wait enable control for Memory Bank1 0 WAIT disable 1 WAIT enable 0 Reserved 5 Reserved 0 DataWidth1 4 Data bus width control for Memory Bank1 0 8 bit 1 16 bit 0 ByteEnable0 3 nWBE nBE for UB LB control for Memory Bank0 0 Not using UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is ded...

Page 129: ...t Description Initial State Tacs 31 28 Adress set up before nGCS 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 Tcos 27 24 Chip selection set up before nOE 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 Reserved 23 21 Reserved 000 Tacc 20 16 Access cycle...

Page 130: ...hat are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 1110 14 clocks 1111 15 clocks Reserved 3 2 Reserved PMC 1 0 Page mode configuration 00 normal 1 data 01 4 data 10 8 data 11 16 data 00 ...

Page 131: ... maximum 2 banks by using two OneNAND Controllers z Supports asynchronous synchronous muxed OneNAND memory z Supports 16 bit wide external memory data paths z Supports SINGLE INCR4 INCR8 burst transfers for 32 bit AHB data bus z Supports SINGLE Word transfers for 32 bit AHB SFR bus z Supports only ERROR OKAY response for both AHB buses z Data buffering in order to achieve maximum performance z Asy...

Page 132: ... product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM Figure 7 1 OneNAND Controller Block Diagram ...

Page 133: ...MC or OneNAND controller by System Controller SFR setting Active LOW Xm0WEn O Xm0WEn Write Enable indicates that the current bus cycle is a write cycle Active LOW Xm0OEn O Xm0OEn Output Enable indicates that the current bus cycle is a read cycle Active LOW Xm0INTsm0_FWEn Xm0INTsm1_FREn I Interrupt inputs from OneNAND memory Bank 0 1 If OneNAND memory is not used these signals must be tied to zero ...

Page 134: ...ransfers 2 Switch the clock ratio in the SFR of System Controller 3 Write to the Clock Ratio Register 4 Start the memory accesses MEMORY ADDRESS MAPPING The OneNAND Controller reads the memory device s dev_id size field to determine the address map and automatically configures the MEM_ADDR field of the address map to support the device Table 7 1 MEM_ADDR Fields defines the field sizes for several ...

Page 135: ...owever Map 00 commands are also used in read modify write operations When the read modify write command sequence is followed map 00 commands may be used to read or write any word in the buffer The memory controller will select dataram 0 or dataram 1 automatically The selection is invisible to the command requestor Table 7 2 Map 00 Address Mapping Address Bits Name Description 31 24 AHB_int_add AHB...

Page 136: ... 4 Map 10 Address Mapping Address Bits Name Description 31 24 AHB_int_add AHB Port Address 23 22 CMD_MAP 10 Initiate a special function of the flash device or read the status of the memory controller 21 0 MEM_ADDR Refer table 7 1 Erase Operation The OneNand flash controller supports single block and multi block erases Multi block erases are performed in parallel if the memory device supports this ...

Page 137: ...s controlled through the lock_bit_per_block register When using this feature if the start and end addresses specified span the entire memory then any block unlock command will be translated to an unlock all command The actual lock unlock lock tight command used is determined by the type of transaction on the AHB bus read or write and the low byte of the datain bus Address Cmd Type Datain Function ...

Page 138: ...address as the destination address for the copy Initiate a copy of PP pages from the source to destination addresses OTP and Spare Area Access Operations The OneNand flash controller supports copy operations However the memory device may have limited support for this function If the copy back function is not supported an interrupt will be triggered An interrupt will also be triggered if the source...

Page 139: ...ad ahead function utilizes a set of registers in the controller to hold the specified pages of data starting at a given address The group of reads is accessed as a continuous series of pages By pulling this data into the memory controller prior to the actual read request being issued the memory controller is able to reduce latency on returning read data to the AHB interface The pipeline write ahea...

Page 140: ... Datain Function Write 0x10 Load the page specified by the FBA FPA and FSA to the map 00 XIP buffer 23 22 10 DFS_DBS FBA FPA and FSA are used Write 0x11 Write the data in the map 00 XIP buffer to the page specified by the FBA FPA and FSA 11 Map 11 Commands Map 11 commands are used for direct memory accesses to the memory device This command type is used primarily for testing and debug of errors by...

Page 141: ...d ahead command may be followed by a pipelined write ahead command and vice versa If a current group of reads or writes is in process the memory controller will hold off the new command until that set of operations is completed The OneNAND flash memory controller may have up to three read ahead or write ahead commands pending in addition to the one being executed The controller will not return to ...

Page 142: ...Read Ahead The procedure to set up multiple areas for pipelined read ahead is as follows 1 You must set the CMD_MAP to Map 10 and set the starting address of the first block to pre read in the FBA FPA and FSA of the address 2 The command type must be set to Write and the datain bus must be driven with a value of 0x40PP where the 0 sets this command as a read ahead and PP is the number of pages to ...

Page 143: ... starting address and the desired page s These write commands must be to an address within the pre written pages You need NOT required to write all of the data or even any of the data before issuing another pipelined write ahead 4 You must set the CMD_MAP to Map 10 and set the starting address of the second block to pre write in the FBA FPA and FSA of the address 5 The command type must be set to ...

Page 144: ...t enforce any timing restrictions around the use of the reset register 2 The burst length value of OneNAND controller must be programmed with the same to or less than the burst length value of the OneNAND flash device 3 AMBA transactions must be of the same burst type throughout a page During page transfers the entire page must be transferred to memory or to the AMBA bus before the dataram buffer ...

Page 145: ...D controller starts counting FLASH_COLD_RST_DELAY with core clock 4 After ARM Core reset is de asserted Instruction fetch is started but this fetch is suspended by OneNAND controller 5 When the count value reaches to predefined FLASH_COLD_RST_DELAY value 534 ACCESS_CLK cycles OneNAND controller start reading memory dependent information A Memory dependent information consists of Manufacturer ID De...

Page 146: ... Mem dep BUF_AMOUNT0 0x701000B0 R Bank0 Amount of Buffer Register Mem dep TECH0 0x701000C0 R Bank0 Technology Register Mem dep FBA_WIDTH0 0x701000D0 R W Bank0 FBA Width Register 0x000A FPA_WIDTH0 0x701000E0 R W Bank0 FPA Width Register 0x0006 FSA_WIDTH0 0x701000F0 R W Bank0 FSA Width Register 0x0002 REVISION0 0x70100100 R Bank0 Revision Register 0x0002 DATARAM00 0x70100110 R W Bank0 Dataram0 Code ...

Page 147: ... R Bank1 Amount of Buffer Register Mem dep TECH1 0x701800C0 R Bank1 Technology Register Mem dep FBA_WIDTH1 0x701800D0 R W Bank1 FBA Width Register 0x000A FPA_WIDTH1 0x701800E0 R W Bank1 FPA Width Register 0x0006 FSA_WIDTH1 0x701800F0 R W Bank1 FSA Width Register 0x0002 REVISION1 0x70180100 R Bank1 Revision Register 0x0002 DATARAM01 0x70180110 R W Bank1 Dataram0 Code Register 0x0002 DATARAM11 0x701...

Page 148: ... and when there is no OneNAND memory access The below field description is for kfm1g16q2a Please refer to appropriate model manual Register Address R W Description Reset Value MEM_CFG0 MEM_CFG1 0x70100000 0x70180000 R W Bank0 Memory Device Configuration Register 0x00000000 MEM_CFGn Bit Description Initial State Reserved 31 16 RM 15 Sets the transfer mode for read operations as synchronous or async...

Page 149: ...0 WM 1 Sets the transfer mode for write operations as synchronous or asynchronous Default value is 0x0 Set by software during initialization 0 Asynchronous Mode 1 Activate Synchronous Mode 0 BWPS 0 Boot buffer write protected status 0 Locked 1 Unlocked 0 Note While OneNAND Controller does not obtain memory bus updating MEM_CFG is stalled and if another write access to MEM_CFG it is possible to be ...

Page 150: ...er is controlled through software 001 Warm Reset 010 Core Reset 011 Hot Reset All other settings Reserved 0 INTERRUPT ERROR STATUS REGISTER Register Address R W Description Reset Value INT_ERR_STAT0 INT_ERR_STAT1 0x70100030 0x70180030 R W Bank0 Interrupt Error Status Register 0x0000 INT_ERR_STATn Bit Description Initial State Reserved 31 14 0 CACHE_OP_ERR 13 An error occurred during a cache read o...

Page 151: ...R 0 Dual purpose interrupt bit The load operation was unsuccessful or there was an ECC error 0 Note When OneNAND Controller receives cold reset it waits until the predefined time as COLD reset wait time passes After COLD reset wait cycles it automatically generates read transactions to obtain memory dependent information from OneNAND memory After read transactions are done RST_CMP bit becomes one ...

Page 152: ... State Reserved 31 14 0 CACHE_OP_ERR 13 RST_CMP 12 RDY_ACT 11 INT_ACT 10 UNSUP_CMD 9 LOCKED_BLK 8 BLK_RW_CMP 7 ERS_CMP 6 PGM_CMP 5 LOAD_CMP 4 ERS_FAIL 3 PGM_FAIL 2 INT_TO 1 LD_FAIL_ECC_ERR 0 Acknowledge bits that correspond to the bits in the INT_ERR_STAT register Setting this bit resets or acknowledges the associated interrupt Set by software 0 ECC ERROR STATUS REGISTER Register Address R W Descr...

Page 153: ...l depend on the actual memory device being used This register is set by the flash controller after reset Read Only DEVICE ID REGISTER Register Address R W Description Reset Value DEVICE_ID0 DEVICE_ID1 0x70100080 0x70180080 R Bank0 Device ID Register Memory dependent DEVICE_IDn Bit Description Initial State Reserved 31 16 DEVICE_ID 15 9 The value programmed will depend on the actual memory device b...

Page 154: ...g used This register is set by the flash controller after reset Read Only BOOT BUFFER SIZE REGISTER Register Address R W Description Reset Value BOOT_BUF_SIZE0 BOOT_BUF_SIZE1 0x701000A0 0x701800A0 R Bank0 Boot Buffer Size Register Memory dependent BOOT_BUF_SIZEn Bit Description Initial State Reserved 31 16 BOOT_BUF 15 0 The value programmed will depend on the actual memory device being used This r...

Page 155: ...used This register is set by the flash controller after reset Read Only FBA WIDTH REGISTER Register Address R W Description Reset Value FBA_WIDTH0 FBA_WIDTH1 0x701000D0 0x701800D0 R W Bank0 FBA Width Register 0x000A FBA_WIDTHn Bit Description Initial State Reserved 31 5 0 FBA 4 0 Sets the number of bits that will be used to represent the number of blocks The default value is 0x0A Set by software d...

Page 156: ...will be used to represent the number of sectors The default value is 0x2 Set by software during initialization 0x2 REVISION REGISTER Register Address R W Description Reset Value REVISION0 REVISION1 0x70100100 0x70180100 R Bank0 Revision Register 0x00000002 REVISIONn Bit Description Initial State Reserved 31 16 0x0000 REVISION 15 0 Holds the controller revision number Default value is 0x1 Read Only...

Page 157: ...ription Reset Value SYNC_MODE0 SYNC_MODE1 0x70100130 0x70180130 R Bank0 Synchronous Mode Register 0x0000 SYNC_MODEn Bit Description Initial State Reserved 31 1 0 RM 1 Sets the transfer mode for read operations as synchronous or asynchronous Default value is 0x0 Set by software during initialization This value is copied from the MEM_CFG register 15 Read Only 0 Asynchronous Mode 1 Activate Synchrono...

Page 158: ...r data only 1 Increase sector size The main data area for the page will be transferred first and then the spare area 0 DBS DFS WIDTH REGISTER Register Address R W Description Reset Value DBS_DFS_WIDTH0 DBS_DFS_WIDTH1 0x70100160 0x70180160 R W Bank0 DBS_DFS width Register 0x0000 DBS_DFS_WIDTHn Bit Description Initial State Reserved 31 2 0 WIDTH 1 0 Sets the DBS and DFS width The default value is 0 ...

Page 159: ...Only 0 BURST READ LATENCY REGISTER Register Address R W Description Reset Value BURST_RD_LAT0 BURST_RD_LAT1 0x70100190 0x70180190 R Bank0 Burst Read Latency Register 0x0006 BURST_RD_LATn Bit Description Initial State Reserved 31 3 0 BURST_RD_LAT 2 0 Sets the burst read latency in cycles The default value is 0x6 This value is copied from the MEM_CFG register 14 12 Read Only 6 INTERRUPT PIN ENABLE R...

Page 160: ... status register This register is only used if the Flash configuration register bit IOBE is clear 500 ACCESS CLOCK REGISTER Register Address R W Description Reset Value ACC_CLOCK0 ACC_CLOCK1 0x701001C0 0x701801C0 R W Bank0 Access Clock Register 0x0003 ACC_CLOCKn Bit Description Initial State Reserved 31 3 0 ACCESS_CLK 2 0 Sets the number of cycles required to cover the access time of the Flash mem...

Page 161: ...0 Error Block Address Register 0x0000 ERR_BLK_ADDRn Bit Description Initial State Reserved 31 12 0 FAIL_BLK_ADDR 11 0 After a program load or erase error interrupt this register will hold the block address of the failing operation Read Only 0 FLASH VERSION ID REGISTER Register Address R W Description Reset Value FLASH_VER_ID0 FLASH_VER_ID1 0x701001F0 0x701801F0 R Bank0 Flash Version ID Register Me...

Page 162: ...ing hardware ECC the NAND flash data validity will be checked After the NAND flash content is copied to SDRAM main program will be executed on SDRAM To use NAND Flash XSELNAND pin must be connected to one FEATURES NAND flash controller features include 1 Auto boot The boot code is transferred into 4 KB Steppingstone during reset After the boot code is transfered boot code will be executed on the S...

Page 163: ...ntroller Block Diagram BOOT LOADER FUNCTION Stepping Stone 4KB Buffer NAND FLASH Controller NAND FLASH Memory Special Function Registers REGISTERS AUTO BOOT CORE ACCESS Boot Code USER ACCESS Figure 8 2 NAND Flash Controller Boot Loader Block Diagram During reset the NAND flash controller will get information about connected NAND flash through Pin status of XOM refer to PIN CONFIGURATION After powe...

Page 164: ...tice PIN CONFIGURATION TABLE OM 4 0 AdvFlash PageSize AddrCycle BusWidth 0000x 0 Normal NAND 1 512 byte 0 3 cycle 0 8 bit data bus 0001x 0 Normal NAND 1 512 byte 1 4 cycle 0 8 bit data bus 0010x 1 Advance NAND 1 2 Kbyte 0 4 cycle 0 8 bit data bus 0011x 1 Advance NAND 1 2 Kbyte 1 5 cycle 0 8 bit data bus Above configuration is applicable when NAND Flash is used as booting memory If NAND Flash is no...

Page 165: ...ion data and associated errata are not yet available Specifications and information herein are subject to change without notice NAND FLASH MEMORY TIMING HCLK CLE ALE nWE TACLS TWRPH0 TWRPH1 DATA COMMAND ADDRESS Figure 8 3 CLE ALE Timing TACLS 1 TWRPH0 0 TWRPH1 0 Block Diagram HCLK nWE nRE DATA DATA TWRPH0 TWRPH1 Figure 8 4 nWE nRE Timing TWRPH0 0 TWRPH1 0 Block Diagram ...

Page 166: ...memory completely The NAND Flash Controller supports direct access interface with the NAND flash memory 1 Writing to the command register the NAND Flash Memory command cycle 2 Writing to the address register the NAND Flash Memory address cycle 3 Writing to the data register write data to the NAND Flash Memory write cycle 4 Reading from the data register read data from the NAND Flash Memory read cy...

Page 167: ...rface A Word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little 4th I O 7 0 3rd I O 7 0 2nd I O 7 0 1st I O 7 0 B Half word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little Invalid value Invalid value 2nd I O 7 0 1st I O 7 0 C Byte Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little Invalid value Invalid value Invalid value 1st ...

Page 168: ...ation For MLC NAND flash memory interface NAND flash controller consists of one ECC module This can be used for only 512 bytes ECC parity code generation For 8 bit memory interface MLC ECC module generates parity code for each 512 byte However SLC ECC modules generate parity code per byte lane separately Following are the ECC parity code and two tables are SLC ECC 28bit ECC Parity Code 22bit Line ...

Page 169: ...C codes are generated by the H W ECC modules SLC ECC Register Configuration Following tables shows the configuration of SLC ECC value read from spare area of external NAND flash memory For comparing to ECC parity code generated by the H W modules the format of ECC read from memory is important NOTE MLC ECC decoding scheme is different to SLC ECC 1 8 bit NAND Flash Memory Interface Register Bit 31 ...

Page 170: ...pare area or check the bit error 8 For example to check the bit error of main data area on page read operation after generating of ECC codes for main data area you have to move the ECC parity codes is stored to spare area to NFMECCD0 and NFMECCD1 From this time the NFECCERR0 and NFECCERR1 have the valid error status values NOTE NFSECCD is for ECC in the spare area Usually the user will write the E...

Page 171: ...a data you have to read parity codes MLC ECC module needs parity codes to detect whether error bits are or not So you have to read ECC parity code right after read 512 byte Once ECC parity code is read MLC ECC engine start to search any error internally MLC ECC error searching engine need minimum 155 cycles to find any error During this time you can continue read main data from external NAND flash...

Page 172: ...28MB 128MB 128MB 128MB 128MB 128MB 2MB 4MB 8MB 16MB 32MB 64MB 128MB 2MB 4MB 8MB 16MB 32MB 64MB 128MB Refer to Table 5 1 1GB HADDR 29 0 Accessible Region SROM CF Xm0CSn 5 SROM CF Xm0CSn 4 SROM OneNAND NAND Xm0CSn 3 SROM OneNAND NAND Xm0CSn 2 SROM Xm0CSn 1 SROM Xm0CSn 0 Internal ROM Boot area OM 4 3 01 10 11 OM 4 3 00 Not using NAND flash for boot ROM Using NAND flash for boot ROM advanced normal St...

Page 173: ...t yet available Specifications and information herein are subject to change without notice NAND FLASH MEMORY CONFIGURATION Figure 8 6 A 8 bit NAND Flash Memory Interface Block Diagram Note NAND CONTROLLER can support to control two nand flash memories NAND BOOT Other BOOT Xm0CSn 2 NAND CONTROLLER CS0 Configurable Xm0CSn 3 NAND CONTROLLER CS1 Configurable If you want NAND BOOT Xm0CSn 2 must be used...

Page 174: ...R W 0xXXXXXXXX NFDATA Data register Base 0x14 R W 0x00000000 NFMECCD0 1st and 2nd main ECC data register Base 0x18 R W 0x00000000 NFMECCD1 3rd and 4th main ECC data register Base 0x1c R W 0x00000000 NFSECCD Spare ECC read register Base 0x20 R W 0x000000 NFSBLK Programmable start block address register Base 0x24 R W 0x000000 NFEBLK Programmable end block address register Base 0x28 R W 0x0080001D NF...

Page 175: ...gLength 25 Message Data length for 4 bit ECC for MLC NAND 0 512 byte for main data area 1 24 byte for meta data 0 ECCType 24 ECC type selection 0 SLC 1 bit correction ECC 1 MLC 4 bit correction ECC 0 Reserved 15 Reserved 0 TACLS 14 12 CLE ALE duration setting value 0 7 Duration HCLK x TACLS 001 Reserved 11 Reserved 0 TWRPH0 10 8 TWRPH0 duration setting value 0 7 Duration HCLK x TWRPH0 1 000 Reserv...

Page 176: ... which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 0 4 address cycle 1 5 address cycle This bit is determined by OM 1 pin status during reset and wake up from sleep mode This bit can be changed by software Reserved 0 Reserved Must be written 0 0 ...

Page 177: ...0200020 to NFEBLK 0x70200024 1 is unlocked and except this area write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occurred NFSTAT 5 bit will be set If the NFSBLK and NFEBLK are same entire area will be locked 0 Soft Lock 16 Soft Lock configuration 0 Disable lock 1 Enable lock Soft lock area can be modified at...

Page 178: ...ster is NFMECC0 1 0x70200034 38 1 SpareECCLock 6 Lock Spare area ECC generation 0 Unlock Spare ECC 1 Lock Spare ECC Spare area ECC status register is NFSECC 0x7020003C 1 InitMECC 5 1 Initialize main area ECC decoder encoder write only 0 InitSECC 4 1 Initialize spare area ECC decoder encoder write only 0 Reserved 3 Reserved HW_nCE 0 Reg_nCE1 2 NAND Flash Memory nGCS 3 signal control 0 Force nGCS 3 ...

Page 179: ... 0x00 NFCMMD Bit Description Initial State Reserved 31 8 Reserved 0x00 NFCMMD 7 0 NAND Flash memory command value 0x00 ADDRESS REGISTER Register Address R W Description Reset Value NFADDR 0x7020000C R W NAND Flash address set register 0x0000XX00 REG_ADDR Bit Description Initial State Reserved 31 8 Reserved 0x00 NFADDR 7 0 NAND Flash memory address value 0x00 DATA REGISTER Register Address R W Desc...

Page 180: ... FEATURES 0x00000000 NFMECCD0 Bit Description Initial State Reserved 31 24 Not used 0x00 ECCData1 23 16 ECC1 for I O 7 0 0x00 Reserved 15 8 Not used 0x00 ECCData0 7 0 ECC0 for I O 7 0 0x00 Note Only word access is valid NFMECCD1 Bit Description Initial State Reserved 31 24 Not used 0x00 ECCData3 23 16 ECC3 for I O 7 0 0x00 Reserved 15 8 Not used 0x00 ECCData2 7 0 ECC2 for I O 7 0 0x00 SPARE AREA E...

Page 181: ...ire area of NAND flash will be locked 0x000000 NFSBLK Bit Description Initial State Reserved 31 24 Reserved 0x00 SBLK_ADDR2 23 16 The 3rd block address of the block erase operation 0x00 SBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 SBLK_ADDR0 7 0 The 1st block address of the block erase operation Only bit 7 5 are valid 0x00 Note Advance Flash s block Address start from 3 ...

Page 182: ...Specifications and information herein are subject to change without notice The NFSLK and NFEBLK can be changed while Soft lock bit NFCONT 16 is enabled But cannot be changed when Lock tight bit NFCONT 17 is set when Lock tight 1 or SoftLock 1 NAND flash memory Locked area Read only Prorammable Readable Area Locked area Read only NFSBLK Address High Low NFEBLK NFEBLK 1 NFSBLK NFEBLK Locked Area Rea...

Page 183: ...Done 6 When 4 bit ECC decoding is finished this value set and issue interrupt if enabled The NFMLCBITPT NFMLCL0 and NFMLCEL1 have valid values To clear this write to 1 1 4 bit ECC decoding is completed 0 IllegalAccess 5 Once Soft Lock or Lock tight is enabled The illegal access program erase to the memory makes this bit set 0 illegal access is not detected 1 illegal access is detected 0 RnB_TransD...

Page 184: ...tial State Reserved 31 25 Reserved 0x00 SErrorDataNo 24 21 In spare area Indicates which number data is error 0011 SErrorBitNo 20 18 In spare area Indicates which bit is error 111 MErrorDataNo 17 7 In main data area Indicates which number data is error 0x7FF MErrorBitNo 6 4 In main data area Indicates which bit is error 111 SpareError 3 2 Indicates whether spare area bit fail error occurred 00 No ...

Page 185: ...ge data red from NAND flash has all FF value 0 MLC MECC Error 28 26 4 bit ECC decoding result 000 No error 001 1 bit error 010 2 bit error 011 3 bit error 100 4 bit error 101 Uncorrectable 11x reserved 000 2nd Bit Error Location 25 16 Error byte location of 2nd bit error 0x00 Reserved 15 10 Reserved 1st Bit Error Location 9 0 Error byte location of 1st bit error 0x00 Note These values are updated ...

Page 186: ...n Initial State Reserved 31 0 Reserved 0x00000000 Note The NAND flash controller generate NFMECC when read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock When ECCType is MLC NFMECC0 Bit Description Initial State 4th Parity 31 24 4th Check Parity generated from main area 512 byte 0x00 3rd Parity 23 16 3rd Check Parity generated from main area 512 byte 0x00 2nd Parity 15 8 2n...

Page 187: ...31 16 Reserved 0xXXXX SECC0_1 15 8 Spare area ECC1 Status for I O 7 0 0xXX SECC0_0 7 0 Spare area ECC0 Status for I O 7 0 0xXX Note The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock NFCONT 6 bit is 0 Unlock MLC 4 BIT ECC ERROR PATTEN REGISTER Register Address R W Description Reset Value NFMLCBITPT 0x70200040 R NAND Flash 4 bit ECC Error Pattern reg...

Page 188: ...rts PC card controller ATAPI controller They are multiplexing from or to PAD signals You must use only 1 mode PC card or True IDE mode Default mode is PC card mode The CF controller has a top level SFR that includes card power enable bit output port enable bit mode select True IDE or PC card bit The PC card controller features The PC card controller has 2 half word 16bits write buffers 4 half word...

Page 189: ...formation herein are subject to change without notice The ATAPI controller features The ATAPI controller is compatible with the ATA ATAPI 6 standard The ATAPI controller has 30 word sized 32bits Special Function Registers The ATAPI controller has 1 FIFO that is 16 x 32bit The ATAPI controller has internal DMA controller from ATA device to memory or from memory to ATA device AHB master DMA controll...

Page 190: ... O Register in CF card strobe PC card mode It is used for accessing register in CF card True IDE mode DMA Acknowledge Xm0OEata Xm0OEata O Output enable strobe PC card mode output enable strobe for memory True IDE mode GND Xm0RESETata Xm0RESETata O CF card reset PC card mode active high True IDE mode active low Xm0WEata Xm0WEata O Write enable strobe PC card mode output enable strobe for memory Tru...

Page 191: ...ein are subject to change without notice XmmcCMD0 XmmcCMD1 XmmcDATA1 5 XhiADR 1 XuRTSn 1 XEINT 10 XspiMOSI 0 XpcmFSYNC 0 XmmcDATA0 0 XmmcDATA1 0 XmmcDATA1 6 XhiADR 2 XuRXD 3 O XhiDATA 0 B XhiDATA 1 B XhiDATA 2 B XhiDATA 3 B XhiDATA 4 B XhiDATA 5 B XhiDATA 6 B XhiDATA 7 B XhiDATA 8 XhiDATA 16 B XhiDATA 9 XhiDATA 17 B XhiDATA 10 XhiCSn B XhiDATA 11 XhiCSn_main B XhiDATA 12 XhiCSn_sub B XhiDATA 13 Xh...

Page 192: ...ct to change without notice XhiDATA 15 XhiIRQn B Xm0CData Xm0CData I Card detect signals Xm0INTata Xm0INTata I Interrupt request from CF card PC card mode active low memory mode level triggering I O mode edge triggering True IDE mode active high XhiADR 12 Xm0WAITn XhiOEnI I Wait signal from CF card UDMA mode device strobe Xm0INPACKata Xm0INPACKata I Input acknowledge in I O mode PC card mode not u...

Page 193: ...fications and information herein are subject to change without notice BLOCK DIAGRAM TOP LEVEL BLOCK DIAGRAM A top level block diagram of the overall CF controller is shown below in Figure 9 1 Output pad enble PC card controller ATAPI controller Top level SFR Address decoder IDE mode Card power enable AHB master IF AHB slave IF HADDR CF card A H B B a c k b o r n CF controller Figure 9 1 CF Control...

Page 194: ...to change without notice PC CARD CONTROLLER BLOCK DIAGRAM A top level block diagram of the PC card controller is shown below in Figure 9 2 PC card controller Block HRDATA HWDATA ADDR nOE nWE nIORD nIOWR nREG WDATA 32 32 11 16 nCE1 nCE2 nWAIT nCD Write_dir 32 32 16 RDATA Special Function Register Main Controller Data Buffer Controller Top Controller Address decoder Address Command buffer AHB ADDR A...

Page 195: ...out notice ATAPI CONTROLLER BLOCK DIAGRAM A top level block diagram of the ATAPI controller is shown below in Figure 9 3 ATAPI interface CRC AHB Slave interface Interrupt source Control Status Register Configuration Register FIFO 32bit x 16 AHB Master interface Transfer control control interrupt Data control Data control PIO data 16 16 16 ATA write data ATA read data AHB slave IF AHB master IF ATA...

Page 196: ...ta and associated errata are not yet available Specifications and information herein are subject to change without notice TIMING DIAGRAM PC CARD MODE SET UP IDLE COMMAND HOLD IDLE nCE1 nCE2 IORD IOWR nOE nWE Figure 9 4 PC Card State Definition Area Attribute memory I O interface Common memory min Max nS Set up 30 70 30 Command 150 165 150 Hold 30 20 20 S C H 300 290 ...

Page 197: ...to change without notice TRUE IDE MODE PIO Mode PIO Mode Waveform t2 t1 teoc t1 CS0 CS1 DA 2 0 DIOR DIOW WR DD 15 0 or DD 7 0 RD DD 15 0 or DD 7 0 Figure 9 5 PIO Mode Waveform Timing Parameter In PIO Mode PIO mode PIO 0 PIO 1 PIO 2 PIO 3 PIO 4 T1 70 50 30 30 25 T2 16bit 165 125 100 80 70 T2 Register 8bit 290 290 290 80 70 TEOC 20 15 10 10 10 T1 T2 TEOC 600 383 240 180 120 Table 9 2 Timing Paramete...

Page 198: ...ires a direction control bit for data bus Two pins XhiIRQn or XirSDBW can be selected for a direction control bit These two pins are used as a control bit not only in UDMA mode but also in PC CARD mode and PIO mode CF card or micro drive can be connected directly to S3C6400 in direct mode without any extra work UDMA In Transfer termination by device CS0 CS1 DA 2 0 RD DD 15 0 or DD 7 0 DMACK DMARQ ...

Page 199: ...nd information herein are subject to change without notice UDMA Out Transfer termination by device CS0 CS1 DA 2 0 DD 15 0 or DD 7 0 DMACK DMARQ DIOW DIOR IORDY tACKENV tACKENV tACKENV tSS tDVS tDVH tACKENV tDVS tDVH Figure 9 8 UDMA Out Operation terminated by device UDMA Out Transfer termination by host CS0 CS1 DA 2 0 DD 15 0 or DD 7 0 DMACK DMARQ DIOW DIOR IORDY tACKENV tDVS tDVH Figure 9 9 UDMA ...

Page 200: ...ta are not yet available Specifications and information herein are subject to change without notice UDMA mode UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4 tACKENV 20 70 20 70 20 70 20 55 20 55 tRP 160 125 100 100 100 tSS 50 50 50 50 50 tDVS 70 48 31 20 6 7 tDVH 6 2 6 2 6 2 6 2 6 2 tDVS tDVH 120 80 60 45 30 Table 9 3 Timing Parameter Each UDMA Mode ATA_UDMA_TIME Tpara UDMA mode min max system clock 1 ...

Page 201: ...e without notice SPECIAL FUNCTION REGISTERS MEMORY MAP Memory Map Diagram HSEL_SLV_Base 0x7030_0000 SFR Area Common Memory Area I O Area Attribute Memory Area HSEL_SLV_Base 0x0000 HSEL_SLV_Base 0x0800 HSEL_SLV_Base 0x1000 SFR_Base HSEL_SLV_Base 0x1800 MUX_REG Reserved Area PC card controller SFRs Reserved Area ATAPI controlller SFRs Reserved Area SFR_Base 0x0000 SFR_Base 0x0020 SFR_Base 0x0004 SFR...

Page 202: ...ATAPI_BASE 0x70301900 ATAPI controller base address ATA_CONTROL 0x70301900 ATA enable and clock down status 0x00000002 ATA_STATUS 0x70301904 ATA status 0x00000000 ATA_COMMAND 0x70301908 ATA command 0x00000000 ATA_SWRST 0x7030190C ATA software reset 0x00000000 ATA_IRQ 0x70301910 ATA interrupt sources 0x00000000 ATA_IRQ_MASK 0x70301914 ATA interrut mask 0x0000001F ATA_CFG 0x70301918 ATA configuratio...

Page 203: ...0x00000000 ATA_PIO_CSD 0x70301970 ATA PIO device command status register 0x00000000 ATA_PIO_DAD 0x70301974 ATA PIO device control alternate status register 0x00000000 ATA_PIO_RDATA 0x7030197C ATA PIO read data from device data register 0x00000000 BUS_FIFO_STATUS 0x70301990 ATA internal AHB FIFO status 0x00000000 ATA_FIFO_STATUS 0x70301994 ATA internal ATA FIFO status 0x00000000 Table 9 4 Register ...

Page 204: ...in PC card mode 0 no reset 1 reset R W 0x0 INT_SEL 12 Card interrupt request type select 0 edge triggering 1 level triggering R W 0x0 nWAIT_EN 11 nWAIT from CF card enable 0 disable always ready 1 enable R W 0x1 DEVICE_ATT 10 Device type is 16bits or 8bits Attribute memory area 0 8bit device 1 16bit device R W 0x1 DEVICE_COMM 9 Device type is 16bits or 8bits Common memory area 0 8bit device 1 16bi...

Page 205: ..._0700 PCCARD_INTMS K SRC Bits Description R W Reset Value Reserved 31 11 Reserved bits R 0x0 INTMSK_ERR_N 10 Interrupt mask bit of no card error 0 unmask 1 mask R W 0x1 INTMSK_IREQ 9 Interrupt mask bit of CF card interrupt request 0 unmask 1 mask R W 0x1 INTMSK_CD 8 Interrupt mask bit of CF card detect 0 unmask 1 mask R W 0x1 Reserved 7 3 Reserved bits R 0x0 INTSRC_ERR_N 2 When host access no card...

Page 206: ...x03 Reserved 15 Reserved bits R 0x0 CMND_ATTR 14 8 Command state timing of attribute memory area Command time HCLK time CMND_ATTR 1 R W 0x19 Reserved 7 Reserved bits R 0x0 SETUP_ATTR 6 0 Setup state timing of attribute memory area Setup time HCLK time SETUP_ATTR 1 R W 0x09 PCCARD_I O Register Address Description Reset Value PCCARD_I O 0x7030182C PCCARD_I O is used to set the card access timing 0x0...

Page 207: ...set Value PCCARD_COMM 0x70301830 PCCARD_COMM is used to set the card access timing 0x0003_1909 PCCARD_COMM Bits Description R W Reset Value Reserved 31 23 Reserved bits R 0x0 HOLD_COMM 22 16 Hold state timing of common memory area Hold time HCLK time HOLD_COMM 1 R W 0x03 Reserved 15 Reserved bits R 0x0 CMND_COMM 14 8 Command state timing of common memory area Command time HCLK time CMND_COMM 1 R W...

Page 208: ...n This bit is asserted in idle state when ATA_CONTROL bit 0 is zero 0 not ready for clock down 1 ready for clock down R 0x1 ATA_ENABLE 0 ATA enable 0 ATA is disabled and preparation for clock down maybe in progress 1 ATA is enabled When this value is set to 1 delay of 200ms will be required R W 0x0 ATA_STATUS Register Address Description Reset Value ATA_STATUS 0x70301904 ATA controller status 0x00...

Page 209: ... available in idle state 10 command abort 11 command continue Only available in transfer pause After issuing the ABORT command make software reset by setting ATA_SWRST 0 to clear the leftover values of internal registers R W 0x0 The STOP command is used when CPU wants to pause data transfer The CPU uses STOP command to judge the transmission data is valid or not while transfer transmits To resume ...

Page 210: ... source 0x0000_0000 ATA_IRQ Bits Description R W Reset Value Reserved 31 5 Reserved bits R 0x0 SBUF_EMPTY_INT 4 When source buffer is empty CPU can clear this interrupt by writing 1 R W 0x0 TBUF_FULL_INT 3 When track buffer is half full CPU can clear this interrupt by writing 1 R W 0x0 ATADEV_IRQ_INT 2 When ATAPI device generates interrupt CPU can clear this interrupt by writing 1 R W 0x0 UDMA_HOL...

Page 211: ...Q_MASK 0x70301914 ATA interrupt mask 0x0000_001F ATA_IRQ_MASK Bits Description R W Reset Value Reserved 31 2 Reserved bits R 0x0 MASK_SBUT_EMPTY_INT 4 Interrupt mask bit of source buffer empty 0 unmask 1 mask R W 0x1 MASK_TBUF_FULL_INT 3 Interrupt mask bit of target buffer full 0 unmask 1 mask R W 0x1 MASK_ATADEV_IRQ_INT 2 Interrupt mask bit of ATA device interrupt request 0 unmask 1 mask R W 0x1 ...

Page 212: ...PTY_INT happens before setting of the second source buffer base address and size Then ATA host controller brings data from the first source buffer repeatedly To avoid this after 1st source buffer is empty the SBUF_EMPTY_MODE bit automatically changes to HIGH even though the default is 0 Therefore you must issue CONTINUE command If you don t want CPU to interfere change the next source buffer addre...

Page 213: ... R W 0x0 ATA_CLASS 3 2 ATA transfer class select 2 b00 transfer class is PIO 2 b01 transfer class is PIO DMA 2 b1x transfer class is UDMA R W 0x0 ATA_IORDY_EN 1 Determines whether IORDY input can extend data transfer 0 IORDY disable ignored 1 IORDY enable can extend R W 0x0 ATA_RST 0 ATAPI device reset by this host 0 no reset 1 reset R W 0x0 ATA_PIO_TIME Register Address Description Reset Value AT...

Page 214: ...x020b_1362 ATA_UDMA_TIME Bits Description R W Reset Value Reserved 31 28 Reserved bits R 0x0 UDMA_TDVH 27 24 UDMA timing parameter tDVH tDVH HCLK time UDMA_TDVH 1 R W 0x2 UDMA_TDVS 23 16 UDMA timing parameter tDVS It shall not have zero value tDVS HCLK time UDMA_TDVS 1 R W 0x0B UDMA_TRP 15 8 UDMA timing parameter tRP tRP HCLK time UDMA_TRP 1 R W 0x13 UDMA_TSS 7 4 UDMA timing parameter tSS tSS HCLK...

Page 215: ...000_ 0000 Reserved 0 Reserved bits R 0x0 ATA_XFR_CNT Register Address Description Reset Value ATA_XFR_CNT 0x70301938 ATA current transfer count 0x0000_0000 ATA_XFR_CNT Bits Description R W Reset Value XFR_CNT 31 1 Current remaining transfer counter This value counts down from ATA_XFR_NUM It goes to zero when pre defined all data has been transferred R 0x0000_0 000 Reserved 0 Reserved bits R 0x0 AT...

Page 216: ... 1 sector 512 byte 32 h200 you must set 32 h1FF 32 h200 1 R W 0x0000000 Reserved 4 0 Reserved bits R 0x00 ATA_SBUF_START Register Address Description Reset Value ATA_SBUF_START 0x70301944 ATA start address of source buffer 0x0000_0000 Name Bits Description R W Reset Value SRC_BUFFER_START 31 2 Start address of source buffer 4byte unit R W 0x0000_0000 Reserved 1 0 Reserved bits R 0x0 ATA_SBUF_SIZE ...

Page 217: ...UR_ADR 31 2 Current address of track buffer R 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_CADDR_SBUF Register Address Description Reset Value ATA_CADDR_SBUF 0x70301950 ATA current read address of source buffer 0x0000_0000 ATA_CADDR_SBUF Bits Description R W Reset Value SRC_BUF_CUR_ADR 31 2 Current address of source buffer R 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_PIO_DTR Register Addre...

Page 218: ...k register W 0x00 Note PIO_DEV_FED can be read by accessing register ATA_PIO_RDATA ATA_PIO_SCR Register Address Description Reset Value ATA_PIO_SCR 0x7030195C ATA PIO sector count register 0x0000_0000 ATA_PIO_SCR Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 PIO_DEV_SCR 7 0 8 bit PIO device sector count command block register W 0x00 Note PIO_DEV_SCR can be read by accessing re...

Page 219: ...middle command block register W 0x00 Note PIO_DEV_LMR can be read by accessing register ATA_PIO_RDATA ATA_PIO_LHR Register Address Description Reset Value ATA_PIO_LHR 0x70301968 ATA PIO device LBA high register 0x0000_0000 ATA_PIO_LHR Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 PIO_DEV_LHR 7 0 8 bit PIO LBA high command block register W 0x00 note PIO_DEV_LHR can be read by a...

Page 220: ...k register W 0x00 Note PIO_DEV_CSD can be read by accessing register ATA_PIO_RDATA ATA_PIO_DAD Register Address Description Reset Value ATA_PIO_DAD 0x70301974 ATA PIO device control alternate status register 0x0000_0000 ATA_PIO_DAD Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 PIO_DEV_DAD 7 0 8 bit PIO device control alternate status control block register W 0x00 Note PIO_DEV_...

Page 221: ...eration R 0x00 Reserved 15 14 Reserved bits R 0x0 BUS_FIFO_RDPNT 13 8 bus fifo read pointer R 0x00 Reserved 7 6 Reserved bits R 0x0 BUS_FIFO_WRPNT 5 0 bus fifo write pointer R 0x00 ATA_FIFO_STATUS Register Address Description Reset Value ATA_FIFO_STATUS 0x70301994 ATA internal ATA FIFO status 0x0000_0000 ATA_FIFO_STAT US Bits Description R W Reset Value Reserved 31 Reserved bit R 0x0 ATA_STATE 30 ...

Page 222: ...ort PCM I2S AC97 GPE 5 in out port PCM I2S AC97 GPF 16 in out port Camera I F PWM Clock Out GPG 7 in out port MMC channel 0 GPH 10 in out port MMC channel 1 GPI 16 in out port LCD Video Out 15 0 GPJ 12 in out port LCD Video Out 23 16 Control signals GPK 16 in out port Host I F HSI Key pad I F GPL 15 in out port Host I F Key pad I F EINT GPM 6 in out port Host I F EINT GPN 16 in out port EINT GPO 1...

Page 223: ...ON GPIO consists of two part alive part and off part In Alive part power is supplied on sleep mode but in off part it is not the same Therefore the registers in alive part can keep their values during sleep mode Register File Mux control Async Interface Alive Part APB Interface Register File Mux control Pad control Interrupt Controller Pad control APB Bus APB Bus Interrupt Controller Wake up contr...

Page 224: ... Configuration Register 0x0 GPCDAT 0x7F008044 R W Port C Data Register Undefined GPCPUD 0x7F008048 R W Port C Pull up down Register 0x00005555 GPCCONSLP 0x7F00804C R W Port C Sleep mode Configuration Register 0x0 GPCPUDSLP 0x7F008050 R W Port C Sleep mode Pull up down Register 0x0 GPDCON 0x7F008060 R W Port D Configuration Register 0x0 GPDDAT 0x7F008064 R W Port D Data Register Undefined GPDPUD 0x...

Page 225: ...R W Port I Pull up down Register 0x55555555 GPICONSLP 0x7F00810C R W Port I Sleep mode Configuration Register 0x0 GPIPUDSLP 0x7F008110 R W Port I Sleep mode Pull up down Register 0x0 GPJCON 0x7F008120 R W Port J Configuration Register 0x0 GPJDAT 0x7F008124 R W Port J Data Register Undefined GPJPUD 0x7F008128 R W Port J Pull up down Register 0x00555555 GPJCONSLP 0x7F00812C R W Port J Sleep mode Con...

Page 226: ...p down Register 0x0 GPQCONSLP 0x7F00818C R W Port Q Sleep mode Configuration Register 0x0 GPQPUDSLP 0x7F008190 R W Port Q Sleep mode Pull up down Register 0x0 SPCON 0x7F0081A0 R W Special Port Configuration Register 0x00011500 MEM0CONSLP0 0x7F0081C0 R W Memory Port 0 Sleep mode configure 0 0x0 MEM0CONSLP1 0x7F0081C4 R W Memory Port 0 Sleep mode configure 1 0x0 MEM1CONSLP 0x7F0081C8 R W Memory Port...

Page 227: ...r 0x0 EINT78FLTCON 0x7F00822C R W External Interrupt 7 8 Filter Control Register 0x0 EINT9FLTCON 0x7F008230 R W External Interrupt 9 Filter Control Register 0x0 EINT12MASK 0x7F008240 R W External Interrupt 1 2 Mask Register 0x00FF7FFF EINT34MASK 0x7F008244 R W External Interrupt 3 4 Mask Register 0x3FFF03FF EINT56MASK 0x7F008248 R W External Interrupt 5 6 Mask Register 0x03FF007F EINT78MASK 0x7F00...

Page 228: ...ption Initial State GPA0 3 0 0000 Input 0001 Output 0010 UART RXD 0 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 External Interrupt Group 1 0 0000 GPA1 7 4 0000 Input 0001 Output 0010 UART TXD 0 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 External Interrupt Group 1 1 0000 GPA2 11 8 0000 Input 0001 Output 0010 UART CTSn 0 0011 Rreserved 0100 Reserved 0101 ADDR_CF 0 ...

Page 229: ...it Description GPA 7 0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPAPUD Bit Description GPA n 2n 1 2n n 0 7 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved...

Page 230: ...3 0 0000 Input 0001 Output 0010 UART RXD 2 0011 Ext DMA Request 0100 IrDA RXD 0101 ADDR_CF 0 0110 Reserved 0111 External Interrupt Group 1 8 0000 GPB1 7 4 0000 Input 0001 Output 0010 UART TXD 2 0011 Ext DMA Ack 0100 IrDA TXD 0101 ADDR_CF 1 0110 Reserved 0111 External Interrupt Group 1 9 0000 GPB2 11 8 0000 Input 0001 Output 0010 UART RXD 3 0011 IrDA RXD 0100 Ext DMA Req 0101 ADDR_CF 2 0110 Reserve...

Page 231: ...corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPBPUD Bit Description GPB n 2n 1 2n n 0 6 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPBSLPCON Bit Description Initial State GPB n 2n 1 2n n 0 6 00 output 0 ...

Page 232: ...Reserved 0101 ADDR_CF 0 0110 Reserved 0111 External Interrupt Group 2 0 0000 GPC1 7 4 0000 Input 0001 Output 0010 SPI CLK 0 0011 reserved 0100 Reserved 0101 ADDR_CF 1 0110 Reserved 0111 External Interrupt Group 2 1 0000 GPC2 11 8 0000 Input 0001 Output 0010 SPI MOSI 0 0011 reserved 0100 Reserved 0101 ADDR_CF 2 0110 Reserved 0111 External Interrupt Group 2 2 0000 GPC3 15 12 0000 Input 0001 Output 0...

Page 233: ...corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPCPUD Bit Description GPC n 2n 1 2n n 0 7 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPCSLPCON Bit Description Initial State GPC n 2n 1 2n n 0 7 00 output 0 ...

Page 234: ...ep mode Configuration Register 0x0 GPDPUDSLP 0x7F008070 R W Port D Sleep mode Pull up down Register 0x0 GPDCON Bit Description Initial State GPD0 3 0 0000 Input 0001 Output 0010 PCM DCLK 0 0011 I2S CLK 0 0100 AC97 BITCLK 0101 ADDR_CF 0 0110 Reserved 0111 External Interrupt Group 3 0 0000 GPD1 7 4 0000 Input 0001 Output 0010 PCM EXTCLK 0 0011 I2S CDCLK 0 0100 AC97 RESETn 0101 ADDR_CF 1 0110 Reserve...

Page 235: ...corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPDPUD Bit Description GPD n 2n 1 2n n 0 4 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPDSLPCON Bit Description Initial State GPD n 2n 1 2n n 0 4 00 output 0 ...

Page 236: ...ister 0x00000155 GPECONSLP 0x7F00808C R W Port E Sleep mode Configuration Register 0x0 GPEPUDSLP 0x7F008090 R W Port E Sleep mode Pull up down Register 0x0 GPDCON Bit Description Initial State GPE0 3 0 0000 Input 0001 Output 0010 PCM DCLK 1 0011 I2S CLK 1 0100 AC97 BITCLK 0101 Reserved 0110 Reserved 0111 Reserved 0000 GPE1 7 4 0000 Input 0001 Output 0010 PCM EXTCLK 1 0011 I2S CDCLK 1 0100 AC97 RES...

Page 237: ...corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPEPUD Bit Description GPE n 2n 1 2n n 0 4 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPESLPCON Bit Description Initial State GPE n 2n 1 2n n 0 4 00 output 0 ...

Page 238: ...l Interrupt Group 4 0 00 GPF1 3 2 00 Input 01 Output 10 CAMIF HREF 11 External Interrupt Group 4 1 00 GPF2 5 4 00 Input 01 Output 10 CAMIF PCLK 11 External Interrupt Group 4 2 00 GPF3 7 6 00 Input 01 Output 10 CAMIF RSTn 11 External Interrupt Group 4 3 00 GPF4 9 8 00 Input 01 Output 10 CAMIF VSYNC 11 External Interrupt Group 4 4 00 GPF5 11 10 00 Input 01 Output 10 CAMIF YDATA 0 11 External Interru...

Page 239: ...PF 15 0 15 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPFPUD Bit Description GPF n 2n 1 2n n 0 15 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPFSLPCON Bi...

Page 240: ... Bit Description Initial State GPG0 3 0 0000 Input 0001 Output 0010 MMC CLK0 0011 reserved 0100 Reserved 0101 ADDR_CF 0 0110 Reserved 0111 External Interrupt Group 5 0 0000 GPG1 7 4 0000 Input 0001 Output 0010 MMC CMD0 0011 reserved 0100 Reserved 0101 ADDR_CF 1 0110 Reserved 0111 External Interrupt Group 5 1 0000 GPG2 11 8 0000 Input 0001 Output 0010 MMC DATA0 0 0011 reserved 0100 Reserved 0101 AD...

Page 241: ...corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPGPUD Bit Description GPG n 2n 1 2n n 0 6 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPGSLPCON Bit Description Initial State GPG n 2n 1 2n n 0 6 00 output 0 ...

Page 242: ... 0100 Key pad COL 0 0101 ADDR_CF 0 0110 Reserved 0111 External Interrupt Group 6 0 0000 GPH1 7 4 0000 Input 0001 Output 0010 MMC CMD1 0011 reserved 0100 Key pad COL 1 0101 ADDR_CF 1 0110 Reserved 0111 External Interrupt Group 6 1 0000 GPH2 11 8 0000 Input 0001 Output 0010 MMC DATA1 0 0011 reserved 0100 Key pad COL 2 0101 ADDR_CF 2 0110 Reserved 0111 External Interrupt Group 6 2 0000 GPH3 15 12 000...

Page 243: ...2 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 External Interrupt Group 6 9 0000 GPHDAT Bit Description GPH 9 0 9 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPHPUD Bit Description GPH...

Page 244: ...er 0x0 GPIPUDSLP 0x7F008110 R W Port I Sleep mode Pull up down Register 0x0 GPICON Bit Description Initial State GPI0 1 0 00 Input 01 Output 10 LCD VD 0 11 reserved 00 GPI1 3 2 00 Input 01 Output 10 LCD VD 1 11 reserved 00 GPI2 5 4 00 Input 01 Output 10 LCD VD 2 11 reserved 00 GPI3 7 6 00 Input 01 Output 10 LCD VD 3 11 reserved 00 GPI4 9 8 00 Input 01 Output 10 LCD VD 4 11 reserved 00 GPI5 11 10 0...

Page 245: ... pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPIPUD Bit Description GPI n 2n 1 2n n 0 15 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPISLPCON Bit Description Initial State GPI n 2n 1 2n n 0 15 00 output 0 01 output 1 10 input 11 Previous state 00 GPIPUDSLP Bit Description GPI n 2n 1 ...

Page 246: ...SLP 0x7F00812C R W Port J Sleep mode Configuration Register 0x0 GPJPUDSLP 0x7F008130 R W Port J Sleep mode Pull up down Register 0x0 GPJCON Bit Description Initial State GPJ0 1 0 00 Input 01 Output 10 LCD VD 16 11 reserved 00 GPJ1 3 2 00 Input 01 Output 10 LCD VD 17 11 reserved 00 GPJ2 5 4 00 Input 01 Output 10 LCD VD 18 11 reserved 00 GPJ3 7 6 00 Input 01 Output 10 LCD VD 19 11 reserved 00 GPJ4 9...

Page 247: ...rt is configured as functional pin the undefined value will be read GPJPUD Bit Description GPJ n 2n 1 2n n 0 11 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPJSLPCON Bit Description Initial State GPJ n 2n 1 2n n 0 11 00 output 0 01 output 1 10 input 11 Previous state 00 GPJPUDSLP Bit Description GPJ n 2n 1 2n n 0 11 00 pull up down disabled 01 pull down enabled 10 ...

Page 248: ... RX READY 0100 Reserved 0101 DATA_CF 0 0110 Reserved 0111 Reserved 0010 GPK1 7 4 0000 Input 0001 Output 0010 Host I F DATA 1 0011 HSI RX WAKE 0100 Reserved 0101 DATA_CF 1 0110 Reserved 0111 Reserved 0010 GPK2 11 8 0000 Input 0001 Output 0010 Host I F DATA 2 0011 HSI RX FLAG 0100 Reserved 0101 DATA_CF 2 0110 Reserved 0111 Reserved 0010 GPK3 15 12 0000 Input 0001 Output 0010 Host I F DATA 3 0011 HSI...

Page 249: ...0001 Output 0010 Host I F DATA 10 0011 Key pad ROW 2 0100 Reserved 0101 DATA_CF 10 0110 Reserved 0111 Reserved 0010 GPK11 15 12 0000 Input 0001 Output 0010 Host I F DATA 11 0011 Key pad ROW 3 0100 Reserved 0101 DATA_CF 11 0110 Reserved 0111 Reserved 0010 GPK12 19 16 0000 Input 0001 Output 0010 Host I F DATA 12 0011 Key pad ROW 4 0100 Reserved 0101 DATA_CF 12 0110 Reserved 0111 Reserved 0010 GPK13 ...

Page 250: ...re subject to change without notice GPKDAT Bit Description GPK 15 0 15 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPKPUD Bit Description GPK n 2n 1 2n n 0 15 00 pull up down disabled 01 p...

Page 251: ...erved 0110 ADDR_CF 0 0111 OTG ULPI DATA 0 0010 GPL1 7 4 0000 Input 0001 Output 0010 Host I F ADDR 1 0011 Key pad COL 1 0100 Reserved 0101 Reserved 0110 ADDR_CF 1 0111 OTG ULPI DATA 1 0010 GPL2 11 8 0000 Input 0001 Output 0010 Host I F ADDR 2 0011 Key pad COL 2 0100 Reserved 0101 Reserved 0110 ADDR_CF 2 0111 OTG ULPI DATA 2 0010 GPL3 15 612 0000 Input 0001 Output 0010 Host I F ADDR 3 0011 Key pad C...

Page 252: ... CE_CF 1 0110 Reserved 0111 OTG ULPI CLK 0010 GPL10 11 8 0000 Input 0001 Output 0010 Host I F ADDR 10 0011 Ext Interrupt 18 0100 Reserved 0101 IORD_CF 0110 Reserved 0111 OTG ULPI NXT 0010 GPL11 15 12 0000 Input 0001 Output 0010 Host I F ADDR 11 0011 Ext Interrupt 19 0100 Reserved 0101 IOWR_CF 0110 Reserved 0111 OTG ULPI DIR 0010 GPL12 19 16 0000 Input 0001 Output 0010 Host I F ADDR 12 0011 Ext Int...

Page 253: ...re subject to change without notice GPLDAT Bit Description GPL 14 0 14 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPLPUD Bit Description GPL n 2n 1 2n n 0 14 00 pull up down disabled 01 p...

Page 254: ...rved 0010 GPM1 7 4 0000 Input 0001 Output 0010 Host I F CSn_main 0011 Ext Interrupt 24 0100 Reserved 0101 DATA_CF 11 0110 CE_CF 1 0111 Reserved 0010 GPM2 11 8 0000 Input 0001 Output 0010 Host I F CSn_sub 0011 Ext Interrupt 25 0100 Host I F MDP_VSYNC 0101 DATA_CF 12 0110 IORD_CF 0111 Reserved 0010 GPM3 15 12 0000 Input 0001 Output 0010 Host I F WEn 0011 Ext Interrupt 26 0100 Reserved 0101 DATA_CF 1...

Page 255: ...s that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice GPLPUD Bit Description GPM n 2n 1 2n n 0 5 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved ...

Page 256: ...nterrupt 1 11 Key pad ROW 1 00 GPN2 5 4 00 Input 01 Output 10 Ext Interrupt 2 11 Key pad ROW 2 00 GPN3 7 6 00 Input 01 Output 10 Ext Interrupt 3 11 Key pad ROW 3 00 GPN4 9 8 00 Input 01 Output 10 Ext Interrupt 4 11 Key pad ROW 4 00 GPN5 11 10 00 Input 01 Output 10 Ext Interrupt 5 11 Key pad ROW 5 00 GPN6 13 12 00 Input 01 Output 10 Ext Interrupt 6 11 Key pad ROW 6 00 GPN7 15 14 00 Input 01 Output ...

Page 257: ...re subject to change without notice GPNDAT Bit Description GPN 15 0 15 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPNPUD Bit Description GPN n 2n 1 2n n 0 15 00 pull up down disabled 01 p...

Page 258: ... 0 00 Input 01 Output 10 MEM0_nCS 2 11 Ext Interrupt Group7 0 10 GPO1 3 2 00 Input 01 Output 10 MEM0_nCS 3 11 Ext Interrupt Group7 1 10 GPO2 5 4 00 Input 01 Output 10 MEM0_nCS 4 11 Ext Interrupt Group7 2 10 GPO3 7 6 00 Input 01 Output 10 MEM0_nCS 5 11 Ext Interrupt Group7 3 10 GPO4 9 8 00 Input 01 Output 10 MEM0_nCS 6 11 Ext Interrupt Group7 4 10 GPO5 11 10 00 Input 01 Output 10 MEM0_nCS 7 11 Ext ...

Page 259: ...en the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPOPUD Bit Description GPO n 2n 1 2n n 0 15 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPOCONSLP Bit Description Initial State GPO n 2n 1 2n n 0 15 00 output 0 01 output 1 10 input 11 Previuos st...

Page 260: ...00 Input 01 Output 10 MEM0_ADDRV 11 Ext Interrupt Group8 0 10 GPP1 3 2 00 Input 01 Output 10 MEM0_SMCLK 11 Ext Interrupt Group8 1 10 GPP2 5 4 00 Input 01 Output 10 MEM0_nWAIT 11 Ext Interrupt Group8 2 10 GPP3 7 6 00 Input 01 Output 10 MEM0_RDY0_ALE 11 Ext Interrupt Group8 3 10 GPP4 9 8 00 Input 01 Output 10 MEM0_RDY1_CLE 11 Ext Interrupt Group8 4 10 GPP5 11 10 00 Input 01 Output 10 MEM0_INTsm0_FWE...

Page 261: ...e When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPPPUD Bit Description GPP n 2n 1 2n n 0 14 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved GPPCONSLP Bit Description Initial State GPP n 2n 1 2n n 0 14 00 output 0 01 output 1 10 input 11 Previuo...

Page 262: ...er 0x0 GPQCON Bit Description Initial State GPQ0 1 0 00 Input 01 Output 10 MEM0_RAS 11 Ext Interrupt Group9 0 10 GPQ1 3 2 00 Input 01 Output 10 MEM0_CAS 11 Ext Interrupt Group9 1 10 GPQ2 5 4 00 Input 01 Output 10 MEM0_SCLK 11 Ext Interrupt Group9 2 10 GPQ3 7 6 00 Input 01 Output 10 MEM0_SCLKn 11 Ext Interrupt Group9 3 10 GPQ4 9 8 00 Input 01 Output 10 MEM0_SCKE 11 Ext Interrupt Group9 4 10 GPQ5 11...

Page 263: ...PQCONSLP Bit Description Initial State GPQ n 2n 1 2n n 0 8 00 output 0 01 output 1 10 input 11 Previuos state 00 GPQPUDSLP Bit Description GPQ n 2n 1 2n n 0 8 00 pull up down disabled 01 pull down enabled 10 pull up enabled 11 Reserved Note 1 When the ports are set to memory interface signals their states are controlled by MEM0CONSTOP in stop mode MEM0CONSLP0 in sleep mode 2 When the ports GPQ 4 0...

Page 264: ...up 11 Do not use 00 MEM1_D_PUD0 13 12 Memory Port 1 Data pin 15 0 pull up down control 00 disabled 01 pull down 10 pull up 11 Do not use 01 MEM0_DQS_PUD 11 10 Memory Port 0 DQS pin pull up down control 00 disabled 01 pull down 10 pull up 11 Do not use 01 MEM0_D_PUD 9 8 Memory Port 0 ROM bank Data pin pull up down control 00 disabled 01 pull down 10 pull up 11 Do not use 01 USB_DMPD 7 USB DM Pull d...

Page 265: ...S_VD 6 0 XvRGBVD 6 0 XvVD 13 7 XvSYS_VD 13 7 XvRGBVD 13 7 XvVD 15 14 XvSYS_VD 15 14 XvRGBVD 15 14 XvVD 17 16 XvSYS_VD 17 16 XvRGBVD 17 16 XvVD 20 18 XvRGBVD 20 18 XvVD 21 XvRGBVD 21 XvVD 22 XvSYS_VSYNC_ldi XvRGBVD 22 XvVD 23 XvSYS_OEn XvRGBVD 23 XvHSYNC XvSYS_CSn_main XvHSYNC XvVSYNC XvSYS_CSn_sub XvVSYNC XvVDEN XvSYS_RS XvVDEN XvVCLK XvSYS_WEn XvVCLK Reserved Reserved USB 1 0 Tranceiver XusbDP Xu...

Page 266: ...e GPIO Off part LCD Mux Bypass Mux GPIO alive part Modem I F Alive part LCD Controller CPU I F RGB Bypass Mux SEL_BYPASS MIFPCON 3 GPICONSLP GPJCONSLP LCD_SEL 1 0 SPCON 1 0 Port Mux I J port LCD I F PAD off interface Alive interface HOST I F PAD off interface Alive interface Port Mux K L M port GPICON GPJCON GPKCON GPLCON GPMCON Modem I F Off part Port Mux Alive K L M port GPKCON GPLCON GPMCON Oth...

Page 267: ... MEM0_FREn 25 Memor port 0 FREn pin Xm0FREn Configure 0 Previous state 1 Hi Z 0 MEM0_FWEn 24 Memor port 0 FWEn pin Xm0FWEn Configure 0 Previous state 1 Hi Z 0 MEM0_CLE 23 Memor port 0 CLE pin Xm0CLE Configure 0 Previous state 1 Hi Z 0 MEM0_ALE 22 Memor port 0 ALE pin Xm0ALE Configure 0 Previous state 1 Hi Z 0 MEM0_OEn 21 Memory port 0 Output Enable pin Xm0OEn Configure 0 Previous state 1 Hi Z MEM0...

Page 268: ... herein are subject to change without notice MEM0_CSn 12 Memory port 0 Chip Select pin Xm0CSn Configure 0 Previous state 1 Hi Z 0 Reserved 11 7 Reserved 00 MEM0_nWEdmc 6 Memory port 0 Dram Write Enable pin Xm0nWEdmc Configure 0 Previous state 1 Hi Z 0 MEM0_AP 5 Memory port 0 AP pin Xm0AP Configure 0 Previous state 1 Hi Z 0 MEM0_SMCLK 4 Memory port 0 SSMC Clock pin Xm0SMCLK Configure 0 Previous sta...

Page 269: ...mory port 1 SCLK pin Xm1SCLK Configure 0 Previous state 1 Hi Z 0 MEM1_CKE 18 Memory port 1 CKE pin Xm1CKE Configure 0 Previous state 1 Hi Z 0 MEM1_DQM 17 Memory port 1 DQM pin Xm1DQM Configure 0 Previous state 1 Hi Z 0 MEM1_A 16 Memory port 1 Address pin Xm1ADDR Configure 0 Previous state 1 Hi Z 0 MEM1_CASn 15 Memory port 1 CAS pin Xm1CASn Configure 0 Previous state 1 Hi Z 0 MEM1_RASn 14 Memory po...

Page 270: ...LK pin Xs0SCLK Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM0_CKE 25 24 Memory port 0 CKE pin Xs0CKE Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM0_DQM 23 22 Memory port 0 DQM pin Xs0DQM Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM0_A 21 20 Memory port0 Address pin Xs0ADDR Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM0_CASn 1...

Page 271: ...ed 0 MEM0_nOEata 25 24 ATA I F Output Enable pin Xm0nOEata Configure 00 output 0 01 output 1 1x input pull up 0 MEM0_nWEata 23 22 ATA I F Write enable pin Xm0nWEata Configure 00 output 0 01 output 1 1x input pull up 0 MEM0_SMCLK 21 20 ROM bank Clock pin Xm0SMCLK Configure 00 output 0 01 output 1 1x input pull up 0 MEM0_WAIT 19 18 ROM bank Wait pin XrWAITn Configure 00 output 0 01 output 1 1x input...

Page 272: ...9 28 Memory port 1 SCLKn pin Xm1SCLKn Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM1_SCLK 27 26 Memory port 1 SCLK pin Xm1SCLK Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM1_CKE 25 24 Memory port 1 CKE pin Xm1CKE Configure 00 output 0 01 output 1 1x output disable hi Z 00 MEM1_DQM 23 22 Memory port 1 DQM pin Xm1DQM Configure 00 output 0 01 output 1 1x output dis...

Page 273: ...1 0100 input hi Z 0101 input pull down enable 0110 inupt pull up enable 0111 do not use 10xx Previous state MEM1_D1 7 4 Memory Port 1 Data pin 31 16 Xm1DATA 31 16 Configure 0000 output 0 0001 output 1 0100 input hi Z 0101 input pull down enable 0110 inupt pull up enable 0111 do not use 10xx Previous state 00 MEM1_D0 3 0 Memory Port 1 Data pin 15 0 Xm1DATA 15 0 Configure 0000 output 0 0001 output 1...

Page 274: ...M0_ALE_CLE 25 24 Memory port 0 CLE ALE pin Xm0CLE Xm0ALE Configure 00 MEM0_SCLKn 23 22 Memory port 0 SCLKn pin Xm0SCLKn Configure 00 MEM0_DQS 21 20 Memory port 0 DQS pin Xm0DQS Configure 00 MEM0_CKE 19 18 Memory port 0 CKE pin Xm0CKE Configure 00 MEM0_SCLK 17 16 Memory port 0 SCLK pin Xm0SCLK Configure 00 MEM0_A 15 14 Memory port0 Address pin Xm0ADDR Configure 00 MEM0_DQM 13 12 Memory port 0 DQM p...

Page 275: ... MEM1_SCLK 17 16 Memory port 1 SCLK pin Xm1SCLK Configure 00 MEM1_A 15 14 Memory port 1 Address pin Xm1ADDR Configure 00 MEM1_DQM 13 12 Memory port 1 DQM pin Xm1DQM Configure 00 MEM1_WEn 11 10 Memory port 1 Write Enable pin Xm1WEn Configure 00 MEM1_RASn_CAS n 9 8 Memory port 1 RAS CAS pin Xm1RASn Xm1CASn Configure 00 MEM1_CSn1 7 6 Memory port 1 Chip Select pin Xm1CSn 1 Configure 00 MEM1_CSn0 5 4 M...

Page 276: ...T0FLTCON3 0x7F00891C R W External Interrupt 0 Filter Control Register 3 0x0 EINT0MASK 0x7F008920 R W External Interrupt 0 Mask Register 0x0FFFFFFF EINT0PEND 0x7F008924 R W External Interrupt 0 Pending Register 0x0 EINT12CON 0x7F008200 R W External Interrupt 1 2 Configuration Register 0x0 EINT34CON 0x7F008204 R W External Interrupt 3 4 Configuration Register 0x0 EINT56CON 0x7F008208 R W External In...

Page 277: ...ta and associated errata are not yet available Specifications and information herein are subject to change without notice EINT9PEND 0x7F008270 R W External Interrupt 9 Pending Register 0x0 PRIORITY 0x7F008280 R W Priority Control Register 0x3FF SERVICE 0x7F008284 R Current Service Register 0x00 SERVICEPEND 0x7F008288 R W Current Service Pending Register 0x00 ...

Page 278: ...ng edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 19 Reserved 0 EINT9 8 18 16 Setting the signaling method of the EINT9 and EINT8 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 15 Reserved 0 EINT7 6 14 12 Setting the signaling method of the EINT7 and EINT6 000 Low level 001 High level 01x Falling...

Page 279: ...0 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 11 Reserved 0 EINT21 20 10 8 Setting the signaling method of the EINT21 and EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 7 Reserved 0 EINT19 18 6 4 Setting the signaling method of the EINT19 and EINT18 ...

Page 280: ...ltering width of EINT0 1 This value is valid when FLTSEL is 1 000 EINT0FLTCON1 Bit Description Initial State FLTEN 31 Filter Enable EINT14 15 0 disables 1 enabled 0 FLTSEL 30 Filter Selection for EINT 14 15 0 delay filter 1 digital filter clock count 0 EINT14 15 29 24 Filtering width of EINT14 15 This value is valid when FLTSEL is 1 000 FLTEN 23 Filter Enable for EINT 12 13 0 disables 1 enabled 0 ...

Page 281: ...LTSEL is 1 000 FLTEN 15 Filter Enable for EINT18 19 0 disables 1 enabled 0 FLTSEL 14 Filter Selection for EINT18 19 0 delay filter 1 digital filter clock count 0 EINT18 19 13 8 Filtering width of EINT18 19 This value is valid when FLTSEL is 1 000 FLTEN 7 Filter Enable for EINT16 17 0 disables 1 enabled 0 FLTSEL 6 Filter Selection for EINT16 17 0 delay filter 1 digital filter clock count 0 EINT16 1...

Page 282: ...0 0 Enable Interrupt 1 Masked 1 EINT19 19 0 Enable Interrupt 1 Masked 1 EINT18 18 0 Enable Interrupt 1 Masked 1 EINT17 17 0 Enable Interrupt 1 Masked 1 EINT16 16 0 Enable Interrupt 1 Masked 1 EINT15 15 0 Enable Interrupt 1 Masked 1 EINT14 14 0 Enable Interrupt 1 Masked 1 EINT13 13 0 Enable Interrupt 1 Masked 1 EINT12 12 0 Enable Interrupt 1 Masked 1 EINT11 11 0 Enable Interrupt 1 Masked 1 EINT10 1...

Page 283: ... EINT19 19 0 Not occur 1 Occur interrupt 0 EINT18 18 0 Not occur 1 Occur interrupt 0 EINT17 17 0 Not occur 1 Occur interrupt 0 EINT16 16 0 Not occur 1 Occur interrupt 0 EINT15 15 0 Not occur 1 Occur interrupt 0 EINT14 14 0 Not occur 1 Occur interrupt 0 EINT13 13 0 Not occur 1 Occur interrupt 0 EINT12 12 0 Not occur 1 Occur interrupt 0 EINT11 11 0 Not occur 1 Occur interrupt 0 EINT10 10 0 Not occur...

Page 284: ...edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 15 Reserved 0 EINT1 14 12 14 12 Setting the signaling method of the EINT1 14 12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 11 Reserved 0 EINT1 11 8 10 8 Setting the signaling method of the EINT1 11 8 000 Low level 001 High level 01x Falling edge ...

Page 285: ...ggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 23 Reserved 0 EINT4 7 4 22 20 Setting the signaling method of the EINT4 7 4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 19 Reserved 0 EINT4 3 0 18 16 Setting the signaling method of the EINT4 3 0 000 Low level 001 High level 01x Falling edge triggered 10x...

Page 286: ... 7 4 22 20 Setting the signaling method of the EINT6 7 4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 19 Reserved 0 EINT6 3 0 18 16 Setting the signaling method of the EINT6 3 0 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 15 7 Reserved 0 EINT5 6 4 6 4...

Page 287: ... edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 19 Reserved 0 EINT8 3 0 18 16 Setting the signaling method of the EINT8 3 0 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 15 Reserved 0 EINT7 15 12 14 12 Setting the signaling method of the EINT7 15 12 000 Low level 001 High level 01x Falling edge ...

Page 288: ...to change without notice EINT9CON Bit Description Initial State Reserved 31 7 Reserved 0x000000 EINT9 8 4 6 4 Setting the signaling method of the EINT9 8 4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 Reserved 3 Reserved 0 EINT9 3 0 2 0 Setting the signaling method of the EINT9 3 0 000 Low level 001 High level 01x Falling edge trigge...

Page 289: ... EINT2 7 0 000 FLTEN1 14 8 15 Filter Enable for EINT1 14 8 0 disables 1 enabled 0 EINT1 14 8 14 8 Filtering width of EINT1 14 8 000 FLTEN1 7 0 7 Filter Enable for EINT1 7 0 0 disables 1 enabled 0 EINT1 7 0 6 0 Filtering width of EINT1 7 0 000 EINT34FLTCON Bit Description Initial State FLTEN4 13 8 31 Filter Enable for EINT2 12 8 0 disables 1 enabled 0 EINT4 13 8 30 24 Filtering width of EINT2 12 8 ...

Page 290: ... 6 0 7 Filter Enable for EINT5 6 0 0 disables 1 enabled 0 EINT5 6 0 6 0 Filtering width of EINT5 6 0 000 EINT78FLTCON Bit Description Initial State FLTEN8 15 8 31 Filter Enable for EINT8 15 8 0 disables 1 enabled 0 EINT8 15 8 30 24 Filtering width of EINT8 15 8 000 FLTEN8 7 0 23 Filter Enable for EINT8 7 0 0 disables 1 enabled 0 EINT8 7 0 22 16 Filtering width of EINT8 7 0 000 FLTEN7 15 8 15 Filte...

Page 291: ...e Interrupt 1 Masked 1 EINT34MASK Bit Description Initial State Reserved 31 30 Reserved 0 EINT4 m 16 m m 0 13 0 Enable Interrupt 1 Masked 1 Reserved 15 5 Reserved 0 EINT3 n n n 0 4 0 Enable Interrupt 1 Masked 1 EINT56MASK Bit Description Initial State Reserved 31 26 Reserved 0 EINT6 m 16 m m 0 9 0 Enable Interrupt 1 Masked 1 Reserved 15 7 Reserved 0 EINT5 n n n 0 6 0 Enable Interrupt 1 Masked 1 EI...

Page 292: ...Occur interrupt 0 EINT34PEND Bit Description Initial State Reserved 31 30 Reserved 0 EINT4 m 16 m m 0 13 0 Not occur 1 Occur interrupt 0 Reserved 15 5 Reserved 0 EINT3 n n n 0 4 0 Not occur 1 Occur interrupt 0 EINT56PEND Bit Description Initial State Reserved 31 26 Reserved 0 EINT6 m 16 m m 0 9 0 Not occur 1 Occur interrupt 0 Reserved 15 7 Reserved 0 EINT5 n n n 0 6 0 Not occur 1 Occur interrupt 0...

Page 293: ...le 1 ARB7 7 External Interrupt Group 7 priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB6 6 External Interrupt Group 6 priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB5 5 External Interrupt Group 5 priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB4 4 External Interrupt Group 4 priority rotate enable 0 Pri...

Page 294: ...n data and associated errata are not yet available Specifications and information herein are subject to change without notice ARBITER0 ARBITER1 Interrupt EINT1 14 0 ARBITER2 EINT2 7 0 ARBITER3 EINT3 4 0 ARBITER4 EINT4 13 0 ARBITER5 EINT5 6 0 ARBITER6 EINT6 9 0 ARBITER7 EINT7 15 0 ARBITER8 EINT8 14 0 ARBITER9 EINT9 8 0 Figure 10 ４ Priority Generating Block ...

Page 295: ...sents which interrupt pending bit must be cleared Only 1 bit is set 1 corresponding to Current Service Register After complete interrupt service routine you can clear the interrupt pending bit in Interrupt Pending Registers by write the value contained in this register For example if the group field of Current Service Register is 4 you can clear the corresponding interrupt pending bit by writing t...

Page 296: ...ode 0 Disable 1 Pull Down Enable 0 RSTOUT 13 12 Reset Out pin XnRSTOUT Configure 00 output 0 01 output 1 1x output disable hi Z 00 Reserved 11 5 Reserved 00 CKE0_INIT 4 Initial value for Memory port 0 CK This value is valid only when system is in reset state of power on or sleep wakeup 1 Reserved 3 2 Reserved 00 KP_COL 1 0 Key Pad Column bit Configure 00 output 0 01 output 1 1x input 00 SLPEN Bit ...

Page 297: ...on is available in the SPINE bus 4 Both source and destination are available in the PERIPHERAL bus ARM PrimeCell DMA controller PL080 is used as S3C6400 DMA controller The DMAC is an Advanced Microcontroller Bus Architecture AMBA compliant System on Chip SoC peripheral that is developed tested and licensed by ARM Limited The DMAC is an AMBA AHB module and connects to the Advanced High performance ...

Page 298: ...ss for source and destination z Programmable DMA burst size The DMA burst size can be programmed to increase efficiency of transfer data Usually the burst size is set to half the size of the FIFO in the peripheral z Internal four word FIFO per channel z Supports 8 16 and 32 bit wide transactions z Big endian and little endian support The DMA controller defaults to little endian mode on reset z Sep...

Page 299: ...product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM Figure 11 1 DMAC block diagram ...

Page 300: ...0 SDMA0 6 DMA_UART3 0 UART3 DMA source 0 DMA0 SDMA0 7 DMA_UART3 1 UART3 DMA source 1 DMA0 SDMA0 8 DMA_PCM0_TX PCM0 DMA TX source DMA0 SDMA0 9 DMA_PCM0_RX PCM0 DMA RX source DMA0 SDMA0 10 DMA_I2S0_TX I2S0 TX DMA source DMA0 SDMA0 11 DMA_I2S0_RX I2S0 RX DMA source DMA0 SDMA0 12 DMA_SPI0_TX SPI0 TX DMA source DMA0 SDMA0 13 DMA_SPI0_RX SPI0 RX DMA source DMA0 SDMA0 14 DMA_HSI_TX MIPI HSI DMA TX source...

Page 301: ...sociated errata are not yet available Specifications and information herein are subject to change without notice DMA1 SDMA1 9 DMA_PWM PWM DMA source DMA1 SDMA1 10 DMA_IrDA IrDA DMA source DMA1 SDMA1 11 DMA_EXTERNAL External DMA source DMA1 SDMA1 12 Reserved DMA1 SDMA1 13 Reserved SDMA1 14 DMA_SECU_RX Security RX DMA source SDMA1 15 DMA_SECU_TX Security TX DMA source ...

Page 302: ...not mandatory to connect the single transfer request signal If a peripheral transfer only single word of data it is not mandatory to connect the burst request signal DMA response signals The DMA response signals indicate whether the transfer initiated by the DMA request signal is complete The response signals can also be used to indicate whether a complete packet has been transferred The DMA respo...

Page 303: ...on under DMA controller flow control For transactions that are not a multiple of the burst size use only the burst request signal as shown in Figure 11 3 The DMAC works out the amount of data to transfer based on the transfer size DMA controller Peripheral DMACBREQ DMACCLR Figure 11 3 Memory to Peripheral transaction comprising bursts that are not multiples of the burst size Only DMACBREQ is requi...

Page 304: ...s shown in Figure 11 4 Source peripheral Destination peripheral DMA controller DMACBREQ DMACSREQ DMACCLR DMACBREQ DMACCLR AMBA bus Figure 11 5 Peripheral to peripheral transaction comprising bursts and single requests The source peripheral follows the same procedure as described in Peripheral to memory transaction under DMA controller flow control The destination peripheral follows the same proced...

Page 305: ...he peripheral which is ready to proceed with a DMA transfer of the indicated size Active HIGH Sampled by the DMA controller on the positive edge of HCLK The DMA request signals are used in conjunction with the DMACCLR signal to perform handshaking DMA Acknowledge or Clear DMACCLRx Indicates to the slave that a DMA transfer is completed Active HIGH DMA Terminal Count DMACTCx Indicates to the slave ...

Page 306: ...ce timing PROGRAMMER S MODEL Programming the DMA controller All transactions on the AHB Slave programming bus must be 32 bit wide This eliminates endian issues when programming the DMA controller Enabling the DMA controller To enable the DMA controller set the DMA Enable bit in the DMACConfiguration register Disabling the DMA controller To disable the DMA controller take the following steps 1 Read...

Page 307: ...el which has to be transferred 3 Clear the Channel Enable bit in the relevant channel configuration register Set up a new DMA transfer Steps to set up a new DMA transfer 1 If the channel is not set aside for the DMA transaction a Read the DMACEnbldChns controller register and find out which channels are inactive b Select an inactive channel which has the required priority 2 Program the DMA control...

Page 308: ... LLI address Source Address for next transfer Next LLI address 0x04 Destination Address for next transfer Next LLI address 0x08 Next LLI address for next transfer Next LLI address 0x0C DMACCxControl0 data for next transfer Next LLI address 0x10 DMACCxControl1 data for next transfer 7 Write the control information into the DMACCxControl register 8 Write the channel configuration information into th...

Page 309: ...hat the transaction is completed 0x004 0x00 DMACIntTCClear W 8 When writing to this register each data bit that is HIGH causes the corresponding bit in the DMACIntTCStatus and DMACRawIntTCStatus registers to be cleared Data bits that are LOW have no effect on the corresponding bit in the register 0x008 DMACIntErrorStatus R 8 This register is used to determine whether an interrupt was generated due...

Page 310: ...R W 32 DMA channel 0 control0 0x10C 0x00000000 DMACC0Control1 R W 32 DMA channel 0 control1 0x110 0x00000000 DMACC0Configuration R W 19 DMA channel 0 configuration register 0x114 0x00000 DMACC1SrcAddr R W 32 DMA channel 1 source address 0x120 0x00000000 DMACC1DestAddr R W 32 DMA channel 1 destination address 0x124 0x00000000 DMACC1LLI R W 32 DMA channel 1 linked list address 0x128 0x00000000 DMACC...

Page 311: ...x1A4 0x00000000 DMACC5LLI R W 32 DMA channel 5 linked list address 0x1A8 0x00000000 DMACC5Control0 R W 32 DMA channel 5 control0 0x1AC 0x00000000 DMACC5Control1 R W 32 DMA channel 5 control1 0x1B0 0x00000000 DMACC5Configuration R W 19 DMA channel 5 configuration register 0x1B4 0x00000 DMACC6SrcAddr R W 32 DMA channel 6 source address 0x1C0 0x00000000 DMACC6DestAddr R W 32 DMA channel 6 destination...

Page 312: ...tus of the terminal count after masking This register must be used in conjunction with the DMACIntStatus register if the combined interrupt request DMACINTCOMBINE is used to request interrupts If the DMACINTTC interrupt request is used then you only have to read the DMACIntTCStatus register to ascertain the source of the interrupt request Table 11 3 shows the bit assignment of the DMACIntTCStatus ...

Page 313: ...or status Interrupt error clear register DMACIntErrClr The DMACIntErrClr register is a write only register and is used to clear the error interrupt requests When writing to this register each data bit that is HIGH causes the corresponding bit in the status register to be cleared Data bits that are LOW have no effect on the corresponding bit in the register Table 11 6 shows the bit assignment of th...

Page 314: ...y the Enable bit in the DMACCxConfiguration register A HIGH bit indicates that a DMA channel is enabled A bit is cleared on completion of the DMA transfer Table 11 9 shows the bit assignment of the DMACEnbldChns register Table 11 9 Bit Assignment of DMACEnbldChns register DMACEnbldChns Bits Type Function EnabledChannels 7 0 R Channel enable status Software burst request register DMACSoftBReq The D...

Page 315: ...register allows DMA last burst requests to be generated by software A DMA request can be generated for each source by writing a 1 to the corresponding register bit A register bit is cleared when the transaction is complete Writing 0 to this register has no effect Reading the register indicates which sources are requesting last burst DMA transfers A request can be generated from either a peripheral...

Page 316: ...W DMA controller enable 0 disabled 1 enabled This bit is reset to 0 Disabling the DMA controller reduces power consumption Note It is not mandatory for AHB master interfaces to have the same endianness Synchronization register DMACSync The DMACSync read write register is used to enable or disable synchronization logic for the DMA request signals The DMA request signals consist of the DMACBREQ 15 0...

Page 317: ...has stopped in which case it shows the source address of the last item read Note The source and destination addresses must be aligned to the source and destination widths Table 11 16 shows the bit assignment of the DMACCxSrcAddr registers Table 11 16 Bit Assignment of DMACCxSrcAddr register DMACCxSrcAddr Bits Type Function SrcAddr 31 0 R W DMA Source address Channel destination address register DM...

Page 318: ...B master 1 LM 1 AHB master 2 Channel control register DMACCxControl0 The eight read write DMACCxControl0 registers contain DMA channel control information such as the burst size and transfer width Each register is programmed directly by software before the DMA channel is enabled When the channel is enabled the register is updated by following the linked list when a complete packet of data has been...

Page 319: ...amount of data that is transferred when the DMACxBREQ signal goes active in the destination peripheral The burst size is not related to the AHB HBURST signal SBSize 14 12 R W Source burst size Indicates the number of transfers which make up a source burst This value must be set to the burst size of the source peripheral or if the source is memory to the memory boundary size The burst size is the a...

Page 320: ...r than pass the transactions through one at a time This bit controls the AHB HPROT 3 signal Channel control register DMACCxControl1 The eight read write DMACCxControl1 registers contain DMA channel control information such as the transfer size Each register is programmed directly by software before the DMA channel is enabled When the channel is enabled the register is updated by following the link...

Page 321: ...rrupt of the relevant channel FlowCntrl 13 11 R W Flow control and transfer type This value is used to indicate the flow controller and transfer type The supported flow controller is only the DMA controller The transfer type can be memory to memory memory to peripheral peripheral to memory or peripheral to peripheral Reserved OneNandModeDst 10 R W Reserved must be written as zero and masked on rea...

Page 322: ...ansfer if one is in progress to complete and the channel is then disabled Any data in the channels FIFO is lost Restarting the channel by simply setting the Channel Enable bit has unpredictable effects and the channel must be fully re initialized The channel is also disabled and Channel Enable bit cleared when the last LLI is reached or if a channel error is encountered If a channel has to be disa...

Page 323: ...PRELIMINARY S3C6400X RISC MICROPROCESSOR DMA 11 27 NOTE ...

Page 324: ...rces The TZIC provides a software interface to the secure interrupt system in a TrustZone design It provides secure control of the nFIQ interrupt and masks the interrupt source s from the interrupt controller on the non secure side of the system VIC You can then use the latter to generate the nIRQ signal To generate nFIQ from the non secure interrupt sources the TZIC0 takes the nNSFIQIN signal fro...

Page 325: ...s Description Group 63 INT_ADC ADC EOC interrupt TZIC1 VIC1 62 INT_PENDN ADC Pen down interrupt TZIC1 VIC1 61 INT_SEC Security interrupt TZIC1 VIC1 60 INT_RTC_ALARM RTC alarm interrupt TZIC1 VIC1 59 INT_IrDA IrDA interrupt TZIC1 VIC1 58 INT_OTG USB OTG interrupt TZIC1 VIC1 57 INT_HSMMC1 HSMMC1 interrupt TZIC1 VIC1 56 INT_HSMMC0 HSMMC0 interrupt TZIC1 VIC1 55 INT_HOSTIF Host Interface interrupt TZI...

Page 326: ...External interrupt 12 19 TZIC1 VIC1 31 INT_LCD 2 LCD interrupt System I F done TZIC0 VIC0 30 INT_LCD 1 LCD interrupt VSYNC interrupt TZIC0 VIC0 29 INT_LCD 0 LCD interrupt FIFO underrun TZIC0 VIC0 28 INT_TIMER4 Timer 4 interrupt TZIC0 VIC0 27 INT_TIMER3 Timer 3 interrupt TZIC0 VIC0 26 INT_WDT Watchdog timer interrupt TZIC0 VIC0 25 INT_TIMER2 Timer 2 interrupt TZIC0 VIC0 24 INT_TIMER1 Timer 1 interr...

Page 327: ... yet available Specifications and information herein are subject to change without notice 8 Reserved TZIC0 VIC0 7 Reserved TZIC0 VIC0 6 Reserved TZIC0 VIC0 5 Reserved TZIC0 VIC0 4 INT_CAMIF_P Camera interface interrupt TZIC0 VIC0 3 INT_CAMIF_C Camera interface interrupt TZIC0 VIC0 2 INT_RTC_TIC RTC TIC interrupt TZIC0 VIC0 1 INT_EINT1 External interrupt 4 11 TZIC0 VIC0 0 INT_EINT0 External interru...

Page 328: ...duct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice FUNCTION BLOCK DIAGRAM Figure 12 2 Vectored Interrupt Controller block diagram ...

Page 329: ...iority Mask Register 0xFFFF VICPRIORITYDAISY 0x028 RW Vector Priority Register for Daisy Chain 0xF VICVECTADDR0 0x100 RW Vector Address 0 Register 0x00000000 VICVECTADDR1 0x104 RW Vector Address 1 Register 0x00000000 VICVECTADDR2 0x108 RW Vector Address 2 Register 0x00000000 VICVECTADDR3 0x10C RW Vector Address 3 Register 0x00000000 VICVECTADDR4 0x110 RW Vector Address 4 Register 0x00000000 VICVEC...

Page 330: ...ster 0xF VICVECTPRIORITY1 0x204 RW Vector Priority 1 Register 0xF VICVECTPRIORITY2 0x208 RW Vector Priority 2 Register 0xF VICVECTPRIORITY3 0x20C RW Vector Priority 3 Register 0xF VICVECTPRIORITY4 0x210 RW Vector Priority 4 Register 0xF VICVECTPRIORITY5 0x214 RW Vector Priority 5 Register 0xF VICVECTPRIORITY6 0x218 RW Vector Priority 6 Register 0xF VICVECTPRIORITY7 0x21C RW Vector Priority 7 Regis...

Page 331: ...ster 0xF VICVECTPRIORITY29 0x274 RW Vector Priority 29 Register 0xF VICVECTPRIORITY30 0x278 RW Vector Priority 30 Register 0xF VICVECTPRIORITY31 0x27C RW Vector Priority 31 Register 0xF VICADDRESS 0xF00 RW Vector Address Register 0x00000000 VICPERIPHID0 0xFE0 R Peripheral Identification Register bit 7 0 0x92 VICPERIPHID1 0xFE4 R Peripheral Identification Register bit 15 9 0x11 VICPERIPHID2 0xFE8 R...

Page 332: ...CFIQSTATUS Bits Name Type Function 31 0 FIQStatus R Show the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers 0 interrupt is inactive reset 1 interrupt is active There is one bit of the register for each interrupt source Raw Interrupt Status Register VICRAWINTR Bits Name Type Function 31 0 RawInterrupt R Show the status of the FIQ interrupts before masking ...

Page 333: ... Read 0 interrupt disabled reset 1 Interrupt enabled The interrupt enable can only be set using this register The VICINTENCLEAR Register must be used to disable the interrupt enable Write 0 no effect 1 interrupt enabled On reset all interrupts are disabled There is one bit of the register for each interrupt source Interrupt Enable Clear VICINTENCLEAR Bits Name Type Function 31 0 IntEnable Clear W ...

Page 334: ... SoftIntClear W Clears corresponding bits in the VICSOFTINT Register 0 no effect 1 software interrupt disabled in the VICSOFTINT Register There is one bit of the register for each interrupt source Protection Enable Register VICPROTECTION Bits Name Type Function 31 1 Reserved Reserved read as zero do not modify 0 Protection RW Enables or disables protected register access 0 protection mode disabled...

Page 335: ...e performed at the end of an interrupt service routine Software Priority Mask Register VICSWPRIORITYMASK Bits Name Type Function 31 16 Reserved Reserved read as zero do not modify 15 0 SWPriorityMask RW Controls software masking of the 16 interrupt priority levels 0 interrupt priority level is masked 1 interrupt priority level is not masked reset Each bit of the register is applied to each of the ...

Page 336: ...R These bits read back as 0x192 VICPERIPHID1 Register Bits Name Type Function 31 8 Reserved read as zero do not modify 7 4 Designer0 R These bits read back as 0x1 3 0 Partnumber1 R These bits read back as 0x1 VICPERIPHID2 Register Bits Name Type Function 31 8 Reserved read as zero do not modify 7 4 Revision R These bits read back as the revision number which can be between 0 and 15 3 0 Designer1 R...

Page 337: ...ICPCELLID0 3 VICPCELLID0 Register Bits Name Type Function 31 8 Reserved read as zero do not modify 7 0 VICPCellID0 R These bits read back as 0x0D VICPCELLID1 Register Bits Name Type Function 31 8 Reserved read as zero do not modify 7 0 VICPCellID1 R These bits read back as 0xF0 VICPCELLID2 Register Bits Name Type Function 31 8 Reserved read as zero do not modify 7 0 VICPCellID2 R These bits read b...

Page 338: ...SsS also provides high speed bulk data processing by providing double layer AHB bus and FIFOs FIFO Rx and FIFO Tx can be programmed to monitor AES or DES 3DES or SHA 1 PRNG module and automatically transfer input output data from the target module This scheme does not require CPU s intervention and can achieve high speed bulk data processing Figure 13 1 shows the block diagram of the SsS and its m...

Page 339: ...nary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 13 1 Block Diagram of the Security Sub System ...

Page 340: ...r Base 0x7D40_0000 Base 0x7D90_0000 Have to use this address to transfer using SDMA1 SDMA1 only see this address Note Write access to FRx_WrBuf makes FIFO Rx to write data to the FIFO memory regardless of the address given That is any address between 0x0040 and 0x007C will trigger the FIFO memory write This feature lets the programmer use burst write to the FIFO Rx Table 3 FIFO Tx Register Map Add...

Page 341: ..._KEY_02 AES Rx Key Input Reg 02 Base 0x88 R W 0x0000_0000 AES_Rx_KEY_03 AES Rx Key Input Reg 03 Base 0x8C R W 0x0000_0000 AES_Rx_KEY_04 AES Rx Key Input Reg 04 Base 0x90 R W 0x0000_0000 AES_Rx_KEY_05 AES Rx Key Input Reg 05 Base 0x94 R W 0x0000_0000 AES_Rx_KEY_06 AES Rx Key Input Reg 06 Base 0x98 R W 0x0000_0000 AES_Rx_KEY_07 AES Rx Key Input Reg 07 Base 0x9C R W 0x0000_0000 AES_Rx_KEY_08 AES Rx K...

Page 342: ... Key Input Reg 2_0 Base 0x1C R W 0x0000_0000 TDES_Rx_KEY2_1 DES 3DES Rx Key Input Reg 2_1 Base 0x20 R W 0x0000_0000 TDES_Rx_KEY3_0 DES 3DES Rx Key Input Reg 3_0 Base 0x24 R W 0x0000_0000 TDES_Rx_KEY3_1 DES 3DES Rx Key Input Reg 3_1 Base 0x40 R W 0x0000_0000 TDES_Rx_INPUT_0 DES 3DES Rx Data Input Reg 0 Base 0x44 R W 0x0000_0000 TDES_Rx_INPUT_1 DES 3DES Rx Data Input Reg 1 Base 0x48 R 0x0000_0000 TD...

Page 343: ... 159 128 Base 0x1C R W 0x0000_0000 SEED_DATA_06 PRNG Seed data 191 160 Base 0x20 R W 0x0000_0000 SEED_DATA_07 PRNG Seed data 223 192 Base 0x24 R W 0x0000_0000 SEED_DATA_08 PRNG Seed data 255 224 Base 0x28 R W 0x0000_0000 SEED_DATA_09 PRNG Seed data 287 256 Base 0x2C R W 0x0000_0000 SEED_DATA_10 PRNG Seed data 319 288 Base 0x30 R 0x0000_0010 HASH_STATUS Status check Base 0x34 R 0x0000_0000 HASH_OUT...

Page 344: ...ASH length 31 0 Tx SHA 1 PRNG Register Map Tx side Base 0x34 R 0x0000_0000 HASH_OUTPUT_01 PRNG_OUTPUT_01 HASH PRNG output h0 Base 0x38 R 0x0000_0000 HASH_OUTPUT_02 PRNG_OUTPUT_02 HASH PRNG output h1 Base 0x3C R 0x0000_0000 HASH_OUTPUT_03 PRNG_OUTPUT_03 HASH PRNG output h2 Base 0x40 R 0x0000_0000 HASH_OUTPUT_04 PRNG_OUTPUT_04 HASH PRNG output h3 Base 0x44 R 0x0000_0000 HASH_OUTPUT_05 PRNG_OUTPUT_05...

Page 345: ...ad 0b DES_intr_Status 21 DES 3DES interrupt status and peding bit This is cleared when read 0b AES_intr_Status 20 AES interrupt status and peding bit This is cleared when read 0b Reserved 19 18 Reserved 00b FTx_intr_Status 17 FIFO Tx interrupt status and peding bit This is cleared when read 0b FRx_intr_Status 16 FIFO Rx interrupt status and peding bit This is cleared when read 0b Reserved 15 Reser...

Page 346: ..._WrBuf is empty 1b FRx_Done 25 Sets to 1 if FIFO Rx has finished transferring FRx_MLen words of data to the destination 0b FRx_Running 24 Sets to 1 if FIFO Rx is transferring data to the destination or waiting for destination input buffer is ready Sets to 1 when FRx_Start bit resets to 0 0b FRx_Wd2Write 23 16 Number of words that can be written to FIFO memory FRx_WrBuf 0x00 FRx_Wd2Read 15 8 Number...

Page 347: ...0 LastValidByte 17 16 Last valid byte in the last word transferred to the SHA 1 PRNG module Only valid when FRx_Dest_Module 2 b10 in FRx_Ctrl End of the SHA text byte 00 first byte LSB in 32bit 01 second byte 10 third byte 11 fourth byte full 32bit Resets to its reset value when FRx_Reset field of FRx_Ctrl register is set 00b BlkSz 15 0 Block size of destination module in word 32 bit unit FIFO Rx ...

Page 348: ...ords left for transfer 0x0000_0000 FIFO RX WRITE BUFFER Register Address R W Description Reset Value 0x7D40_0040 0x7D40_007C FIFO Rx write buffer 32 word Note This address is for CPU access FRx_WrBuf 0x7D90_0040 0x7D90_007C W FIFO Rx write buffer 32 word Note This address is for SDMA1 Security DMA 1 You should use it to transfer from memory to FRx_WrBuf using SDMA1 0x0000_0000 FRx_WrBuf Bit Descri...

Page 349: ...Full 27 Sets to 1 if FIFO Tx buffer FTx_RdBuf is full 0b Empty 26 Sets to 1 if FIFO Tx buffer FTx_RdBuf is empty 1b Done 25 Sets to 1 if FIFO Tx has finished transferring FTx_MLen words of data from the source 0b Running 24 Sets to 1 if FIFO Tx is transferring data from the source or waiting for source output buffer is ready Sets to 1 when FTx_Start bit resets to 0 0b Wd2Read 23 16 Number of words...

Page 350: ... Initial State FTx_BlkSz 31 0 Block size of destination module in word 32 bit unit FIFO Tx will transfer FTx_BlkSz word and then triggers the destination module to start processing The destination module is selected by FTx_Dest_Module field in FTx_Ctrl Resets to its reset value when FTx_Reset field of FTx_Ctrl register is set 0x0000_0000 FIFO TX SOURCE ADDRESS REGISTER Register Address R W Descrip...

Page 351: ...x read buffer 32 word Note This address is for CPU access FTx_RdBuf 0x7DA0_0040 0x7DA0_007 C R W FIFO Tx read buffer 32 word Note This address is for SDMA1 Security DMA 1 You should use it to transfer from FTx_RdBuf to memory using SDMA1 0x0000_0000 FTx_RdBuf Bit Description Initial State RdBuf 31 0 FIFO Tx read buffer 32x32 bit 0x0000_0000 Note Read access to FTx_RdBuf makes FIFO Tx to read data ...

Page 352: ...s Privilege Mismatch is occurred 0b Reserved 29 11 Reserved 0x000000 AesOutReady 10 If set to 1 AES Output Buffer is Full and ARM or Rx FiFo is permitted to Read current 128bits result data 0b AesInReady 9 If set to 1 AES Input Buffer is Empty and ARM or Rx FiFo is permitted to write next 128bits data 1b AesContDecOn 8 Continuous Decryption Enable Bits 0 Decryption Key is changed 1 Decryption Key ...

Page 353: ...AES 1st 4th 32bit Data Input Register 0x0000_0000 AES_RX_DOUT_01 AES_RX_DOUT_04 AES_TX_DOUT_01 AES_TX_DOUT_04 Register Address R W Description Reset Value AES_Rx_DOUT_01 0x7D10_0020 R W AES Data Output Register 01 Least Significant 0x0000_0000 AES_Rx_DOUT_02 0x7D10_0024 R W AES Data Output Register 02 Least Significant 0x0000_0000 AES_Rx_DOUT_03 0x7D10_0028 R W AES Data Output Register 03 Least Si...

Page 354: ... Significant 0x0000_0000 AES_Rx_KEY_08 0x7D10_009C R W AES Key Input Register 08 Least Significant 0x0000_0000 AES_Rx_KEY Bit Description Initial State AesKey 31 0 AES 1st 8th 32bit Key Input Register 0x0000_0000 AES_RX_IV_01 AES_RX_IV_04 Register Address R W Description Reset Value AES_Rx_IV_01 0x7D10_00A0 R W AES IV Input Register 01 0x0000_0000 AES_Rx_IV_02 0x7D10_00A4 R W AES IV Input Register...

Page 355: ...d 0b RdPrivMismatch 30 SFR Read Access Privilege Mismatch Status bit If set to 1 SFR Read Access Privilege Mismatch is occurred 0b Reserved 29 8 Reserved 0x0000_00 TdesOutReady 7 If set to 1 AES Out Buffer is Full and ARM or Rx FiFo is permitted to Read current 128bits result data 0b TdesInReady 6 If set to 1 TDES Input Buffer is Empty and ARM or Rx FiFo is permitted to write next 128bits data 1b ...

Page 356: ...t 0x0000_0000 TDES_Rx_KEY Bit Description Initial State TdesKey 31 0 TDES 1st 6th 32bit Key Input Register 0x0000_0000 TDES_RX_INPUT_0 TDES_RX_INPUT_1 Register Address R W Description Reset Value TDES_Rx_INPUT_0 0x7D20_0040 R W TDES Data Input Register 0 Least Significant 0x0000_0000 TDES_Rx_INPUT_1 0x7D20_0044 R W TDES Data Input Register 1 Least Significant 0x0000_0000 TDES_Rx_INPUT Bit Descript...

Page 357: ...e not yet available Specifications and information herein are subject to change without notice TDES_RX_IV_0 TDES_RX_IV_1 Register Address R W Description Reset Value TDES_Rx_IV_0 0x7D20_0050 R W TDES IV Input Register 0 0x0000_0000 TDES_Rx_IV_1 0x7D20_0054 R W TDES IV Input Register 1 0x0000_0000 TDES_Rx_IV Bit Description Initial State TdesIv 31 0 TDES 1st and 2nd 32bit IV Input Register 0x0000_0...

Page 358: ...ants 0 constants 1 arbitary IV 0b End_of_Hash_byte 7 6 End of the SHA text byte 00 first byte LSB in 32bit 01 second byte 10 third byte 11 fourth byte full 32bit 00b SEED_SETTING_ENABLE 5 Seed setting enable 1 b1 0b Hash_input_finished 4 Finished the hash input will be cleared by hardware 0b Hash_start 3 Start the hash software reset will be automatically cleared by hardware 0b Data_Selection 2 In...

Page 359: ..._DATA_08 0x7D30_0024 R W PRNG seed data 8 255 224 0x0000_0000 SEED_DATA_09 0x7D30_0028 R W PRNG seed data 9 287 256 0x0000_0000 SEED_DATA_10 0x7D30_002C R W PRNG seed data 10 319 288 0x0000_0000 SEED_DATA Bit Description Initial State SEED_DATA 31 0 PRNG seed data HASH_CONTROL 5 1 b1 0x0000_0000 HASH_STATUS Register Address R W Description Reset Value HASH_STATUS 0x7D30_0030 R Hash status 0x0000_0...

Page 360: ...PUT_08 0x7D30_0050 R Hash output 08 or PRNG output 255 224 0x0000_0000 HASH_OUTPUT_09 0x7D30_0054 R Hash output 09 or PRNG output 287 256 0x0000_0000 HASH_OUTPUT_10 0x7D30_0058 R Hash output 10 or PRNG output 319 288 0x0000_0000 HASH_OUTPUT_01 0x7D70_0034 R Hash output 01 or PRNG output 31 1 0x0000_0000 HASH_OUTPUT_02 0x7D70_0038 R Hash output 02 or PRNG output 63 32 0x0000_0000 HASH_OUTPUT_03 0x7...

Page 361: ...70_0060 R HASH_MIDOUT 127 96 0x0000_0000 HASH_MIDOUT_03 0x7D70_0064 R HASH_MIDOUT 95 64 0x0000_0000 HASH_MIDOUT_04 0x7D70_0068 R HASH_MIDOUT 63 32 0x0000_0000 HASH_MIDOUT_05 0x7D70_006C R HASH_MIDOUT 31 0 0x0000_0000 HASH_MIDOUT Bit Description Initial State HASH_MIDOUT 31 0 HASH_MIDOUT 0x0000_0000 HASH_IV_01 HASH_IV_05 Register Address R W Description Reset Value HASH_IV_01 0x7D30_0070 W HASH_IV ...

Page 362: ...are not yet available Specifications and information herein are subject to change without notice PRE_MSG_LENGTH_01 PRE_MSG_LENGTH_02 Register Address R W Description Reset Value PRE_MSG_LENGTH_01 0x7D70_0084 R W PRE_MSG_LENGTH 63 32 0x0000_0000 PRE_MSG_LENGTH_02 0x7D70_0088 R W PRE_MSG_LENGTH 31 0 0x0000_0000 PRE_MSG_LENGTH Bit Description Initial State PRE_MSG_LENGTH 31 0 PRE_MSG_LENGTH 0x0000_00...

Page 363: ...up to 5 overlay image windows Overlay image windows support various color format 16 level alpha blending color key x y position control soft scrolling variable window size and etc The display controller supports various color formats such as RGB 1BPP to 24 BPP and YCbCr 4 4 4 only local bus The display controller can be programmed to support the different requirements on the screen Requirements re...

Page 364: ... BPP bit per pixel palletized color Supports 16 18 or 24 BPP non palletized color Supports YCbCr 4 4 4 local input from Local Bus Post Processor Supports RGB 8 8 8 local input from Local Bus Post Processor Window 1 Supports 1 2 4 or 8 BPP bit per pixel palletized color Supports 16 18 or 24 BPP non palletized color Supports YCbCr 4 4 4 local input from Local Bus TV Scaler Supports RGB 8 8 8 local i...

Page 365: ... up table 256 x 25 ARGB bits palette 2ea for Window 0 Window1 16 entry x 16 bits Look up table for Window 2 16 entry x 16 bits Look up table for Window 3 4 entry x 16 bits Look up table for Window 4 Soft Scrolling Horizontal 1 Byte resolution Vertical 1 pixel resolution Virtual Screen Virtual image can have up to 16 Mbyte image size Transparent Overlay Supports Transparent Overlay Color Key Chroma...

Page 366: ...VDEN SYS_CS1 SYS_CS0 etc Data Flow FIFO is present in the VDMA When FIFO is empty or partially empty VDMA requests data fetching from the frame memory based on the burst memory transfer mode Consecutive memory fetching of 4 8 16 words per one burst request without allowing the bus mastership to another bus master during the bus transfer When this kind of transfer request is accepted by bus arbitra...

Page 367: ...agram of the Data Flow Interface Display controller supports 2 types of display device One type is the conventional RGB interface which uses RGB data Vertical horizontal sync data valid signal and data sync clock The Second type is I80 CPU Interface which uses address data chip select read write control and register status indicating signal In this type of LCD driver it has a frame buffer and has ...

Page 368: ...mat of frame buffer The next table shows some examples of each display mode 25BPP display A888 BSWP 0 HWSWP 0 D 31 25 D 24 D 23 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel would be blended with alpha value selected by AEN ...

Page 369: ...ay A887 BSWP 0 HWSWP 0 D 31 24 D 23 D 22 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel would be blended with alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G AL...

Page 370: ...for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 24BPP display 888 BSWP 0 HWSWP 0 D 31 24 D 23 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel Note 1 D 23 16 Red data D 15 8 Green data D 7 0 Blue data ...

Page 371: ...ay A666 BSWP 0 HWSWP 0 D 31 19 D 18 D 17 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel would be blended with alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G AL...

Page 372: ...ll characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 18BPP display 666 BSWP 0 HWSWP 0 D 31 18 D 17 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel P1 P2 P3 P4 P5 LCD Panel Note 1 D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 373: ...H AEN1 P1 AEN2 P2 004H AEN3 P3 AEN4 P4 008H AEN5 P5 AEN6 P6 BSWP 0 HWSWP 1 31 D 30 16 D 15 D 14 0 000H AEN2 P2 AEN1 P1 004H AEN4 P4 AEN3 P3 008H AEN6 P6 AEN5 P5 P1 P2 P3 P4 P5 LCD Panel Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel would be blended with alpha value selected by AEN Alpha value is selected by SFR valu...

Page 374: ...ion data and associated errata are not yet available Specifications and information herein are subject to change without notice 16BPP display 1555 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 P1 P2 P3 P4 P5 LCD Panel Note 1 D 14 10 D 15 Red data D 9 5 D 15 Green data D 4 0 D 15 Blue data ...

Page 375: ...cterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 16BPP display 565 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 P1 P2 P3 P4 P5 LCD Panel Note 1 D 15 11 Red data D 10 5 Green data D 4 0 Blue data ...

Page 376: ... 23 16 D 15 8 D 7 0 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 BSWP 1 HWSWP 0 D 31 24 D 23 16 D 15 8 D 7 0 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel would be blended with alpha value selected by AEN ...

Page 377: ...H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 BSWP 1 HWSWP 0 D 31 28 D 27 24 D 23 20 D 19 16 D 15 12 D 11 8 D 7 4 D 3 0 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 Note 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pi...

Page 378: ...4 P5 P6 P7 P8 004H P17 P18 P19 P20 P21 P22 P23 P24 008H P33 P34 P35 P36 P37 P38 P39 P40 D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000H P9 P10 P11 P12 P13 P14 P15 P16 004H P25 P26 P27 P28 P29 P30 P31 P32 008H P41 P42 P43 P44 P45 P46 P47 P48 Note 1 If ALPHAPAL is enabled then the MSB of Palette memory is acting as a AEN bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this...

Page 379: ... etc format For example of A 5 5 5 format write palette as specified in Table 14 2 and then connect VD pin to TFT LCD panel R 5 VD 23 19 G 5 VD 15 11 and B 5 VD 7 3 The AEN bit controls the blending function enable or disable At the end Set WPALCON W1PAL case window0 register to 0 b101 Table 14 1 25 A 8 8 8 Palette Data Format INDE X Bit Pos 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 ...

Page 380: ... 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 00H A E N R 4 R 3 R 2 R 1 R 0 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 01H A E N R 4 R 3 R 2 R 1 R 0 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 FFH A E N R 4 R 3 R 2 R 1 R 0 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 Num ber of VD 2 3 2 2 2 1 2 0 1 9 1 5 1 4 1 3 1 2 1 1 7 6 5 4 3 Palette Read Write It is prohibited to access Palette...

Page 381: ...he color limitation by using color index with Color LUT This feature enhances the system performance by reducing the data rate of total system Total 5 window example win 0 base Local YCbCr RGB without palette win 1 Overlay1 RGB with palette win 2 Overlay2 RGB with palette win 3 Caption RGB 1 2 4 with 16 level Color LUT win 4 Cursor RGB 1 2 with 4 level Color LUT Overlay Priority Win 4 Win 3 Win 2 ...

Page 382: ...Alpha WinOut B Win0123 B x Beta Win4 B x Alpha Where if A bit is set then AR1 Window 1 s Red blending factor ALPHA1_R VIDOSD1C AR2 Window 2 s Red blending factor ALPHA1_R VIDOSD2C AR3 Window 3 s Red blending factor ALPHA1_R VIDOSD3C Else if A bit is cleared then AR1 Window 1 s Red blending factor ALPHA0_R VIDOSD1C AR2 Window 2 s Red blending factor ALPHA0_R VIDOSD2C AR3 Window 3 s Red blending fac...

Page 383: ...example of the R Red output using ALPHA_R value of each window All windows have two kinds of alpha blending value One is alpha value for transparency enable AEN value 1 the other is alpha value for transparency disable AEN value 0 If WINEN_F is enabled and BLD_PIX is enabled then AR will be selected by applying the below equation AR Pixel R s AEN value 1 b1 Reg ALPHA1_R Reg ALPHA0_R AG Pixel G s A...

Page 384: ...ice Table 14 3 Blending User s Table ALPHA_SEL 1 value WINCON1 2 3 4 0 1 0 Plane blending using ALPHA0 Plane blending using ALPAH1 BLD_PIX 6 value WINCON1 2 3 4 1 Pixel blending selected by AEN AEN value Frame Buffer 0 1 Using ALPHA0 Using ALPHA1 OR Color key blending enabled by KEYBLEN KEYBLEN 26 value W1 2 3 4KEYCON0 0 1 Key blending disable Non key area using ALPHA0 Key area using ALPHA1 Pixel ...

Page 385: ... The display controller supports color key function for the various effect of image mapping Color image of OSD layer which is specified by COLOR KEY register will be substituted by back ground image for special functionality It will be substituted as cursor image or pre view image of the camera Figure 14 5 Color key function configurations Color Key Enable Blended Alpha 0 OSD Image 180x100 Back Gr...

Page 386: ...gurations of the display control registers in VSFR the VTIME module can generate the programmable control signals suitable for the support of many different types of display device The RGB_VSYNC signal is asserted to cause the LCD s line pointer to start over at the top of the display The RGB_VSYNC and RGB_HSYNC pulse generation is controlled by the configuration of both the HOZVAL field and the L...

Page 387: ..._CS1 SYS_WE and SYS_RS control signals are generated by VTIME_I80 For more information refer to Figure 14 9 for Timing Diagram Their timing parameters LCD_CS_SETUP LCD_WR_SETUP LCD_WR_ACT LCD_WR_HOLD can be set through I80IFCONA0 and I80IFCONA1 SFRs Partial Display Control Although partial display is a main feature of cpu style LDI VTIME_I80 does not support this function in H W logic However this...

Page 388: ... to LDI_CMD11 contiguously For example only the use of LDI_CMD0 LDI_CMD3 and LDI_CMD11 is possible 3 Maximum 12 auto commands are available Normal Command Setting commands in LDI_CMD0 11 Setting 0x1 for CMD0_EN CMD11_EN Set NORMAL_CMD_ST Display Controller has the following miscellaneous traits for command operations Auto Normal Auto and Normal command mode is possible for each 12 commands Display...

Page 389: ...mand CMD1 CMD2 CMD3 CMD4 AUTO_COMMAND_RATE 4 b0010 per 4 frames CMD0_RS 1 CMD1_RS 1 CMD2_RS 0 CMD3_RS 1 CMD4_RS 0 RSPOL 0 Figure 14 6 Sending Command I80 CPU Interface Trigger VTIME_I80 starts its operation only when a S W trigger occurs There are two kinds of triggers S W trigger is generated by setting SW_CPUSTTRIG SFR Interrupt Frame Done Interrupt is generated at the completion of one frame 1 ...

Page 390: ...ata of line 8 of virtual screen This is the data of line 8 of virtual screen This is the data of line 9 of virtual screen This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD p...

Page 391: ...ync Signal RGB_VSYNC Output Pad Vertical Sync Signal RGB_VCLK Output Pad LCD Video Clock RGB_VDEN Output Pad Data Enable RGB_VD 23 0 Output Pad RGB data output In 16bpp pins match with following as RGB_VD 23 19 R RGB_VD 15 10 G RGB_VD 7 3 B Please refer to Table 14 7 for more information Note LCD_SEL 1 0 value 0x7F0081A0 must be set as 01 to use RGB I F Style Please refer to GPIO Manual for more i...

Page 392: ...ce Destination Description SYS_VDIN 17 0 In Video Mux Video Data Input SYS_VDOUT 17 0 Out Video Mux Video Data Output SYS_CS0 Output Video Mux Chip select for LCD0 SYS_CS1 Output Video Mux Chip select for LCD1 SYS_WE Output Video Mux Write enable SYS_OE Output Video Mux Output Enable SYS_RS Output Video Mux Register State Select Note LCD_SEL 1 0 value 0x7F0081A0 must be set as 00 to use Host I F S...

Page 393: ...llel 24BPP 888 18BPP 666 16BPP 565 24BPP 888 16BPP 666 18BPP 666 16BPP 565 VD 23 R 7 R 5 R 4 D 7 D 5 VD 22 R 6 R 4 R 3 D 6 D 4 VD 21 R 5 R 3 R 2 D 5 D 3 VD 20 R 4 R 2 R 1 D 4 D 2 VD 19 R 3 R 1 R 0 D 3 D 1 VD 18 R 2 R 0 D 2 D 0 VD 17 R 1 D 1 R 5 VD 16 R 0 D 0 R 4 VD 15 G 7 G 5 G 5 R 3 R 4 VD 14 G 6 G 4 G 4 R 2 R 3 VD 13 G 5 G 3 G 3 R 1 R 2 VD 12 G 4 G 2 G 2 R 0 R 1 VD 11 G 3 G 1 G 1 G 5 R 0 VD 10 G...

Page 394: ...external modem or MCU can access the system interface LCD Panel through the by pass After reset the initial output path of LCD controller is by pass like described in below figure 14 10 In order to operate in the normal display mode RGB or CPU I F SEL_BYPASS 3 value 0x7410800C must be set as 0 normal mode instead of 1 by pass mode CAM IF Post Processor Display Controller TV Scaler TV Encoder DAC 2...

Page 395: ...play 7 WINCONx each window format setting 8 VIDOSDxA VIDOSDxB Window position setting 9 VIDOSDxC alpha value setting 10 VIDWxxADDx source image address setting 11 WxKEYCONx Color key value register 12 WINxMAP window color control 13 WPALCON palette control register 14 WxPDATAxx Window Palette Data of the each Index SFR Memory Map Register Address R W Description Reset Value VIDCON0 0x77100000 R W ...

Page 396: ...x77100088 R W Video Window 4 s position control register 0x0000_0000 VIDW00ADD0B0 0x771000A0 R W Window 0 s buffer start address register buffer 0 0x0000_0000 VIDW00ADD0B1 0x771000A4 R W Window 0 s buffer start address register buffer 1 0x0000_0000 VIDW01ADD0B0 0x771000A8 R W Window 1 s buffer start address register buffer 0 0x0000_0000 VIDW01ADD0B1 0x771000AC R W Window 1 s buffer start address r...

Page 397: ...ontrol 0x0000_0000 WIN4MAP 0x77100190 R W Window color control 0x0000_0000 WPALCON 0x771001A0 R W Window Palette control register 0x0000_0000 TRIGCON 0x771001A4 R W I80 RGB Trigger Control register 0x0000_0000 I80IFCONA0 0x771001B0 R W I80 Interface control 0 for Main LDI 0x0000_0000 I80IFCONA1 0x771001B4 R W I80 Interface control 0 for Sub LDI 0x0000_0000 I80IFCONB0 0x771001B8 R W I80 Interface c...

Page 398: ...tte Data of the Index A B 0x0000_0000 W2PDATACD 0x77100318 R W Window 2 Palette Data of the Index C D 0x0000_0000 W2PDATAEF 0x7710031C R W Window 2 Palette Data of the Index E F 0x0000_0000 W3PDATA01 0x77100320 R W Window 3 Palette Data of the Index 0 1 0x0000_0000 W3PDATA23 0x77100324 R W Window 3 Palette Data of the Index 2 3 0x0000_0000 W3PDATA45 0x77100328 R W Window 3 Palette Data of the Inde...

Page 399: ...BPP 011 16 8 bit mode 24 BPP 100 18 bit mode 18BPP 101 8 8 bit mode 16BPP 000 L0_DATA16 22 20 Select the mode of output data format of I80 CPU I F LDI0 Only when VIDOUT 1 0 2 b10 000 16 bit mode 16 BPP 001 16 2 bit mode 18 BPP 010 9 9 bit mode 18 BPP 011 16 8 bit mode 24 BPP 100 18 bit mode 18BPP 101 8 8 bit mode 16BPP 000 19 Reserved 0 PNRMODE 18 17 Select the display mode Where VIDOUT 1 0 2 b00 ...

Page 400: ...current frame end 0 Disable the video output and the Display control signal 1 Enable the video output and the Display control signal If set on and off this bit then you will read H and video controller enable until the end of current frame 0 Note 1 Display On ENVID ENVID_F set to 1 Direct Off ENVID ENVID_F set to 0 simultaneously Per Frame Off ENVID_F set 0 ENVID set 1 Caution In normal display mo...

Page 401: ...6 Vertical back porch is the number of inactive lines at the start of a frame after vertical synchronization period 0x0 VFPD 15 8 Vertical front porch is the number of inactive lines at the end of a frame before vertical synchronization period 0x0 VSPW 7 0 Vertical sync pulse width determines the VSYNC pulse s high level width by counting the number of inactive lines 0x0 Video Time Control 1 Regis...

Page 402: ...20 R W Window 0 control register 0x0000_0000 WINCON0 Bit Description Initial State nWide Narrow 27 26 Select color space conversion equation from YCbCr to RGB according to input value range 2 00 for YCbCr Wide range and 2 11 for YCbCr Narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 00 25 23 Reserved 0 ENLOCAL 22 Select Data access method 0 Dedicated DMA 1 Local Path from P...

Page 403: ...ed 0100 reserved 0101 16 BPP non palletized R 5 G 6 B 5 0110 reserved 0111 16 BPP non palletized I 1 R 5 G 5 B 5 1000 unpacked 18 BPP non palletized R 6 G 6 B 6 1001 reserved 1010 reserved 1011 unpacked 24 BPP non palletized R 8 G 8 B 8 11xx reserved 0 Reserved 1 0 ENWIN_F 0 Video output and the logic immediately enable disable 0 Disable the video output and the VIDEO control signal 1 Enable the v...

Page 404: ...disable at the ENWIN_F disable state 0 BUFSTATUS 21 Buffer Status Read Only 0 buffer set 0 1 buffer set 1 0 BUFSEL 20 Select Buffer set 0 1 0 buffer set 0 1 buffer set 1 0 BUFAUTOEN 19 Double Buffer Auto control bit 0 Fixed by BUFSEL 1 Auto changed by Trigger Input 0 BITSWP 18 Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP 17 Byte swaps control bit 0 Swap Disable 1 Swap Enable 0 HAWSWP...

Page 405: ...alletized A 1 R 8 G 8 B 8 111x reserved Note 1101 can support unpacked 28 BPP also non palletized A 4 R 8 G 8 B 8 at BLD_PIX 1 ALPHA_SEL 1 Select Alpha value by When Per plane blending case BLD_PIX 0 0 using ALPHA0_R G B values 1 using ALPHA1_R G B values When Per pixel blending BLD_PIX 1 0 selected by AEN A value or chroma key 1 using DATA 27 24 data only when BPPMODE_F 4 b1101 0 ENWIN_F 0 Video ...

Page 406: ...isable state 0 21 19 Reserved BITSWP 18 Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP 17 Byte swaps control bit 0 Swap Disable 1 Swap Enable 0 HAWSWP 16 Half Word swap control bit 0 Swap Disable 1 Swap Enable 0 reserved 15 12 Must be 0 0 InRGB 13 It indicates the input color space of source image Only for ENLOCAL enable 0 RGB 1 YCbCr 0 reserved 12 11 Should be 0 0 BURSTLEN 10 9 DMA s ...

Page 407: ...using ALPHA0_R G B values 1 using ALPHA1_R G B values When BLD_PIX 1 0 selected by AEN A value or chroma key 1 using DATA 27 24 data only when BPPMODE_F 4 b1101 0 ENWIN_F 0 Video output and the logic immediately enable disable 0 Disable the video output and the VIDEO control signal 1 Enable the video output and the VIDEO control signal 0 Window 3 Control Register Register Address R W Description R...

Page 408: ...palletized A 1 R 6 G 6 B 6 1011 unpacked 24 BPP non palletized R 8 G 8 B 8 1100 unpacked 24 BPP non palletized A 1 R 8 G 8 B 7 1101 unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 111x reserved Note 1101 can support unpacked 28 BPP also non palletized A 4 R 8 G 8 B 8 at BLD_PIX 1 0 ALPHA_SEL 1 Select Alpha value by When BLD_PIX 0 0 using ALPHA0_R G B values 1 using ALPHA1_R G B values When BLD_PIX ...

Page 409: ... Select the BPP Bits Per Pixel mode Window image 0000 1 BPP LUT 0001 2 BPP LUT 0010 reserved 0011 reserved 0100 reserved 0101 16 BPP non palletized R 5 G 6 B 5 0110 16 BPP non palletized A 1 R 5 G 5 B 5 0111 16 BPP non palletized I 1 R 5 G 5 B 5 1000 unpacked 18 BPP non palletized R 6 G 6 B 6 1001 unpacked 18 BPP non palletized A 1 R 6 G 6 B 5 1010 unpacked 19 BPP non palletized A 1 R 6 G 6 B 6 10...

Page 410: ...r interlace TV output this value MUST be set to half of the original screen y coordinate And the original screen y coordinate MUST be even value 0 Window 0 Position Control B Register Register Address R W Description Reset Value VIDOSD0B 0x77100044 R W Video Window 0 s position control register 0x0 VIDOSD0B Bit Description initial state OSD_RightBotX_F 21 11 Horizontal screen coordinate for right ...

Page 411: ... 10 0 Vertical screen coordinate for left top pixel of OSD image for interlace TV output this value MUST be set to half of the original screen y coordinate And the original screen y coordinate MUST be even value 0 Window 1 Position Control B Register Register Address R W Description Reset Value VIDOSD1B 0x77100054 R W Video Window 1 s position control register 0x0 VIDOSD1B Bit Description initial ...

Page 412: ...d Alpha value case AEN 1 0 ALPHA1_G 7 4 Green Alpha value case AEN 1 0 ALPHA1_B 3 0 Blue Alpha value case AEN 1 0 Window 1 Position Control D Register Register Address R W Description Reset Value VIDOSD1D 0x7710005C R W Video Window 0 s Size control register 0x0 VIDOSD1D Bit Description initial state 25 Reserved 0 24 Reserved 0 OSDSIZE 23 0 Window Size Eq Height Width Number of Word Note Set filed...

Page 413: ...screen coordinate for right bottom pixel of OSD image for interlace TV output this value MUST be set to half of the original screen y coordinate And the original screen y coordinate MUST be odd value 0 Note Registers must have word boundary X position So 24 BPP mode must have X position by 1 pixel ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel ex X 0 2 4 6 8 BPP mode must have X position...

Page 414: ... Video Window 3 s position control register 0x0 VIDOSD3A Bit Description initial state OSD_LeftTopX_F 21 11 Horizontal screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F 10 0 Vertical screen coordinate for left top pixel of OSD image for interlace TV output this value MUST be set to half of the original screen y coordinate And the original screen y coordinate MUST be even value 0 W...

Page 415: ...pha control register 0x0 VIDOSD3C Bit Description initial state 24 Reserved 0 ALPHA0_R 23 20 Red Alpha value case AEN 0 0 ALPHA0_G 19 16 Green Alpha value case AEN 0 0 ALPHA0_B 15 12 Blue Alpha value case AEN 0 0 ALPHA1_R 11 8 Red Alpha value case AEN 1 0 ALPHA1_G 7 4 Green Alpha value case AEN 1 0 ALPHA1_B 3 0 Blue Alpha value case AEN 1 0 Window 4 Position Control A Register Register Address R W...

Page 416: ...f OSD image for interlace TV output this value MUST be set to half of the original screen y coordinate And the original screen y coordinate MUST be odd value 0 Note Registers must have word boundary X position So 24 BPP mode must have X position by 1 pixel ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel ex X 0 2 4 6 8 BPP mode must have X position by 4 pixel ex X 0 4 8 12 Window 4 Positio...

Page 417: ...W Window 4 s buffer start address register 0x0 VIDWxxADD0 Bit Description Initial State VBANK_F 31 24 These bits indicate A 31 24 of the bank location for the video buffer in the system memory 0 VBASEU_F 23 0 These bits indicate A 23 0 of the start address of the Video frame buffer 0 FRAME Buffer Address 1 Register Register Address R W Description Reset Value VIDW00ADD1B0 0x771000D 0 R W Window 0 ...

Page 418: ...s of the first byte to be displayed in the new Video line OFFSIZE_F must have value that is multiple of 4 byte size or 0 0 PAGEWIDTH_F 12 0 Virtual screen page width the number of byte This value defines the width of the view port in the frame PAGEWIDTH must have bigger value than the burst size and the size must be aligned word boundary 0 VIDEO interrupt Control 0 Register Register Address R W De...

Page 419: ...e 1 enable 5 Window 0 control 0 disable 1 enable 0 FIFOLEVEL 4 2 Video FIFO Interrupt Level Select 000 0 25 001 0 50 010 0 75 011 0 empty 100 100 full 0 INTFIFOEN 1 Video FIFO interrupts Enable control bit 0 Video FIFO Level Interrupt Disable 1 Video FIFO Level Interrupt Enable 0 INTEN 0 Video interrupts Enable control bit 0 Video Interrupt Disable 1 Video Interrupt Enable 0 VIDEO interrupt Contro...

Page 420: ...lor Key Chroma key Enable control 0 color key disable 1 color key enable 0 DIRCON 24 Color key Chroma key direction control 0 If the pixel value of fore ground image matches with COLVAL the pixel from back ground image is displayed only in OSD area 1 If the pixel value of back ground matches with COLVAL the pixel from fore ground image is displayed only in OSD area 0 COMPKEY 23 0 Each bit is corre...

Page 421: ...layed only in OSD area 0 COMPKEY 23 0 Each bit corresponds to the COLVAL 23 0 If some position bit is set then that position bit of COLVAL will be ignored in the fore ground or back ground match 0 Note Set BLD_PIX 1 ALPHA_SEL 0 to use alpha blending using color key WIN2 Color key 1 Register Register Address R W Description Reset Value W2KEYCON1 0x7710014C R W Color key value transparent value regi...

Page 422: ...000 0 W3KEYCON1 Bit Description Initial state COLVAL 23 0 Color key value for the transparent pixel effect 0 Win4 Color Key 0 Register Register Address R W Description Reset Value W4KEYCON0 0x77100158 R W Color key control register 0x00000 W4KEYCON0 Bit Description Initial state KEYBLEN 26 Color Key Chroma key Enable control 0 disable blending operation disable 1 Blending using ALPHA0_x for non ke...

Page 423: ..._000 0 W4KEYCON1 Bit Description Initial state COLVAL 23 0 Color key value for the transparent pixel effect 0 Note COLVAL and COMPKEY use 24bit color data at all BPP mode BPP24 mode 24 bit color value is valid A COLVAL Red COLVAL 23 17 Green COLVAL 15 8 Blue COLVAL 7 0 B COMPKEY Red COMPKEY 23 17 Green COMPKEY 15 8 Blue COMPKEY 7 0 BPP16 5 6 5 mode 16 bit color value is valid A COLVAL Red COLVAL 2...

Page 424: ...ntrol 00 8bit 01 6bit 10 5bit 0 GDithPos 4 3 Green Dither bit control 00 8bit 01 6bit 10 5bit 0 BDithPos 2 1 Blue Dither bit control 00 8bit 01 6bit 10 5bit 0 DITHEN_F 0 Dithering Enable bit 0 dithering disable 1 dithering enable 0 WIN0 Color MAP Register Address R W Description Reset Value WIN0MAP 0x77100180 R W Window color control 0x00000 WIN0MAP Bit Description Initial state MAPCOLEN_ F 24 Win...

Page 425: ...Reset Value WIN2MAP 0x77100188 R W Window color control 0x00000 WIN2MAP Bit Description Initial state MAPCOLEN_F 24 Window s color mapping control bit If this bit is enabled then Video DMA will stop and MAPCOLOR will be appear on back ground image instead of original image 0 disable 1 enable 0 MAPCOLOR 23 0 Color Value 0 WIN3 Color MAP Register Address R W Description Reset Value WIN3MAP 0x7710018...

Page 426: ...eset Value WPALCON 0x771001A0 R W Window Palette control register 0x0000_0000 WPALCON Bit Description Initial state PALUPDATEEN 9 0 Normal Mode 1 Enable Palette Update 0 W4PAL 8 This bit determines the size of the palette data format of Window 4 0 16 bit 5 6 5 1 16 bit A 5 5 5 0 W3PAL 7 This bit determines the size of the palette data format of Window 3 0 16 bit 5 6 5 1 16 bit A 5 5 5 0 W2PAL 6 Th...

Page 427: ...Status Read Only 0 Indicate I80 frame transfer is not finished 1 Indicate I80 frame transfer finished Clear Condition Read or New Frame Start Only when TRGMODE is 1 0 SWTRGCMD 1 1 Software Triggering Command Write Only Only when TRGMODE is 1 0 TRGMODE 0 Software Trigger enable control 0 Disable 1 Enable 0 LCD I80 Interface Control 0 Register Address R W Description Reset Value I80IFCONA0 0x771001B...

Page 428: ...e RS Signal 0 RS signal is low during video data transfer 1 RS signal is high during video data transfer 0 1 Reserved 0 I80IFEN 0 LCD I80 Interface control 0 Disable 1 Enable 0 LCD I80 Interface Control 1 Register Address R W Description Reset Value I80IFCONB0 0x771001B8 R W I80 Interface control for Main LDI LCD 0x0 I80IFCONB1 0x771001BC R W I80 Interface control for Sub LDI LCD 0x0 I80IFCONBx Bi...

Page 429: ...face Command Control 0 0x00000 LDI_CMDCO N0 Bit Description Initial state 31 24 Reserved CMD11_EN 23 22 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Command Enable 00 CMD10_EN 21 20 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Command Enable 00 CMD9_EN 19 18 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Au...

Page 430: ...ble 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Command Enable 00 CMD4_EN 9 8 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Command Enable 00 CMD3_EN 7 6 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Command Enable 00 CMD2_EN 5 4 00 Disable 01 Normal Command Enable 10 Auto Command Enable 11 Normal and Auto Comma...

Page 431: ... CMD10_RS 10 Command 10 RS control 0 CMD9_RS 9 Command 9 RS control 0 CMD8_RS 8 Command 8 RS control 0 CMD7_RS 7 Command 7 RS control 0 CMD6_RS 6 Command 6 RS control 0 CMD5_RS 5 Command 5 RS control 0 CMD4_RS 4 Command 4 RS control 0 CMD3_RS 3 Command 3 RS control 0 CMD2_RS 2 Command 2 RS control 0 CMD1_RS 1 Command 1 RS control 0 CMD0_RS 0 Command 0 RS control 0 I80 System Interface Manual Comma...

Page 432: ...ace nWE Signal control 0 Disable High 1 Enable Low 0 SCOMEN 0 LCD I80 System Interface Command Mode Enable 0 Disable Normal Mode 1 Enable Manual Command Mode 0 I80 System Interface Manual Command Control 1 Register Address R W Description Reset Value SIFCCON1 0x771001E4 R W I80 System Interface Manual Command Data Write Control 0x0 SIFCCON1 Bit Description Initial State SYS_WDATA 17 0 LCD I80 Syst...

Page 433: ...MD7 0x7710029c R W I80 Interface Command 7 0x0 LDI_CMD8 0x771002A0 R W I80 Interface Command 8 0x0 LDI_CMD9 0x771002A4 R W I80 Interface Command 9 0x0 LDI_CMD10 0x771002A8 R W I80 Interface Command 10 0x0 LDI_CMD11 0x771002AC R W I80 Interface Command 11 0x0 I80IFCONx Bit Description Initial State LDI_CMD 17 0 LDI command 0 Window 2 s Palette Data Register Address R W Description Reset Value W2PDA...

Page 434: ...89 0x77100330 R W Window 3 Palette Data of the Index 8 9 0x0 W3PDATAAB 0x77100334 R W Window 3 Palette Data of the Index A B 0x0 W3PDATACD 0x77100338 R W Window 3 Palette Data of the Index C D 0x0 W3PDATAEF 0x7710033C R W Window 3 Palette Data of the Index E F 0x0 W3PDATAxx Bit Description Initial State ODD_VAL 31 16 Lut Value register 0 EVEN_VAL 15 0 Lut Value register 0 Window 4 s Palette Data R...

Page 435: ... associated errata are not yet available Specifications and information herein are subject to change without notice WIN1 Palette Ram Access Address not SFR Index Address R W Description Reset Value 00 0x77100800 R W Window 1 Palette entry 0 address undefined 01 0x77100804 R W Window 1 Palette entry 1 address undefined FF 0x77100BFC R W Window 1 Palette entry 255 address undefined ...

Page 436: ...ctions and usage of the Postprocessor interface of the S3C6400 OVERVIEW The Post processor administers the video graphic scale video format conversion and color space conversion It is composed of Data Path DMA controller and Register files as shown in the Figure 15 1 Figure 15 1 Block Diagram of Post Processor Register Files DMA Controller Scale Format Conversion CSC Pre Scale Main Scale Pre Scale...

Page 437: ...420 422 format z Graphic input format 16 bit 565format or 24 bit z Graphics Output format to Memory 16 bit 565 format 24 bit graphic data progressive only z Video Output format to Memory YCbCr420 YCbCr422 z Output format to external FIFO YCbCr444 RGB 30 bit for interlace and progressive z FreeRun Mode Operation z Programmable source and destination image size up to 2048 2048 resolution z Programma...

Page 438: ...or two output modes such as DMA mode and FIFO mode are available as shown in the following Figure 15 2 In FIFO mode if LCDPathEnable 1 For more information refer to chapter 6 Register File List destination image is transferred to the FIFO in display controller or some other IP with FIFO interface without additional memory bandwidth such as POST to Memory and Memory to Display Controller The source...

Page 439: ...lied within unified address space as described in Figure 15 3 b Byte interleaving order of YCbCr422 source image can be selected either from YCbYCr or CbYCrY as shown in case B and C of Figure 15 3 b and Figure 15 4 Byte order of RGB 24 bit and half word order of RGB 16 bit are described in case D and E of Figure 15 3 b and Figure 15 4 In both cases of YCbCr420 and YCbCr422 source image format whe...

Page 440: ... 1 InRGB Format MODE 15 0 InYCbCr Format Video Graphic Format Data Format in Fig15 3 and 4 1 0 0 1 X 420 YCbCr Format A 0 0 1 1 00 10 422 YCbYCr Format B B 0 0 1 1 01 11 422 CbYCrY Format C C 0 1 1 1 X RGB 24 bit true color D 0 1 1 0 X RGB 16 bit Format E Table 15 1 b Mode configuration for video graphic destination format and the corresponding data format Description MODE 18 OutRGB MODE 17 DST420...

Page 441: ... N Case B Y N 1 Cb N Y N Cr N Case B Y N 1 Cr N Y N Cb N Case C Cb N Y N 1 Cr N Y N Case C Cr N Y N 1 Cb N Y N Case D Don t Care RN GN BN 31 27 26 21 20 16 15 11 10 5 4 0 Case E R 4 0 G 5 0 B 4 0 R 4 0 G 5 0 B 4 0 Pixel N 1 Pixel N Figure 15 4 Byte and half word organization Block Diagram MSB LSB Y Cb Cr 1 Frame Video Data Or 1 Frame Y Y Y Y Cb Cb Cb Cb Cr Cr Cr Cr Memory Space WORD x R G B D Pixe...

Page 442: ...Lists The interlace control bit is enabled only if LCDPathEnable 1 otherwise its value is unaffected to DMA mode operation which support only progressive Even if an interlaced scan mode is enabled LCDPathEnable 1 and Interlace 1 per frame management which consists of even field and odd filed operates automatically This means that user interruption is unnecessary to inter field switching in the sam...

Page 443: ... registers of pre scaled image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to the following equations If SRC_Width 64 DST_Width Exit 1 Out Of Horizontal Scale Range else if SRC_Width 32 DST_Width PreScale_H_Ratio 32 H_Shift 5 else if SRC_Width 16 DST_Width PreScale_H_Ratio 16 H_Shift 4 else if SRC_Width 8 DST_Width PreScale_H_Ratio 8 H_Shift 3 else if SRC_...

Page 444: ...on herein are subject to change without notice else if SRC_Height 16 DST_Height PreScale_V_Ratio 16 V_Shift 4 else if SRC_Height 8 DST_Height PreScale_V_Ratio 8 V_Shift 3 else if SRC_Height 4 DST_Height PreScale_V_Ratio 4 V_Shift 2 else if SRC_Height 2 DST_Height PreScale_V_Ratio 2 V_Shift 1 else PreScale_V_Ratio 1 V_Shift 0 PreScale_DSTHeight SRC_Height PreScale_V_Ratio dy SRC_Height 8 DST_Height...

Page 445: ... such as a RGB graphic format or an YCbCr422 format only Y component of three source components is valid and two chroma address components are invalid as shown in Figure 15 6 b If a destination image is stored in the non interleaved format such as YCbCr420 all source address components RGB oCb oCr are valid as shown in Figure 15 6 a If a source image is stored by the interleaved format such as a R...

Page 446: ...t of Y RGB ADDRStart_Y SRC_Width SRC_Height ByteSize_Per_Pixel Offset_Y SRC_Height 1 ADDREnd_Cb Valid for YCbCr420 source format ADDRStart_Cb Memory size for the component of Cb ADDRStart_Cb SRC_Width 2 SRC_Height 2 ByteSize_Per_Pixel Offset_Cb SRC_Height 2 1 ADDREnd_ Cr Valid for YCbCr420 source format ADDRStart_ Cr Memory size for the component of Cr ADDRStart_Cr SRC_Width 2 SRC_Height 2 ByteSiz...

Page 447: ...erization data and associated errata are not yet available Specifications and information herein are subject to change without notice Where Offset_Y Cb Cr RGB Memory size for offset per a horizontal line Number of pixel or sample in horizontal offset ByteSize_Per_Pixel or Sample ByteSize_Per_Pixel 1 for YCbCr420 2 for 16 bit RGB and YcbCr422 4 for 24 bit RGB ...

Page 448: ...fset address is used for the following two situations One is to fetch some parts of source image in order to zoom in out as shown in Figure 15 7 a The other is to restore destination image for PIP picture in picture applications as shown in Figure 15 7 b The word boundary constraints must be satisfied in both cases a b Figure 15 7 Offset address for a Source image for zoom in out operation and b D...

Page 449: ...errupt controller must be cleared by the interrupt service routine The polling POSTENVID is used to detect the end of the operation Figure 15 8 Start and termination of POST PROCESSOR operation AutoLoadEnable 0 Block Diagram 5 2 Free Run Mode To activatethe new frame management scheme of free run operation you must set AutoLoadEnable bit to 1 In this mode user can pre define the next frame related...

Page 450: ...ADDRStart_Y 0x77000020 R W DMA Buffer 0 Start address for source Y or RGB component 0x20000000 ADDRStart_Cb 0x77000024 R W DMA Buffer 0 Start address for source Cb component 0x20000000 ADDRStart_Cr 0x77000028 R W DMA Buffer 0 Start address for source Cr component 0x20000000 ADDRStart_RGB 0x7700002C R W DMA Buffer 0 Start address for destination Y or RGB component 0x20000000 ADDREnd_Y 0x77000030 R ...

Page 451: ...for source Cb component 0x20006300 NxtADDREnd_Cr 0x7700006C R W Next Frame Buffer 1 DMA End address for source Cr component 0x20006300 NxtADDREnd_RGB 0x77000070 R W Next Frame Buffer 1 DMA End address for destination Y or RGB component 0x20006300 ADDRStart_oCb 0x77000074 R W DMA Buffer 0 Start address for destination Cb component 0x20000000 ADDRStart_oCr 0x77000078 R W DMA Buffer 0 Start address f...

Page 452: ... full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NxtADDREnd_oCr 0x77000098 R W Next Frame DMA Buffer 1 End address for destination Cr component 0x20006300 POSTENVID 0x7700009C R W Enable Video Processing 0x0 MODE_2 0x770000A0 R W Mode Register 2 0x0 ...

Page 453: ...he clock source as direct or divide using CLKVAL_F register 0 Direct clock frequency of TSCLK frequency of Clock source 1 Divided by CLKVAL_F 0 CLKSEL_F 22 21 Select the Video Clock source 00 HCLK 01 PLL Ext Clock input 10 reserved 11 27MHz Ext Clock input 0 OutYCbCrFormat 20 19 It determines the byte organization of word data when the destination image is interleaved YCbCr format For more informa...

Page 454: ...n the processing of the current frame is finished 0 disable 1 enable 0 POSTINT 6 Interrupt Pending Bit If INTEN is enabled it is automatically asserted right after finishing operation of the current frame It must be cleared by interrupt service routine 0 disable 1 enable 0 IRQ_LEVEL 5 It determines the interrupt generation scheme 1 for level interrupt must be 1 0 OutRGBFormat 4 It determines the o...

Page 455: ...nary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 15 10 Internal clock scheme Block Diagram ...

Page 456: ...al 0x0 PreScale_Ratio Bit Description Initial State PreScale_V_Ratio 13 7 Pre scale ratio for vertical direction For more information refer to chapter 15 3 0x0 PreScale_H_Ratio 6 0 Pre scale ratio for horizontal direction For more information refer to chapter 15 3 0x0 Pre Scale Image Size Register Register Address R W Description Reset Value PreScaleImgSize 0x77000008 R W Pre Scaled image size 0x0...

Page 457: ... chapter 15 3 0x0 SRCWidth 11 0 Source image width For more information refer to chapter 15 3 0x0 Horizontal Main Scale Ratio Register Register Address R W Description Reset Value MainScale_H_R atio 0x77000010 R W Main scale ratio for horizontal direction 0x0 SRC_Width Bit Description Initial State MainScale_H_R atio 8 0 Main scale ratio for horizontal direction For more information refer to chapt...

Page 458: ...ption Reset Value DSTImgSize 0x77000018 R W Destination image size 0x0 SRCImgSize Bit Description Initial State DSTHeight 23 12 Destination image height For more information refer to chapter 15 3 0x0 DSTWidth 11 0 Destination image width For more information refer to chapter 15 3 0x0 Pre Scale Shift Factor Register Register Address R W Description Reset Value PreScale_SHFactor 0x7700001C R W Pre s...

Page 459: ...escription Reset Value ADDRStart_Y 0x77000020 R W 30 0 DMA Buffer 0 Start address for source Y or RGB component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_Cb 0x77000024 R W 30 0 DMA Buffer 0 Start address for source Cb component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_Cr 0x77000028 R W 30 0 DMA Buffer 0 Start address for source Cr component ...

Page 460: ...or source Y or RGB component For more information refer to chapter 15 4 0x20006300 Register Address R W Bit Description Reset Value ADDREnd_Cb 0x77000034 R W 30 0 DMA Buffer 0 End address for source Cb component For more information refer to chapter 15 4 0x20006300 Register Address R W Bit Description Reset Value ADDREnd_Cr 0x77000038 R W 30 0 DMA Buffer 0 End address for source Cr component For m...

Page 461: ...component for fetching source image For more information refer to chapter 15 4 0x0 Register Address R W Bit Description Reset Value Offset_Cb 0x77000044 R W 23 0 Offset of Cb component for fetching source image For more information refer to chapter 15 4 0x0 Register Address R W Bit Description Reset Value Offset_Cr 0x77000048 R W 23 0 Offset of Cr component for fetching source image For more infor...

Page 462: ...NxtADDRStart_Y 0x77000054 R W 30 0 Next Frame Buffer 1 DMA Start address for source Y or RGB component 0x20000000 Register Address R W Bit Description Reset Value NxtADDRStart_Cb 0x77000058 R W 30 0 Next Frame Buffer 1 DMA Start address for source Cb component 0x20000000 Register Address R W Bit Description Reset Value NxtADDRStart_Cr 0x7700005C R W 30 0 Next Frame Buffer 1 DMA Start address for s...

Page 463: ... Y or RGB component For more information refer to chapter 15 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_Cb 0x77000068 R W 30 0 Next Frame Buffer 1 DMA End address for source Cb component For more information refer to chapter 15 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_Cr 0x7700006C R W 30 0 Next Frame Buffer 1 DMA End address for source...

Page 464: ...er 0 Start address for destination Cb component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_oCr 0x77000078 R W 30 0 DMA Buffer 0 Start address for destination Cr component 0x20000000 DMA End Address Register for Output Cb and Cr Register Address R W Bit Description Reset Value ADDREnd_oCb 0x7700007C R W 30 0 DMA Buffer 0 End address for destination Cb component For more i...

Page 465: ... of Cb component for fetching destination image For more information refer to chapter 15 4 0x0 Register Address R W Bit Description Reset Value Offset_oCr 0x77000088 R W 23 0 Offset of Cr component for fetching destination image For more information refer to chapter 15 4 0x0 Next Frame DMA Start Address Register for Output Cb and Cr Register Address R W Bit Description Reset Value NxtADDRStart_oCb...

Page 466: ...ion refer to chapter 15 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_oCr 0x77000098 R W 30 0 Next Frame DMA Buffer 1 End address for destination Cr component For more information refer to chapter 15 4 0x20006300 POSTENVID Register for Enable Video Processing Register Address R W Bit Description Reset Value POSTENVID 0x7700009C R W 31 Enable Video Processing It enables t...

Page 467: ... State ADDR_CH_DIS 4 Next Address Change Disable in Free Run Mode Software Trigger Mode When the current frame is completely finished and ADDR_CH_DIS is 0 Next frame address set of NxtADDRXXX is copied into the current frame address set of ADDRXXX But if ADDR_CH_DIS is 1 ADDRXXX is not changed For more information refer to chapter 15 5 2 0 Address Change Enable 1 Address Change Disable 0 BC_SEL 3 ...

Page 468: ...3C6400 OVERVIEW TV Scaler is similar to Post Processor except FIFO size targeted SD TV and Input FIFO Mode Figure 16 2 The TV Scaler performs video graphic scale video format conversion and color space conversion It is composed of Data Path DMA controller and Register files as shown in the Figure 16 1 Figure 16 1 Block Diagram of TV Scaler Register Files DMA Controller Scale Format Conversion CSC ...

Page 469: ...16 bit 565format or 24 bit z Graphics Output format to Memory 16 bit 565 format 24 bit graphic data progressive only z Video Output format to Memory YCbCr420 YCbCr422 z Input format to external FIFO YCbCr444 RGB 24 bit for interlace and progressive z Output format to external FIFO YCbCr444 RGB 30 bit for interlace and progressive z FreeRun Mode Operation z Programmable destination image size up to...

Page 470: ...able 1 For more information refer to chapter 6 Register File List destination image is transferred to the FIFO in display controller or some other IP with FIFO interface without additional memory bandwidth such as TV SCALER to Memory and Memory to Display Controller The source image format and the destination image format are described in chapter 2 2 FIFO mode DMA Mode FIFO Mode Video Graphic 1 Fr...

Page 471: ...d within unified address space as described in Figure 16 3 b Byte interleaving order of YCbCr422 source image can be selected either from YCbYCr or CbYCrY as shown in case B and C of Figure 16 3 b and Figure 16 4 Byte order of RGB 24 bit and half word order of RGB 16 bit are described in case D and E of Figure 16 3 b and Figure 16 4 In both cases of YCbCr420 and YCbCr422 source image format whethe...

Page 472: ...MODE 1 InRGB Format MODE 15 0 InYCbCr Format Video Graphic Format Data Format in Fig16 3and 4 1 0 0 1 420 YCbCr Format A 0 0 1 1 00 10 422 YCbYCr Format B B 0 0 1 1 01 11 422 CbYCrY Format C C 0 1 1 1 RGB 24 bit true color D 0 1 1 0 RGB 16 bit Format E Table 16 1 b Mode configuration for video graphic destination format and the corresponding data format Description MODE 18 OutRGB MODE 17 DST420 MO...

Page 473: ... Case B Y N 1 Cb N Y N Cr N Case B Y N 1 Cr N Y N Cb N Case C Cb N Y N 1 Cr N Y N Case C Cr N Y N 1 Cb N Y N Case D Don t Care RN GN BN 31 27 26 21 20 16 15 11 10 5 4 0 Case E R 4 0 G 5 0 B 4 0 R 4 0 G 5 0 B 4 0 Pixel N 1 Pixel N Figure 16 4 Byte and half word organization Block Diagram MSB LSB Y Cb Cr 1 Frame Video Data Or 1 Frame Y Y Y Y Cb Cb Cb Cb Cr Cr Cr Cr Memory Space WORD x R G B D PixelN...

Page 474: ...ined in chapter 6 Register Files Lists The interlace control bit is enabled only if LCDPathEnable 1 otherwise its value is unaffected to DMA mode operation which support only progressive Even if an interlaced scan mode is enabled LCDPathEnable 1 and Interlace 1 per frame management which consists of even field and odd filed operates automatically This means that user interruption is unnecessary to...

Page 475: ... Figure 16 5 Source destination image size Block Diagram The other control registers of pre scaled image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to the following equations If SRC_Width 64 DST_Width Exit 1 Out Of Horizontal Scale Range else if SRC_Width 32 DST_Width PreScale_H_Ratio 32 H_Shift 5 else if SRC_Width 16 DST_Width PreScale_H_Ratio 16 H_Shift...

Page 476: ...thout notice else if SRC_Height 32 DST_Height PreScale_V_Ratio 32 V_Shift 5 else if SRC_Height 16 DST_Height PreScale_V_Ratio 16 V_Shift 4 else if SRC_Height 8 DST_Height PreScale_V_Ratio 8 V_Shift 3 else if SRC_Height 4 DST_Height PreScale_V_Ratio 4 V_Shift 2 else if SRC_Height 2 DST_Height PreScale_V_Ratio 2 V_Shift 1 else PreScale_V_Ratio 1 V_Shift 0 PreScale_DSTHeight SRC_Height PreScale_V_Rat...

Page 477: ...ormat such as a RGB graphic format or an YCbCr422 format only Y component of three source components is valid and two chroma address components are invalid as shown in Figure 16 6 b If a destination image is stored in the non interleaved format such as YCbCr420 all source address components RGB oCb oCr are valid as shown in Figure 16 6 a If a source image is stored by the interleaved format such a...

Page 478: ...of Y RGB ADDRStart_Y SRC_Width SRC_Height ByteSize_Per_Pixel Offset_Y SRC_Height 1 ADDREnd_Cb Valid for YCbCr420 source format ADDRStart_Cb Memory size for the component of Cb ADDRStart_Cb SRC_Width 2 SRC_Height 2 ByteSize_Per_Pixel Offset_Cb SRC_Height 2 1 ADDREnd_ Cr Valid for YCbCr420 source format ADDRStart_ Cr Memory size for the component of Cr ADDRStart_Cr SRC_Width 2 SRC_Height 2 ByteSize_...

Page 479: ...zation data and associated errata are not yet available Specifications and information herein are subject to change without notice Where Offset_Y Cb Cr RGB Memory size for offset per a horizontal line Number of pixel or sample in horizontal offset ByteSize_Per_Pixel or Sample ByteSize_Per_Pixel 1 for YCbCr420 2 for 16 bit RGB and YcbCr422 4 for 24 bit RGB ...

Page 480: ...et address is used for the following two situations One is to fetch some parts of source image in order to zoom in out as shown in Figure 16 7 a The other is to restore destination image for PIP picture in picture applications as shown in Figure 16 7 b The word boundary constraints must be satisfied in both cases a b Figure 16 7 Offset address for a source image for zoom in out operation and b Des...

Page 481: ...rrupt controller must be cleared by the interrupt service routine The polling POSTENVID is also used to detect the end of the operation Figure 16 8 Start and termination of TV SCALER operation AutoLoadEnable 0 5 2 Free Run Mode To activatethe new frame management scheme of free run operation you must set AutoLoadEnable bit to 1 In this mode user can pre define the next frame related address set of...

Page 482: ...ion 0x0 DSTImgSize 0x76300018 R W Destination image size 0x0 PreScale_SHFactor 0x7630001C R W Pre scale shift factor 0x0 ADDRStart_Y 0x76300020 R W DMA Buffer 0 Start address for source Y or RGB component 0x20000000 ADDRStart_Cb 0x76300024 R W DMA Buffer 0 Start address for source Cb component 0x20000000 ADDRStart_Cr 0x76300028 R W DMA Buffer 0 Start address for source Cr component 0x20000000 ADDR...

Page 483: ...Cb component 0x20000000 NxtADDRStart_Cr 0x7630005C R W Next Frame Buffer 1 DMA Start address for source Cr component 0x20000000 NxtADDRStart_RGB 0x76300060 R W Next Frame Buffer 1 DMA Start address for destination Y or RGB component 0x20000000 NxtADDREnd_Y 0x76300064 R W Next Frame Buffer 1 DMA End address for source Y or RGB component 0x20006300 NxtADDREnd_Cb 0x76300068 R W Next Frame Buffer 1 DM...

Page 484: ...hing destination image 0x0 Offset_oCr 0x76300088 R W Offset of Cr component for fetching destination image 0x0 NxtADDRStart_oCb 0x7630008C R W Next Frame DMA Buffer 1 Start address for destination Cb component 0x20006300 NxtADDRStart_oCr 0x76300090 R W Next Frame DMA Buffer 1 Start address for destination Cr component 0x20006300 NxtADDREnd_oCb 0x76300094 R W Next Frame DMA Buffer 1 End address for...

Page 485: ... 0 CLKDIR 23 Select the clock source as direct or divide using CLKVAL_F register 0 Direct clock frequency of TSCLK frequency of Clock source 1 Divided by CLKVAL_F 0 CLKSEL_F 22 21 Select the Video Clock source 00 HCLK 01 PLL Ext Clock input 10 reserved 11 27MHz Ext Clock input 0 OutYCbCrFormat 20 19 It determines the byte organization of word data when the destination image is interleaved YCbCr fo...

Page 486: ...the processing of the current frame is finished 0 disable 1 enable 0 POSTINT 6 Interrupt Pending Bit If INTEN is enabled it is automatically asserted right after finishing operation of the current frame It must be cleared by interrupt service routine 0 disable 1 enable 0 IRQ_LEVEL 5 It determines the interrupt generation scheme 1 for level interrupt must be 1 0 OutRGBFormat 4 It determines the out...

Page 487: ...y product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 16 10 Internal clock scheme Block Diagram ...

Page 488: ...0x0 PreScale_Ratio Bit Description Initial State PreScale_V_Ratio 13 7 Pre scale ratio for vertical direction For more information refer to chapter 16 3 0x0 PreScale_H_Ratio 6 0 Pre scale ratio for horizontal direction For more information refer to chapter 16 3 0x0 Pre Scale Image Size Register Register Address R W Description Reset Value PreScaleImgSize 0x76300008 R W Pre Scaled image size 0x0 Pr...

Page 489: ...hapter 16 3 0x0 SRCWidth 11 0 Source image width For more information refer to chapter 16 3 0x0 Horizontal Main Scale Ratio Register Register Address R W Description Reset Value MainScale_H_R atio 0x76300010 R W Main scale ratio for horizontal direction 0x0 SRC_Width Bit Description Initial State MainScale_H_R atio 8 0 Main scale ratio for horizontal direction For more information refer to chapter...

Page 490: ...on Reset Value DSTImgSize 0x76300018 R W Destination image size 0x0 SRCImgSize Bit Description Initial State DSTHeight 23 12 Destination image height For more information refer to chapter 16 3 0x0 DSTWidth 11 0 Destination image width For more information refer to chapter 16 3 0x0 Pre Scale Shift Factor Register Register Address R W Description Reset Value PreScale_SHFactor 0x7630001C R W Pre scal...

Page 491: ...cription Reset Value ADDRStart_Y 0x76300020 R W 30 0 DMA Buffer 0 Start address for source Y or RGB component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_Cb 0x76300024 R W 30 0 DMA Buffer 0 Start address for source Cb component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_Cr 0x76300028 R W 30 0 DMA Buffer 0 Start address for source Cr component 0x...

Page 492: ... source Y or RGB component For more information refer to chapter 16 4 0x20006300 Register Address R W Bit Description Reset Value ADDREnd_Cb 0x76300034 R W 30 0 DMA Buffer 0 End address for source Cb component For more information refer to chapter 16 4 0x20006300 Register Address R W Bit Description Reset Value ADDREnd_Cr 0x76300038 R W 30 0 DMA Buffer 0 End address for source Cr component For mor...

Page 493: ...mponent for fetching source image For more information refer to chapter 16 4 0x0 Register Address R W Bit Description Reset Value Offset_Cb 0x76300044 R W 23 0 Offset of Cb component for fetching source image For more information refer to chapter 16 4 0x0 Register Address R W Bit Description Reset Value Offset_Cr 0x76300048 R W 23 0 Offset of Cr component for fetching source image For more informa...

Page 494: ...tADDRStart_Y 0x76300054 R W 30 0 Next Frame Buffer 1 DMA Start address for source Y or RGB component 0x20000000 Register Address R W Bit Description Reset Value NxtADDRStart_Cb 0x76300058 R W 30 0 Next Frame Buffer 1 DMA Start address for source Cb component 0x20000000 Register Address R W Bit Description Reset Value NxtADDRStart_Cr 0x7630005C R W 30 0 Next Frame Buffer 1 DMA Start address for sou...

Page 495: ... or RGB component For more information refer to chapter 16 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_Cb 0x76300068 R W 30 0 Next Frame Buffer 1 DMA End address for source Cb component For more information refer to chapter 16 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_Cr 0x7630006C R W 30 0 Next Frame Buffer 1 DMA End address for source C...

Page 496: ... 0 Start address for destination Cb component 0x20000000 Register Address R W Bit Description Reset Value ADDRStart_oCr 0x76300078 R W 30 0 DMA Buffer 0 Start address for destination Cr component 0x20000000 DMA End Address Register for Output Cb and Cr Register Address R W Bit Description Reset Value ADDREnd_oCb 0x7630007C R W 30 0 DMA Buffer 0 End address for destination Cb component For more inf...

Page 497: ... Cb component for fetching destination image For more information refer to chapter 16 4 0x0 Register Address R W Bit Description Reset Value Offset_oCr 0x76300088 R W 23 0 Offset of Cr component for fetching destination image For more information refer to chapter 16 4 0x0 Next Frame DMA Start Address Register for Output Cb and Cr Register Address R W Bit Description Reset Value NxtADDRStart_oCb 0x...

Page 498: ...tion refer to chapter 16 4 0x20006300 Register Address R W Bit Description Reset Value NxtADDREnd_oCr 0x76300098 R W 30 0 Next Frame DMA Buffer 1 End address for destination Cr component For more information refer to chapter 16 4 0x20006300 POSTENVID Register for Enable Video Processing Register Address R W Bit Description Reset Value POSTENVID 0x7630009C R W 31 Enable Video Processing It turns on...

Page 499: ...n 00 TV Encoder output 01 FIMD WIN1 1x FIMD WIN2 00 ADDR_CH_DIS 4 Next Address Change Disable in Free Run Mode Software Trigger Mode When the current frame is completely finished and ADDR_CH_DIS is 0 Next frame address set of NxtADDRXXX is copied into the current frame address set of ADDRXXX But if ADDR_CH_DIS is 1 ADDRXXX is not changed For more information refer to chapter 16 5 2 0 Address Chang...

Page 500: ...Second it supports the image display of various size There are full wide and original mode Additionally TV Encoder in S3C6400 supports analog composite out and S video out FEATURE Built in the MIE Mobile Image Enhancer engine Black White Stretch Blue Stretch Flesh Tone Correction Dynamic Horizontal Peaking LTI Black and White Noise reduction Contrast Sharpness Gamma and Brightness Control It is po...

Page 501: ... not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM Image Enhancer LPF LPF LPF Sub Carrier Gen DAC DAC Macrovision Sync Gen Y C Sin Cos Y CVBS C TV Scaler Enhancing Encoding Block TV Controller FIFO 2048 depth Timing Generator SFR Control Block BUS Control Signal Data Signal Data Signal Control Signal Figure 17 1 TV Encoder Block Diagram ...

Page 502: ...of a image enhancing by controlling Black White Stretch Gamma Bright Contrast and so on We can get the image which is reinforced with some effect And then the encoder generated TV signal which is ITU R BT 656 format DATA PATHS BUS Figure 17 2 TV Encoder Data Path Concept To display the different image at LCD and TV there are two paths Post Processor Display controller LCD panel path 1 in figure Da...

Page 503: ...vel 100 IRE 7 5 IRE 40 IRE Figure 17 3 Composition of Analog Composite Signal Figure 17 3 shows horizontal timing In X axis for TV composite out it divide 3 timing parts It is Back Porch Active and Front Porch Back Porch and Front Porch are to synchronize signal And Active Region contains valid data In Y axis for TV composite out it contains luminance and chrominance component DC level in Figure 1...

Page 504: ...L BANDWIDTH 6 MHZ NTSC J LINE FIELD 525 59 94 FH 15 734 KHZ FV 59 94 HZ FSC 3 579545 MHZ BLANKING SETUP 0 IRE VIDEO BANDWIDTH 4 2 MHZ AUDIO CARRIER 4 5 MHZ CHANNEL BANDWIDTH 6 MHZ NTSC 4 43 LINE FIELD 525 59 94 FH 15 734 KHZ FV 59 94 HZ FSC 4 43361875 MHZ BLANKING SETUP 7 5 IRE VIDEO BANDWIDTH 4 2 MHZ AUDIO CARRIER 4 5 MHZ CHANNEL BANDWIDTH 6 MHZ Figure 17 4 Common NTSC System Types of NTSC are NT...

Page 505: ... 5 MHZ AUDIO CARRIER 5 5 MHZ CHANNEL BANDWIDTH B 7 MHZ B1 G H 8 MHZ M LINE FIELD 525 59 94 FH 15 734 KHZ FV 59 94 HZ FSC 3 57561149 MHZ BLANKING SETUP 7 5 IRE VIDEO BANDWIDTH 4 2 MHZ AUDIO CARRIER 4 5 MHZ CHANNEL BANDWIDTH 6 MHZ D LINE FIELD 625 50 FH 15 625 KHZ FV 50 HZ FSC 4 43361875 MHZ BLANKING SETUP 0 IRE VIDEO BANDWIDTH 6 0 MHZ AUDIO CARRIER 6 5 MHZ CHANNEL BANDWIDTH 8 MHZ N LINE FIELD 625 5...

Page 506: ...Back porch Vertical Front porch 858 60Hz or 864 50Hz 1440 720 60Hz or 50Hz 480 60Hz or 576 50Hz Figure 17 6 Composition of TV screen In 60Hz type The size of a frame is 858x525 This contains synchronous and real image region Real image is 720x480 However figure 17 6 is not 720 but 1440 Because TV encoder which embedded S3C6400 needs double horizontal data rate It uses to enhance image Otherwise Th...

Page 507: ...zontal timing relation The horizontal line is composed of active and synchronous region In 60Hz a line consists of active 1440 pixel front porch 32 pixel and back porch containing synch width 244 pixel Also It is possible to configure horizontal under scan size Horizontal enhancer offset value means that enhance engine which embedded TV encoder needs 26 clocks to enhance image So we transmit data ...

Page 508: ...at are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice REQUESTED VERTICAL TIMING Figure 17 8 Requested Vertical Timing Diagram in 60Hz Figure 17 9 Requested Vertical Timing Diagram in 50Hz ...

Page 509: ...MNINOLOGY INPUT IMAGE ENERGY OUTPUT IMAGE ENERGY White Tilt Point Black Tilt Point Figure 17 10 The concept of Tilt Point in White and Black Stretch Tilt point means the inflection point in in out energy equation The equation is usually linear But if we makes inflection points in the equation we can get another resolution in in out relation For example if wide output range is covered by narrow inp...

Page 510: ... N0 1 Out side VBI reduce sync and blank N0 0 Within side VBI reduce sync and blank level N1 5 0 To indicate the first line where color stripe is appeared in field1 1 64 line 00000 1line N2 5 0 Interval of color stripe between the first and the second in field1 0 63 line N3 5 0 To indicate the first line where color stripe is appeared in field2 264 327 314 377 line N4 5 0 Interval of color stripe ...

Page 511: ...0 56us 0 07us N20 define property of zone 0 normal 1 modify N21 stype of modified zone Figure 17 11 Horizontal Timing Diagram for color stripe macrovision control Pseudo sync and AGC pulse control register Table 17 1 Registers table of pseudo sync and AGC pulse Register Description Note N8 5 3 Pseudo sync duration in format A N8 2 0 Pseudo sync duration in format B 2 12 reg 13 5M 525 2 8 reg 13 5M...

Page 512: ...0 14 AGC pulse type A B 7 21 line N13 0 7 on off control of format A N14 0 7 on off control of format B N9 5 3 The location of the first P S in format A N9 2 0 The location of the first P S in format B N8 5 3 Period of P S in format A N8 2 0 Period of P S in format B N10 5 3 Interval of P S in format A N10 2 0 Interval of P S in format B N10 7 4 The number of EOF pulse 0 15ea after Vsync de assert...

Page 513: ...00F0F Macrovision5 0x0405000A Macrovision5 0x0405000A AGC 4L Macrovision6 0x000003FF AGC 2L Macrovision6 0x000003FF Macrovision0 0x2115173E Macrovision0 0x1A2A2F3E Macrovision1 0x03050515 Macrovision1 0x03040236 Macrovision2 0x00231C19 Macrovision2 0x001D2524 Macrovision3 0x7E070FF8 Macrovision3 0x6DCF36B8 Macrovision4 0x01910EF0 Macrovision4 0x00701323 Macrovision5 0x02030705 Macrovision5 0x050A0...

Page 514: ...ta are not yet available Specifications and information herein are subject to change without notice DAC BOARD CONFIGURE GUIDE ZL 75 ohm ZS 150 ohm DAC Zo 75 X2 Zm Iout 6 6 mA Figure 17 13 DAC Board Guide It is the current drive DAC in S3C6400 Output current is 6 6mA So it has to load 150 ohm resistor And it is recommended to use AMP equipment Because it prevents electrical damage by ESD ...

Page 515: ...ackground control 0x00000110 BGHVAVCTRL 0x76200038 R W Background VAV HAV control 0xB400F000 ContraBright 0x76200044 R W Contrast Bright control 0x00000040 CbCrGainCTRL 0x76200048 R W Cb Cr gain control 0x00400040 DemoWinCTRL 0x7620004C R W Demo window control 0x00000010 FTCA 0x76200050 R W Flesh tone control 0x00D7008C BWGAIN 0x76200058 R W Black White stretch gain control 0x00000034 SharpCTRL 0x...

Page 516: ...ntroller control SFR set 0x00010000 TVCTRL Bit Description Reset Value 31 17 Reserved 0 INTFIFOUR 16 FIFO under run interrupt control 0 Disable 1 Enable 0x1 15 13 Reserved 0 INTStatus 12 FIFO under run status register If the register is high the FIFO under run interrupt is occurred If you want to clear the interrupt you also have to write high 0 11 9 Reserved 0 TVOUTTYPE 8 Select TV out type 0 Com...

Page 517: ...EG3 Register Address R W Description Reset Value HBPORCH 0x76200008 R W Horizontal back porch end point 0x008000F4 HBPORCH Bit Description Reset Value 31 24 Reserved 0 HSPW 23 16 Horizontal sync pulse width Default 0x80 128 NTSC PAL 0x80 15 11 Reserved 0 HBPD 10 0 Horizontal back porch end point NTSC 0xF4 244 PAL 0x108 264 0xF4 TVENCREG4 Register Address R W Description Reset Value HEnhOffset 0x76...

Page 518: ...ndow start point Default 0x0 0 0 TVENCREG6 Register Address R W Description Reset Value HDemoWinSize 0x76200014 R W Horizontal demo window size 0x05A00000 HDemoWinSize Bit Description Reset Value 31 27 Reserved 0 HDWEP 26 16 Horizontal demo window size Default 0x5A0 1440 0x5A0 15 11 Reserved 0 HDWSP 10 0 Horizontal demo window start point Default 0x0 0 0 TVENCREG7 Register Address R W Description ...

Page 519: ...CTRL Bit Description Reset Value 31 1 Reserved 0 PEDOff 0 Encoder pedestal control 0 Pedestal on NTSCM PALM 1 Pedestal off Even NTSCM PALM 0 TVENCREG9 Register Address R W Description Reset Value YCFilterBW 0x76200020 R W Y C filter bandwidth control 0x00000043 YCFilterBW Bit Description Reset Value 31 7 Reserved 0 YBW 6 4 Luminance bandwidth 3dB 0 6 0 MHz Recommended at S Video out 1 3 8 MHz 2 3 ...

Page 520: ...ment of 1 4063 0x00 0 phase shift 0x80 180 phase shift 0xFF 358 5938 phase shift 0 TVENCREG11 Register Address R W Description Reset Value FscCTRL 0x76200028 R W Fsc Sub Carrier Frequency control 0x00000000 FscCTRL Bit Description Reset Value 31 15 Reserved 0 FscCtrl 14 0 Fsc control Equation note FscCtrl 2 s Current DTO set value FscCtrl 14 0 2 9 0 TVENCREG12 Register Address R W Description Rese...

Page 521: ...Reserved 0 SME 8 Soft mixed enable 0 Disable 1 Enable soft mixed for background border 1 7 Reserved 0 BGCS 6 4 Background color select 0 Black 1 Blue 2 Red 3 Magenta 4 Green 5 Cyan 6 Yellow 7 White 1 BGYOFS 3 0 Background luminance offset 0 TVENCREG15 Register Address R W Description Reset Value BGHVAVCTRL 0x76200038 R W Background VAV HAV control 0xB400F000 BGHVAVCTRL Bit Description Reset Value ...

Page 522: ...y product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 17 14 The Calculation Method of Back ground ...

Page 523: ...set Value ContraBright 0x76200044 R W Contrast Bright control 0x00000040 ContraBright Bit Description Reset Value 31 24 Reserved 0 BRIGHT 23 16 Brightness control 2 s 0x7F Maximum brightness 0x80 Minimum brightness 0x00 15 8 Reserved 0 CONTRAST 7 0 Contrast gain control 0 4 0x40 TVENCREG19 Register Address R W Description Reset Value CbCrGainCTRL 0x76200048 R W Cb Cr gain control 0x00400040 CbCrGa...

Page 524: ...trol 0x00000010 DemoWinCTRL Bit Description Reset Value 31 25 Reserved 0 MVDemo 24 Enhancer demo window on off 0 Normal operation 1 Enhancer demonstration window mode 0 23 17 Reserved 0 FreshEn 16 Fresh tone correction on off 0 Fresh tone correction disable 1 Fresh tone correction enable 0 15 13 Reserved 0 BStOff 12 Black stretch off control 0 Black stretch enable 1 Black stretch disable 0 11 9 Re...

Page 525: ...08C FTCA Bit Description Reset Value 31 24 Reserved 0 FTCAC 23 16 Flesh tone correction angle Cosine value Equation FTCAC cos x 90 2 8 x 90 180 degree ex x 123 degree FTCAC cos 123 90 2 8 0xD7 0xD7 15 8 Reserved 0 FTCAS 7 0 Flesh tone correction angle Sine value Equation FTCAS sin x 90 2 8 x 90 180 degree ex x 123 degree FTCAS sin 123 90 2 8 0x8B 0x8C TVENCREG23 Register Address R W Description Re...

Page 526: ...Sharpness control 0x0304501F SharpCTRL Bit Description Reset Value 31 28 Reserved 0 SHARPT 27 20 Dynamic sharpness tilt point 0x30 19 15 Reserved 0 SDhCor 14 12 Sharpness coring control 0 Disable coring 7 Max coring 0x5 11 10 Reserved 0 DShpF0 9 8 Sharpness center frequency recommend DShpF0 0x2 above VGA 640x480 which is the output DShpF0 0 below QVGA 320x160 0 Low frequency 2 7MHz 3 4MHz 4 5MHz 2...

Page 527: ...31 13 Reserved 0 GamEn 12 Gamma enable 0 Gamma disable 1 Gamma enable 0 11 10 Reserved 0 GamMode 9 8 Gamma control mode 0 Min gamma gain 3 Max gamma gain 0x1 7 3 Reserved 0 DCTRAN 2 0 DC tran gain 0 80 5 100 7 110 0x4 TVENCREG27 Register Address R W Description Reset Value FscAuxCTRL 0x76200068 R W Fsc auxiliary control 0x00000000 FscAuxCTRL Bit Description Reset Value 31 5 Reserved 0 Phalt 4 Sub ...

Page 528: ...ion Reset Value 31 10 Reserved 0 SySize 9 0 Hsync size 0x3D NTSC 0x3E PAL 0x3D TVENCREG29 Register Address R W Description Reset Value BurstCTRL 0x76200070 R W Burst signal control 0x00690049 BurstCTRL Bit Description Reset Value 31 26 Reserved 0 BuEnd 25 16 Burst end position 0x69 NTSC 0x6A PAL 0x69 15 10 Reserved 0 BuSt 9 0 Burst start position 0x49 NTSC 0x4A PAL 0x49 TVENCREG30 Register Address...

Page 529: ...onEnd 25 16 Active video end position 0x348 NTSC 0x352 PAL 0x348 15 10 Reserved 0 AvonSt 9 0 Active video start position 0x78 NTSC 0x82 PAL 0x78 TVENCREG32 Register Address R W Description Reset Value EncCTRL 0x7620007C R W Encoder control 0x00000011 EncCTRL Bit Description Reset Value 31 1 Reserved 0 BGEn 0 Background enable 0 Disable 1 Enable 0x1 TVENCREG33 Register Address R W Description Reset...

Page 530: ...Reserved 0 N1 13 8 Macrovision control N1 0x17 N0 7 0 Macrovision control N0 0 TVENCREG35 Register Address R W Description Reset Value Macrovision1 0x76200088 R W Macrovision control 1 0x02050515 Macrovision1 Bit Description Reset Value 31 26 Reserved 0 N7 25 24 Macrovision control N7 0x2 23 19 Reserved 0 N6 18 16 Macrovision control N6 0x5 15 11 Reserved 0 N5 10 8 Macrovision control N5 0x5 7 6 R...

Page 531: ...acrovision control N11 0x07F8 TVENCREG38 Register Address R W Description Reset Value Macrovision4 0x76200094 R W Macrovision control 4 0x01600F0F Macrovision4 Bit Description Reset Value 31 25 Reserved 0 N16 24 Macrovision Control N16 0x1 N15 23 16 Macrovision Control N15 0x60 N14 15 8 Macrovision Control N14 0xF N13 7 0 Macrovision Control N13 0xF TVENCREG39 Register Address R W Description Rese...

Page 532: ...aracterization data and associated errata are not yet available Specifications and information herein are subject to change without notice TVENCREG40 Register Address R W Description Reset Value Macrovision6 0x7620009C R W Macrovision control 6 0x000003FF Macrovision6 Bit Description Reset Value 31 10 Reserved 0 N21 9 0 Macrovision control N21 0x3FF ...

Page 533: ...t Block Transfer BitBLT and Color Expansion Text Drawing Rendering a primitive takes two steps 1 configure the rendering parameters such as foreground color and the coordinate data by setting the drawing context registers 2 start the rendering process by setting the relevant command registers A H B B U S A H B S L A V E I F Register File Pattern Memory 8x8x16 bpp Cmd FIFO 32x40 bit Primitive Drawi...

Page 534: ...creen Color Expansion Memory to Screen Host to Screen Per pixel Operation Maximum 2048 2048 image size Window Clipping 90 180 270 X flip Y flip Rotation Totally 256 3 operand Raster Operation ROP Transparent Mode for BitBLT Alpha Blending Alpha Blending with a user specified 256 level alpha value Per pixel Alpha Blending 8x8x16 bpp pattern drawing Data Format 15 16 18 24 32 bpp color format suppor...

Page 535: ...IPELINE The figure below illustrates the rendering pipeline each stage of which is explained in the following sections PRIMITIVE DRAWING Primitive Drawing determines the pixels to fill and pass their coordinates to the next stage for further operations FIMG 2D supports three types of primitive drawing 1 line point drawing 2 bit block transfer 3 color expansion Line Point Drawing Line Drawing rende...

Page 536: ...s by Raster Operation changing the dimension of a rectangular image and so on FIMG 2D can render image in Transparent Mode In this mode the pixels having the same color with blue screen color BS_COLOR are not written to the destination image resulting in a transparent effect The Transparent Mode is illustrated in the following image in which the BS_COLOR is set to white and the destination image i...

Page 537: ...e values of X INCR and Y INCR CMDR_2 CMDR_3 The host provides the source image data through these two command registers When the host writes the first 32 bit data into CMDR_2 the rendering process starts in the host to screen mode Then the host should provide the rest of data by writing into CMDR_3 continuously Color Expansion Font Drawing Color Expansion expands the monochrome color to either bac...

Page 538: ...estination and third operand according to the 8 bit ROP value specified by the user The truth table of ROP is given in the following table Source Destination Third Operand ROP Value 1 1 1 Bit7 1 1 0 Bit6 1 0 1 Bit5 1 0 0 Bit4 0 1 1 Bit3 0 1 0 Bit2 0 0 1 Bit1 0 0 0 Bit0 The third operand can be pattern or foreground color configurable by the OS bit in the ROP_REG Pattern is a user specified 8x8x16 ...

Page 539: ...ENDING Alpha Blending combines the source color and the destination color in the frame buffer to get the new destination color FIMG 2D supports 256 level user specified alpha value and per pixel alpha blending as well Fading effect is also supported User specified alpha value ALPHA from 0 to 255 Alpha Blending data source ALPHA 1 destination 256 ALPHA 8 Fading data source ALPHA 1 8 fading offset P...

Page 540: ... line on which ox oy lies The effects of all rotation options are summarized in the following table and illustrated in Figure 3 Related Registers ROT_OC_REG Coordinate of the rotation reference point ROTATE_REG Rotation mode configuration Rotation Effect 0 90 180 270 X flip Y flip x dcx dcy ox oy dcx 2ox dcy ox oy dcx dcx 2ox y dcy dcx ox oy dcy 2oy dcx ox oy dcy 2oy dcy FIMG 2D FIMG 2D FIMG 2D Fi...

Page 541: ...able Specifications and information herein are subject to change without notice CLIPPING Clipping discards the pixels after rotation outside the clipping window The color data of the discarded pixels will not be written into the framebuffer Related Registers CW_LT_REG Coordinate of the leftmost topmost point of the clipping window CW_RB_REG Coordinate of the rightmost bottommost point of the clipp...

Page 542: ... 0x76100114 W Command register for Color Expansion Host to Screen Font Continue CMD7_REG 0x7610011C W Command register for Color Expansion Memory to Screen Common Resource Registers COLOR_MODE_REG 0x76100200 R W Color Mode register 0x0000_0008 HORI_REG_REG 0x76100204 R W Horizontal Resolution register 0x0000_0000 SC_WIN_REG 0x76100210 R W Screen Clip Window register 0x0000_0000 SC_WIN_X_REG 0x7610...

Page 543: ...x76100338 W Y coordinate of Coordinates 3 0x0000_0000 ROT_OC_REG 0x76100340 R W Rotation Origin Coordinates 0x0000_0000 ROT_OC_X_REG 0x76100344 W X coordinate of Rotation Origin Coordinates 0x0000_0000 ROT_OC_Y_REG 0x76100348 W Y coordinate of Rotation Origin Coordinates 0x0000_0000 ROTATE_REG 0x7610034C R W Rotation Mode register 0x0000_0001 ENDIA_READSIZE 0x76100350 RW Read size select 0x0000_00...

Page 544: ...verflows this bit will be set Reserved 7 1 0x0 E 0 FIFO level Interrupt Enable If E bit is set to 1 when FIFO_INT_LEVEL is same with FIFO_NO_USED Graphics Engine makes INTREQ signal high 0x0 GENERAL FIFO INTERRUPT CONTROL REGISTER FIFO_INTC_REG Register Offset R W Description Reset Value FIFO_INTC_REG 0x76100008 R W Interrupt Control register 0x0000_0018 FIFO_INTC_REG Bit Description Initial State...

Page 545: ...n Reset Value FIFO_STAT_REG 0x76100010 R Command FIFO Status register 0x0000_0600 FIFO_STAT_REG Bit Description Initial State Reserved 31 13 0x0 DE_FIN 10 Graphics Drawing Engine finished 1 G2D_IDLE 9 Graphics Engine IDLE state 1 OVR_INT 8 Overflow Interrupt 0 Reserved 7 6 0x0 FIFO_NO_USED 5 0 The number of FIFO entry used 0x0 GENERAL FRAME BUFFER BASE ADDRESS REGISTER FB_BA_REG Register Offset R ...

Page 546: ...ved 7 2 L 1 0 Nothing 1 Line Drawing P 0 0 Nothing 1 Point Drawing COMMAND BITBLT REGISTER CMD1_REG Register Offset R W Description Reset Value CMD1_REG 0x76100104 W Command register for BitBLT CMD1_REG Bit Description Initial State Reserved 31 2 S 1 0 Nothing 1 Stretch BitBLT N 0 0 Nothing 1 Normal BitBLT COMMAND HOST TO SCREEN START BITBLT REGISTER CMD2_REG Register Offset R W Description Reset ...

Page 547: ...TER CMD4_REG Register Offset R W Description Reset Value CMD4_REG 0x76100110 W Command register for Color Expansion Host to Screen Font Start CMD4_REG Bit Description Initial State Data 31 0 Packed format bitmap data COMMAND HOST TO SCREEN CONTINUE COLOR EXPANSION REGISTER CMD5_REG Register Offset R W Description Reset Value CMD5_REG 0x76100114 W Command register for Color Expansion Host to Screen...

Page 548: ...ORI_RES_REG Register Offset R W Description Reset Value HORI_REG_REG 0x76100204 R W Horizontal Resolution register 0x0000_0000 HORI_REG_REG Bit Description Initial State Reserved 31 12 0x0 HoriRes 11 0 Horisontal resolution should be 4 s multiple 0x0 COMMON RESOURCE SCREEN CLIPPING WINDOW SC_WIN_REG Register Offset R W Description Reset Value SC_WIN_REG 0x76100210 R W Screen Clip Window register 0...

Page 549: ...N_Y_REG Register Offset R W Description Reset Value SC_WIN_Y_REG 0x76100218 W Max Y of Screen Clip Window register 0x0000_0000 SC_WIN_Y_REG Bit Description Initial State Reserved 31 1 0x0 MaxSY 10 0 Max Screen Clipping Y Window 0x0 COMMON RESOURCE CLIPPING WINDOW LEFTTOP CW_LT_REG Register Offset R W Description Reset Value CW_LT_REG 0x76100220 R W LeftTop coordinates of Clip Window 0x0000_0000 CW...

Page 550: ...G Bit Description Initial State Reserved 31 27 0x0 BottomCW_Y 26 16 Bottom Y Clipping Window 0x0 Reserved 15 11 0x0 RightCW_X 10 0 Right X Clipping Window 0x0 COMMON RESOURCE RIGHT X CLIPPING WINDOW CW_RB_X_REG Register Offset R W Description Reset Value CW_RB_X_REG 0x76100234 W Right X coordinate of Clip Window 0x0000_0000 CW_RB_X_REG Bit Description Initial State Reserved 31 11 0x0 RightCW_X 10 ...

Page 551: ...Y 0x0 Reserved 15 11 0x0 X 10 0 Coordinate_0 X 0x0 COMMON RESOURCE COORDINATE_0 X REGISTER COORD0_X_REG Register Offset R W Description Reset Value COORD0_X_REG 0x76100304 W X coordinate of Coordinates 0 0x0000_0000 COORD0_X_REG Bit Description Initial State Reserved 31 11 0x0 COORD0_X 10 0 Coordinate_0 X 0x0 COMMON RESOURCE COORDINATE_0 Y REGISTER COORD0_Y_REG Register Offset R W Description Rese...

Page 552: ... Reserved 31 11 0x0 COORD1_X 10 0 Coordinate_1 X 0x0 COMMON RESOURCE COORDINATE_1 Y REGISTER COORD1_Y_REG Register Offset R W Description Reset Value COORD1_Y_REG 0x76100318 W Y coordinate of Coordinates 1 0x0000_0000 COORD1_Y_REG Bit Description Initial State Reserved 31 11 0x0 COORD1_Y 10 0 Coordinate_1 Y 0x0 COMMON RESOURCE COORDINATE_2 REGISTER COORD2_ REG Register Offset R W Description Reset...

Page 553: ...0_0000 COORD2_X_REG Bit Description Initial State Reserved 31 11 0x0 COORD2_X 10 0 Coordinate_2 X 0x0 COMMON RESOURCE COORDINATE_2 Y REGISTER COORD2_Y_REG Register Offset R W Description Reset Value COORD2_Y_REG 0x76100328 W Y coordinate of Coordinates 2 0x0000_0000 COORD2_Y_REG Bit Description Initial State Reserved 31 11 0x0 COORD2_Y 10 0 Coordinate_2 Y 0x0 COMMON RESOURCE COORDINATE_3 REGISTER ...

Page 554: ... COORD3_Y_REG Bit Description Initial State Reserved 31 11 0x0 COORD3_Y 10 0 Coordinate_3 Y 0x0 COMMON RESOURCE ROTATION ORIGIN COORDINATE ROT_OC_REG Register Offset R W Description Reset Value ROT_OC_REG 0x76100340 R W Rotation Origin Coordinates 0x0000_0000 ROT_OC_REG Bit Description Initial State Reserved 31 27 0x0 Y 26 16 Coordinate_3 Y 0x0 Reserved 15 11 0x0 X 10 0 Coordinate_3 X 0x0 COMMON R...

Page 555: ..._REG 0x76100348 W Y coordinate of Rotation Origin Coordinates 0x0000_0000 ROT_OC_Y_REG Bit Description Initial State Reserved 31 1 0x0 ROT_OC_Y 10 0 Rotation Origin Coordinate Y 0x0 COMMON RESOURCE ROTATION REGISTER ROTATE_REG Register Offset R W Description Reset Value ROTATE_REG 0x7610034C R W Rotation Mode register 0x0000_0001 ROTATE_REG Bit Description Initial State Reserved 31 6 0x0 FY 5 Y fl...

Page 556: ... READ_SIZE 1 0 2 b00 Read Burst Size 1 2 b01 Read Burst Size 4 2 b10 Read Burst Size 8 2 b11 Read Burst Size 16 0x0 COMMON RESOURCE X INCREMENT REGISTER X_INCR_REG Register Offset R W Description Reset Value X_INCR_REG 0x76100400 R W X Increment register 0x0000_0000 X_INCR_REG Bit Description Initial State Reserved 31 22 0x0 X_INCR 21 0 X increment value 0x0 COMMON RESOURCE Y INCREMENT REGISTER Y_...

Page 557: ...tate Reserved 31 14 0x0 OS 13 Third Operand Select 1 b0 Pattern 1 b1 Foreground Color 0x0 ABM 12 10 Alpha Blending Mode 3 b000 No Alpha Blending 3 b001 Perpixel Alpha Blending with Source Bitmap 3 b010 Alpha Blending with Register 3 b011 Perpixel Alpha Blending with Third Bitmap 3 b100 Fading Others Reserved 0x0 T 9 0 Opaque Mode 1 Transparent Mode 0x0 Reserved 8 0x0 ROP Value 7 0 Raster Operation...

Page 558: ...OR_REG 0x76100504 R W Background Color register 0x0000_0000 BG_COLOR_REG Bit Description Initial State Reserved 31 24 0x0 BackgroundColor 23 0 Background Color Value 0x0 COMMON RESOURCE BLUESCREEN COLOR REGISTER BS_COLOR_REG Register Offset R W Description Reset Value BS_COLOR_REG 0x76100508 R W Blue Screen Color register 0x0000_0000 BS_COLOR_REG Bit Description Initial State Reserved 31 24 0x0 Bl...

Page 559: ...scription Initial State Reserved 31 19 0x0 POffsetY 18 16 Pattern Offset Y Value 0x0 Reserved 15 3 0x0 POffsetX 2 0 Pattern OffsetX Value 0x0 COMMON RESOURCE PATTERN OFFSET X REGISTER PATOFF_X_REG Register Offset R W Description Reset Value PATOFF_X_REG 0x76100704 W Pattern Offset X register 0x0000_0000 PATOFF_X_REG Bit Description Initial State Reserved 31 3 0x0 POffsetX 2 0 Pattern OffsetX Value...

Page 560: ...lipping image data It is composed of Rotate FSM Rotate Buffer AMBA AHB 2 0 master slave interface and Register files Overall features are summarized as follows FEATURE Supports image format YCbCr 4 2 2 interleave YCbCr 4 2 0 non interleave RGB565 and RGB888 unpacked Supports rotate degree 90 180 270 flip vertical and flip horizontal BLOCK DIAGRAM Follow figure 19 1 shows the block diagram of Image...

Page 561: ...ct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice ORIGINAL IMAGE FLIP VERTICAL FLIP HORIZONTAL 180 DEGREE ROTATION ...

Page 562: ...3 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 90 AND 270 DEGREE ROTATION ...

Page 563: ...0x7720_0020 R W Rotator Destination Image CR component Address Register 0x0000_0000 STATCFG 0x7720_002C R Rotator Status Register 0x0000_0000 ROTATOR CONTROL REGISTER Register Address R W Description Reset Value CTRLCFG 0x7720_0000 R W Rotator Control Register 0x000_0000 CTRLREG Bit Description Initial State Reserved 31 25 Reserved 000b Enable Int 24 Interrupt Enable 0 Disable interrupt 1 Enable i...

Page 564: ...RCE IMAGE ADDRESS REGISTER 2 CR COMPONENT Register Address R W Description Reset Value SRCADDRREG2 0x7720_000C R W Rotator Source Image Address Register 0x0000_0000 SRCADDRREG2 Bit Description Initial State Source Address 30 0 The address of source image 0x0000_0000 ROTATOR SOURCE IMAGE SIZE REGISTER Register Address R W Description Reset Value SRCSIZEREG 0x7720_0010 R W Rotator Source Image Size ...

Page 565: ... R W Rotator Destination Image Address Register 0x0000_0000 DESTADDRREG 2 Bit Description Initial State Destination Address 30 0 The address of destination image 0x0000_0000 ROTATOR STATUS REGISTER Register Address R W Description Reset Value STATCFG 0x7720_002C R Rotator Status Register 0x0000_0000 STATREG Bit Description Initial State Current line number 31 16 Indicate where rotator accesses ima...

Page 566: ... dedicated to generate smaller size image for preview The other one is the codec scaler which is dedicated to generate codec useful image Two Channel MSDMA Memory Scaling DMA can read the memory data for each scaling path Two Output DMAs exist The one is the Preview DMA The other one is the Codec DMA Two DMA are dedicated to the YCbCr 4 2 2 YCbCr 4 2 0 and RGB output The CAMERA INTERFACE in S3C640...

Page 567: ...tor YCbCr RGB YCbCr RGB YCbCr RGB YCbCr RGB Color Space Conversion YCbCr RGB Color Space Conversion YCbCr RGB YCbCr RGB YCbCr RGB YCbCr RGB YCbCr RGB MSDMA Memory YCbCr 4 2 0 YCbCr 4 2 2 RGB YCbCr 4 2 0 YCbCr 4 2 2 RGB Camera interface Display Controller Display Controller Flip RGB16 18 24bit YCbCr 4 2 X YCbCr444 RGB24bit YCbCr444 RGB24bit Figure 20 1 Camera interface overview Preview Codec Presca...

Page 568: ... are as follows ITU R BT 601 YCbCr 8 bit mode ITU R BT 656 YCbCr 8 bit mode SIGNAL DESCRIPTION Name I O Description External camera processor interface signal XciPCLK I Pixel Clock driven by the Camera processor A XciVSYNC I Frame Sync driven by the Camera processor A XciHREF I Horizontal Sync driven by the Camera processor A XciYDATA 7 0 I Pixel Data driven by the Camera processor A XciRSTn O Sof...

Page 569: ...th 1 frame 8 bit mode Figure 20 2 ITU R BT 601 Input timing diagram PCLK DATA 7 0 Cr FF 00 00 XY Cb Y FF 00 00 XY Video timing reference codes Pixel data Video timing reference codes Figure 20 3 ITU R BT 656 Input timing diagram There are two timing reference signals in ITU R BT 656 format one at the beginning of each video data block start of active video SAV and one at the end of each video data...

Page 570: ... 0 in SAV Start of Active Video 1 in EAV End of Active Video P0 P1 P2 P3 protection bit Camera interface logic can catch the video sync bits like H SAV EAV and V Frame Sync after reserved data as FF 00 00 Caution All external camera interface IOs must not be combined with any other GPIO or bi directional ports Caution All external camera interface IOs are recommended to be shmitt trigger type IO f...

Page 571: ...tions and information herein are subject to change without notice Note If rotator is enabled t4 t1 must be long enough to finish DMA transactions It is because DMA transaction for rotator line buffer are delayed by 4 or 8 horizontal lines EXTERNAL INTERNAL CONNECTION GUIDE All Camera Interface input signals must not occur inter skewing to pixel clock line Recommend next pin location and routing Fi...

Page 572: ...CbCr 4 2 2 or RGB image data in the memory The P port and C port can be selected memory input data through MSDMA or camera input data through Camera These four master ports support the variable applications like DSC Digital Steel Camera MPEG 4 video conference video recording etc For example P port image can be used as preview image and C port image can be used as JPEG image in DSC application The...

Page 573: ...ter than pixel clock As highlighted in figure 20 7 CAMCLK must be divided from the fixed frequency like APLL or MPLL clock If external clock oscillator is used CAMCLK must be floated Internal scaler clock is system clock It is not mandatory for two clock domains to be synchronized with each other Other signals as PCLK must be similarly connected to shimitt triggered level shifter XciCLK Divide Cou...

Page 574: ...E must be higher than others If AHB bus is traffic enough that DMA operation is not ending during one horizontal period plus blank it might be entered into mal function Therefore the priority of CAMERA INTERFACE must be separated to other round robin or circular arbitration priorities It is also recommended that AHB bus which includes CAMERA INTERFACE must have higher priority than any other multi...

Page 575: ...STORING METHOD The little endian method is the storing method to the frame memory The first entering pixels stored into LSB sides and the last entering pixels stored into MSB sides The carried data by AHB bus is 32 bit word Therefore CAMERA INTERFACE make the each Y Cb Cr words by little endian style One pixel Color 1 pixel is one word for RGB 24 bit 18 bit format Otherwise two pixels are one word...

Page 576: ...ming Cb frame memory Cr frame memory Little endian method time Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y4 Y3 Y2 Y1 Y8 Y7 Y6 Y5 Cb4 Cb3 Cb2 Cb1 Cb8 Cb7 Cb6 Cb5 Little endian method Cr4 Cr3 Cr2 Cr1 Cr8 Cr7 Cr6 Cr5 Little endian method RGB frame memory 24 18 bit RGB1 RGB2 RGB3 RGB4 RGB5 RGB6 RGB7 RGB8 RGB frame memory 16 bit RGB2 1 RGB4 3 RGB6 5 RGB8 7 RGB10 9 RGB12 11 RGB14 13 RGB16 15 R8 G8 B8 2 32 bit 1 R 5 G...

Page 577: ...e period It is recommend to do first setting at the VSYNC L state VSYNC information can be read from status SFR Refer to the below figure 20 10 All command includes ImgCptEn and is valid at VSYNC falling edge Make sure that except first SFR setting all command must be programmed in ISR Interrupt Service Routine It is not allowed for target size information to be changed during capture operation Ho...

Page 578: ...ein are subject to change without notice SFR setting ENVID_M_P or ENVID_M_C Image Capture Frame Capture Start for MSDMA input Read Memory SFR setting ImgCptEn_PrSc or ImgCptEn_CoSC SEL_DMA_CAM SFR setting SEL_DMA_CAM New command valid timing diagram for MSDMA memory input SFR setting ENVID Image Capture Read Memory New command SFR setting New command P or C Port DMA end MSDMA end Read start In cap...

Page 579: ...s read in ISR means next frame count On following diagram last captured frame count is 1 That is Frame 1 is the last captured frame among frame 0 3 FrameCnt is increased by 1 at IRQ rising Camera input capture path ISR region ISR region ISR region VSYNC ISR region ImgCptEn cmd LastIRQEn Capture O Capture O Capture O Capture X IRQ Auto cleared Last IRQ High ISR region ISR region ISR region FrameCnt...

Page 580: ...d after P port or C port DMA operation is completed for per frame This mode is aware of starting point by user s SFR setting ENVID 0 1 Therefore this mode does not required IRQ of starting point and LastIRQ FrameCnt is increased by 1 at ENVID_M_P ENVID_M_C low to rising 0 1 and ImgCptEn_PrSC ImgCptEn_CoSC 1 SFR region SFR region SFR region ENVID_MS SFR region Preview DMA frame done Capture O Captu...

Page 581: ...DMA_CAM_P SEL_DMA_CAM_C signal must be set 1 This input path is called Memory Scaling DMA path This path is not allowed windowing zoom function Note Memory image format for MSDMA input are 1 YCbCr 4 2 0 non interleave 2 YCbCr 4 2 2 non interleave 3 YCbCr 4 2 2 Interleave 4 RGB External camera Memory MSDMA T_PatternMux CatchCam Color Space Converter S c a l e r Signal Muxing ITU R 601 656 MSDMA pat...

Page 582: ... Cr value offset control 1 128 0 0 normally used 0 X X reserved 29 0 X X SrcHsize_CAM 28 16 Camera source horizontal pixel number must be 8 s multiple minimum 8 It must be 4 s multiple of PreHorRatio if WinOfsEn is 0 0 X O Order422_CAM 15 14 Camera Input YCbCr order inform for 8 bit mode 8 bit mode 00 YCbYCr 01 YCrYCb 10 CbYCrY 11 CrYCbY 0 X X Reserved 13 0 X X SrcVsize_CAM 12 0 Camera source vert...

Page 583: ...WinHorOfst 26 16 Window horizontal offset by pixel unit It must be 2 s multiple 0 X O ClrOvCoFiCb 15 1 clear the overflow indication flag of input CODEC FIFO Cb 0 normal 0 X X ClrOvCoFiCr 14 1 clear the overflow indication flag of input CODEC FIFO Cr 0 normal 0 X X ClrOvPrFiCb 13 1 clear the overflow indication flag of input PREVIEW FIFO Cb 0 normal 0 X X ClrOvPrFiCr 12 1 clear the overflow indica...

Page 584: ...ust be set at only ITU T 601 8 bit mode Not allowed with input 16 bit mode or ITU T 656 mode max 1280 X 1024 00 external camera processor input normal 01 color bar test pattern 10 horizontal increment test pattern 11 vertical increment test pattern 0 X X InvPolPCLK 26 1 inverse the polarity of PCLK 0 normal 0 X X InvPolVSYNC 25 1 inverse the polarity of VSYNC 0 normal 0 X X InvPolHREF 24 1 inverse...

Page 585: ..._ c INTERRUPT LEVEL INTERRUPT EDGE TRIGGER SFR IRQ_CLR SET Interrupt SET Auto cleared Low to High cleared IRQ_CLR Auto cleared Figure 20 17 Interrupt generation scheme WINDOW OFFSET REGISTER 2 Register Address R W Description Reset Value CIWDOSFT2 0x78000014 RW Window offset register 2 0 CIWDOFST2 Bit Description Initial State M L Reserved 31 27 0 X X WinHorOfst2 26 16 Window horizontal offset2 by...

Page 586: ...DRESS REGISTER Register Address R W Description Reset Value CICOYSA2 0x7800001C RW 2nd frame start address for codec DMA 0 CICOYSA2 Bit Description Initial State M L CICOYSA2 31 0 Non Interleave Y Interleave YCbCr RGB 2nd frame start address 0 O X CODEC OUTPUT Y3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOYSA3 0x78000020 RW 3rd frame start address for codec DMA 0 CICOY...

Page 587: ...UT CB2 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA2 0x7800002C RW Cb 2nd frame start address for codec DMA 0 CICOCBSA2 Bit Description Initial State M L CICOCBSA2 31 0 Cb 2nd frame start address for codec DMA 0 O X CODEC OUTPUT CB3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA3 0x78000030 RW Cb 3rd frame start address for codec DMA 0 ...

Page 588: ...UT CR2 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCRSA2 0x7800003C RW Cr 2nd frame start address for codec DMA 0 CICOCRSA2 Bit Description Initial State M L CICOCRSA2 31 0 Cr 2nd frame start address for codec DMA 0 O X CODEC OUTPUT CR3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCRSA3 0x78000040 RW Cr 3rd frame start address for codec DMA 0 ...

Page 589: ...rleave 10 YCbCr 4 2 2 codec output image format Interleave 11 RGB codec output image format cf RGB format register OutRGB_FMT_Pr 0 O O TargetHsize_Co 28 16 Horizontal pixel number of target image for codec DMA 16 s multiple minimum 16 0 O O FlipMd_Co 15 14 Image mirror and rotation for codec DMA 00 Normal 01 X axis mirror 10 Y axis mirror 11 180 rotation XY axis mirror 0 O O reserved 13 TargetVsiz...

Page 590: ...c Y frames 0 O O Cburst1_Co 13 9 Main burst length for codec Cb Cr frames 0 O O Cburst2_Co 8 4 Remained burst length for codec Cb Cr frames 0 O O Reserved 3 0 X X LastIRQEn_Co 2 1 enable last IRQ at the end of frame capture It is recommended to check the done signal of capturing image for JPEG One pulse 0 normal 0 X X Order422_Co 1 0 Interleaved YCbCr 4 2 2 output order memory storing style LSB MS...

Page 591: ...length 2 Yburst1_Co and wanted Remained burst length 2 Yburst2_Co Cb Cr wanted Main burst length Yburst1_Co 2 Cburst1_Co and wanted Remained burst length Yburst2_Co 2 Cburst2_Co Example 1 Target image size QCIF horizontal Y width 176 pixels 1 pixel 1 Byte If output format non interleave YCbCr 4 2 2 0 1 word 4 pixels Yword 176 4 44 words 44 8 4 Y main burst 8 Y remained burst 4 Cword 176 4 2 22 wor...

Page 592: ...ETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_Width satisfy the word boundary constraints such that the number of horizontal pixel can be represented to kn where n 1 2 3 and k 1 2 8 for 24bppRGB 16bppRGB YCbCr420 image respectively TargetHsize must not be larger than Camera SourceHsize Similarly TargetVsize must not be larger than Camera SourceVsize DMA input source size can b...

Page 593: ...rtical Scale Range else if SRC_Height 32 DST_Height PreVerRatio_xx 32 V_Shift 5 else if SRC_Height 16 DST_Height PreVerRatio_xx 16 V_Shift 4 else if SRC_Height 8 DST_Height PreVerRatio_xx 8 V_Shift 3 else if SRC_Height 4 DST_Height PreVerRatio_xx 4 V_Shift 2 else if SRC_Height 2 DST_Height PreVerRatio_xx 2 V_Shift 1 else PreVerRatio_xx 1 V_Shift 0 PreDstHeight_xx SRC_Height PreVerRatio_xx MainVerR...

Page 594: ...n height for codec pre scaler 0 X O CODEC MAIN SCALER CONTROL REGISTER Register Address R W Description Reset Value CICOSCCTRL 0x78000058 RW Codec main scaler control 0x18000000 CICOSCCTRL Bit Description Initial State M L ScalerBypass_Co 31 Codec scaler bypass In this case ImgCptEn_CoSC must be 0 but ImgCptEn must be 1 Generally this mode uses large image size upper scaler maximum size Therefore ...

Page 595: ...selection register only when FIFO mode LCDPathEn 1 1 for Interlace scan and 0 for progressive scan In DMA mode LCDPathEn 0 progressive scan is applied whatever this value has This mode is not allowed when Input image data is from Camera processor 0 O O MainHorRatio_Co 24 16 Horizontal scale ratio for codec main scaler 0 O O CoScalerStart 15 Codec scaler start 1 scaler start 0 scaler stop 0 O O InR...

Page 596: ... to Display Controller Output data format is determined by only Output format register OutFormat_xx RGB format 24bit RGB or OutFormat_xx YCbCr format YCbCr444 The source image format and the destination image format restriction are described in the following table Input Image Format Progressive Output image Format Progressive Interlace 420 YCbCr Format 422 YCbYCr non interleave YCbCr 422 YCbYCr in...

Page 597: ...iminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 20 20 I O Timing Diagram for LCD Path ...

Page 598: ...TARGET AREA REGISTER Register Address R W Description Reset Value CICOTAREA 0x7800005C RW Codec dma target area 0 CICOTAREA Bit Description Initial State M L Reserved 31 26 0 X X CICOTAREA 25 0 Target area for codec DMA Target H size x Target V size 0 O O CODEC STATUS REGISTER Register Address R W Description Reset Value CICOSTATUS 0x78000064 R W Codec path status 0 Video Graphic 1 Frame Video Gra...

Page 599: ... 0 X X FlipMd_Co 24 23 Flip mode of codec DMA 0 X X ImgCptEn 22 Image capture enable of global camera interface 0 X X ImgCptEn_CoSC 21 Image capture enable of codec path 0 X X VSYNC_A 20 External camera A VSYNC polarity inversion was not adopted X X X reserved 19 X X X reserved 18 X X X FrameEnd_Co 17 When codec frame operation finish FrameEnd_Co is generated and FrameEnd_Co is clear by user setti...

Page 600: ... Y4 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRYSA4 0x78000078 RW 4th frame start address for preview DMA 0 CIPRCLRSA4 Bit Description Initial State M L CIPRYSA4 31 0 Non Interleave Y Interleave YCbCr RGB 4th frame start address 0 O X PREVIEW OUTPUT CB1 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRCBSA1 0x7800007C RW 1st frame start address f...

Page 601: ...T CB4 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRCBSA4 0x78000088 RW 4th frame start address for preview DMA 0 CIPRCBSA4 Bit Description Initial State M L CIPRCBSA4 31 0 Cb 4th frame start address for preview DMA 0 O X PREVIEW OUTPUT CR1 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRCRSA1 0x7800008C RW 1st frame start address for preview DMA 0...

Page 602: ...8000098 RW 4th frame start address for preview DMA 0 CIPRCRSA4 Bit Description Initial State M L CIPRCRSA4 31 0 Cr 4th frame start address for preview DMA 0 O X PREVIEW TARGET FORMAT REGISTER Register Address R W Description Reset Value CIPRTRGFMT 0x7800009C RW Target image format of preview DMA 0000_0000 CIPRTRGFMT Bit Description Initial State M L Reserved 31 0 X X OutFormat_Pr 30 29 00 YCbCr 4 ...

Page 603: ...e Line Buffer size for Rotation is 320 Words per line It means that max TargetHsize is 320 pixels when RGB888 666 Rot90_Pr 1 Original image 0 0 0 Rot90_ Pr FlipMd _Pr 1 FlipMd _Pr 0 MSB LSB X axis flip 0 0 1 Y axis flip 0 1 0 180 clockwise 0 1 1 90 clockwise 1 0 0 90 X axis flip 1 0 1 90 Y axis flip 1 1 0 90 XY axis flip 270 clockwise 1 1 1 Figure 20 22 Preview image mirror and rotation PREVIEW DM...

Page 604: ...review output format is YCbCr 4 2 2 interleave ScalerBypass_Pr 0 and ScaleUp_V_Pr 1 Wanted main burst length 16 and Wanted remained burst length 16 is not allowed Non Interleaved burst length Y burst length YCbCr 4 2 0 YCbCr 4 2 2 Rot90_Pr 0 YCbCr output Rot90_Pr 1 YCbCr output Y Main burst length 4 8 16 Remained burst length 4 8 16 Main burst length 2 Remained burst length 2 C Main burst length 2...

Page 605: ...1 wanted burst length must be 4 When Preview output is RGB565 and OutRot90_Pr 1 wanted burst length must be 4 When Preview output is Non Interleave YCbCr and OutRot90_Pr 1 wanted burst length must be 2 Y and 1 C If Preview output is RGB888 666 mode and OutRot90_Pr 1 and the original target horizontal width size before rotation TargetHsize is lager than 160 pixels wanted burst length must be 4 But ...

Page 606: ...ess than 8 PREVIEW PRE SCALER CONTROL REGISTER 2 Register Address R W Description Reset Value CIPRSCPREDST 0x780000A8 RW Preview pre scaler destination format 0 CIPRSCPREDST Bit Description Initial State M L Reserved 31 28 0 X X PreDstWidth_Pr 27 16 Destination width for preview pre scaler 0 O O Reserved 15 12 0 X X PreDstHeight_Pr 11 0 Destination height for preview pre scaler 0 O O PREVIEW MAIN ...

Page 607: ...d 0 for DMA mode FIFO mode output format is YCbCr4 4 4 or RGB24bit its selection depends on OutFormat register OutFormat_Pr RGB RGB24bit otherwise YCbCr4 4 4 0 O O Interlace_Pr 25 Output scan method selection register only when FIFO mode LCDPathEn 1 1 for Interlace scan and 0 for progressive scan In DMA mode LCDPathEn 0 progressive scan is applied whatever this value has Interlace mode is allowed ...

Page 608: ...or preview DMA Target H size x Target V size 0 O X PREVIEW STATUS REGISTER Register Address R W Description Reset Value CIPRSTATUS 0x780000B8 R W Preview path status 0 CIPRSTATUS Bit Description Initial State M L OvFiY_Pr 31 Overflow state of preview FIFO Y 0 X X OvFiCb_Pr 30 Overflow state of preview FIFO Cb 0 X X OvFiCr_Pr 29 Overflow state of preview FIFO Cr 0 X X Reserved 28 0 X X FrameCnt_Pr ...

Page 609: ...frame control only camera input is applied 1 Enable Step by Step frame one shot mode 0 Disable FreeRun mode 0 X O Cpt_FrEn_Pr 24 Capture preview frame control only camera input is applied 1 Enable Step by Step frame one shot mode 0 Disable Free Run mode 0 X O Cpt_FrPtr 23 19 Capture sequence turn around pointer Common preview codec 0 X X Cpt_ FrMod 18 Capture frame control mode Common preview code...

Page 610: ...0 Repeat Capture No Capture Capture Capture Figure 20 23 Capture frame control For skipped frmes IRQ_CI is not generated And FrameCnt is not increased IMAGE EFFECTS REGISTER Register Address R W Description Reset Value CIIMGEFF 0x780000D0 RW Image Effects related 0010_0080 CIIMGEFF Bit Description Initial State M L IE_ON_Pr 31 0 image effect function disable in preview path 1 enable 0 O O IE_ON_Co...

Page 611: ...r 8 d128 for GRAYSCALE Wide CSC Range 0 PAT_Cb 255 Narrow CSC Range 16 PAT_Cb 240 8 d128 O O Reserved 12 8 0 X X PAT_Cr 7 0 It is used only for FIN is Arbitrary Cb Cr Common preview codec path PAT_Cb Cr 8 d128 for GRAYSCALE Wide CSC Range 0 PAT_Cr 255 Narrow CSC Range 16 PAT_Cr 240 8 d128 O O Cf sepia PAT_Cb 8 d115 PAT_Cr 8 d145 Original Arbitrary sepia Negative Art freeze Embossing Silhouette MSD...

Page 612: ...BSA Bit Description Initial State M L Reserved 31 0 X X MSCOCB0SA 30 0 DMA start address for Cb component non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA FOR CODEC CR START ADDRESS REGISTER Register Address R W Description Reset Value MSCOCR0SA 0x780000DC RW MSDMA Cr0 start address related 0000_0000 MSCOCRSA Bit Description Initial State M L Reserved 31 0 X X MSCOCR0SA 30 0 DMA start address for Cr c...

Page 613: ...DMA CR END ADDRESS REGISTER Register Address R W Description Reset Value MSCOCR0EN D 0x780000E8 RW MSDMA Cr0 end address related 0000_0000 MSCOCREND Bit Description Initial State M L Reserved 31 0 X X MSCOCR0END 30 0 DMA End address for Cr component non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA FOR CODEC Y OFFSET REGISTER Register Address R W Description Reset Value MSCOYOFF 0x780000EC RW MSDMA Y o...

Page 614: ...image non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA FOR CODEC SOURCE IMAGE WIDTH REGISTER Register Address R W Description Reset Value MSCOWIDTH 0x780000F8 RW MSDMA source image width related 0000_0000 MSCOWIDTH Bit Description Initial State M L AutoLoadEnable 31 MSDMA Automatically restart Only Software trigger mode At the first frame start requires ENVID start setting After first frame next frame...

Page 615: ...boundary i e ADDRStart_X 1 0 00 ADDRStart_Cb and ADDRStart_Cr are valid only for the non interleave YCbCr420 422 source image format MSDMA End address ADDREnd_Y ADDRStart_Y Memory size for the component of Y RGB YCbCr interleave ADDRStart_Y SRC_Width SRC_Height ByteSize_Per_Pixel Offset_Y SRC_Height 1 ADDREnd_Cb Valid for YCbCr420 422 non interleave source format ADDRStart_Cb Memory size for the c...

Page 616: ... interleave RGB 16 bit 4 for RGB 18 24 bit Real_Height SRC_Height 2 YCbCr 420 case SRC_Height YCbCr 422 non interleave case MSDMA FOR CODEC CONTROL REGISTER Register Address R W Description Reset Value MSCOCTRL 0x780000FC RW MSDMA for codec control register 0000_0000 MSCOCTRL Bit Description Initial State M L Reserved 31 7 0 X X EOF_M_C 6 When MSDMA operation done End Of Frame will be generated re...

Page 617: ...care using external camera signal for codec path 2 SEL_DMA_CAM 1 ENVID is set 0 1 then MSDMA operation start for codec 0 O X Note ENVID_M_C SFR must be set at last Starting order for using MSDMA input path SEL_DMA_CAM_C others SFR setting Image Capture Enable SFR setting ENVID_M_C SFR setting ENVID_MS Next frame start Frame start 0 1 setting Auto Clear Frame end 0 1 setting Mode MSDMA input DMA ou...

Page 618: ...MSDMA Start End OFFSET MSDMA Source image width MSDMA control Preview DMA RGB start address Preview Target format Preview DMA Control etc Operation Done EOF signal generation Operation Done IRQ signal generation SFR SFR Figure 20 25 SFR Operation related each DMA when selected MSDMA input path ENVID_MS Frame start address change ADDR_CH_DIS Start End ADDRESS 0 user setting A 0 F A F Start End ADDR...

Page 619: ...for Interleave YCbCr 4 2 2 RGB component 0 O X MSDMA FOR PREVIEW CB0 START ADDRESS REGISTER Register Address R W Description Reset Value MSPRCB0SA 0x78000104 RW MSDMA Cb0 start address related 0000_0000 MSCBSA Bit Description Initial State M L Reserved 31 0 X X MSPRCB0SA 30 0 DMA start address for Cb component non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA FOR PREVIEW CR0 START ADDRESS REGISTER Regi...

Page 620: ...ter Address R W Description Reset Value MSPRCB0END 0x78000110 RW MSDMA Cb0 end address related 0000_0000 MSPRCBEND Bit Description Initial State M L Reserved 31 0 X X MSPRCB0END 30 0 DMA End address for Cb component non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA CR0 END ADDRESS REGISTER Register Address R W Description Reset Value MSPRCR0EN D 0x78000114 RW MSDMA Cr0 end address related 0000_0000 MSP...

Page 621: ...1 24 0 X X MSPRCBOFF 23 0 Offset of Cb component for fetching source image non interleave YCbCr 4 2 0 4 2 2 0 O X MSDMA FOR PREVIEW CR OFFSET REGISTER Register Address R W Description Reset Value MSPRCROFF 0x78000120 RW MSDMA Cr offset related 0000_0000 MSPRCROFF Bit Description Initial State M L Reserved 31 24 0 X X MSPRCROFF 23 0 Offset of Cr component for fetching source image non interleave YC...

Page 622: ...IDTH 11 0 MSDMA source image horizontal pixel size must be 8 s multiple Also must be 4 s multiple of PreHorRatio minimum 16 0 O X MSDMA FOR PREVIEW CONTROL REGISTER Register Address R W Description Reset Value MSPRCTRL 0x78000128 RW MSDMA control register for preview 0000_0000 MSPRCTRL Bit Description Initial State M L Reserved 31 7 0 X X EOF_M_P 6 When MSDMA operation done End Of Frame will be ge...

Page 623: ...MSDMA operation start for preview 0 O X CODEC SCAN LINE Y OFFSET REGISTER Register Address R W Description Reset Value CICOSCOSY 0x7800012C RW Codec scan line Y offset related 0 CICOSCOS Bit Description Initial State M L Reserved 31 29 0 X X Initial_Yoffset_Co 28 16 The number of the skipped pixels for initial Y offset scanline Y offset can be used when Non interleaved Y or Interleaved YCbCr422 or...

Page 624: ...offset_C o 28 16 The number of the skipped pixels for initial Cb offset scanline Cb offset can be used when Non interleaved YCbCr4 2 0 4 2 2 0 X O Reserved 15 13 0 X X Line_Cboffset_Co 12 0 The number of the skipped pixels in the screen of the target image when scan line is changed Scanline Cr offset can be used when Non interleaved YCbCr4 2 0 4 2 2 0 X O CODEC SCAN LINE CR OFFSET REGISTER Registe...

Page 625: ...fset can be used when Non interleaved Y or Interleaved YCbCr422 or RGB format 0 O O PREVIEW SCAN LINE CB OFFSET REGISTER Register Address R W Description Reset Value CIPRSCOSCB 0x7800013c RW Preview scan line Cb offset related 0 CICOSCOS Bit Description Initial State M L Reserved 31 29 0 X X Initial_Cboffset_Pr 28 16 The number of the skipped pixels for initial Cb offset scanline Cb offset can be ...

Page 626: ...l characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Reserved 15 13 0 X X Line_Croffset_Pr 12 0 The number of the skipped pixels in the screen of the target image when scan line is changed Scanline Cr offset can be used when Non interleaved YCbCr4 2 0 4 2 2 0 X O ...

Page 627: ... usages of Multi Format Video codec in S3C6400X RISC microprocessor Overview FIMV MFC V1 0 is a high performance video codec IP that supports H 263P3 MPEG 4 SP H 264 and VC 1 FIMV MFC V1 0 consists of the embedded BIT processor and video codec core module The BIT processor parses or forms bitstream and controls the video codec To speed up the bitstream processing some hardware accelerators are inc...

Page 628: ... module schedules the processing flow of the functional blocks of the video codec to reduce loads on the BIT processor and complexity of the firmware FIMV MFC V1 0 includes a rotation mirroring module In case of rotating and or mirroring the source image in the encoder no additional bandwidth is required for the processing However in the decoder the decoded image with any rotation and or mirroring...

Page 629: ...tream encoding and 3 streams decoding are possible Multi format is supported Ex The video IP encodes the MPEG 4 bitstream and decodes H 264 bitstream simultaneously Coding tools 16 16 1 2 and 1 4 pel accuracy motion estimation All variable block sizes are supported In case of encoding 8x4 4x8 and 4x4 block sizes are not supported Unrestricted motion vector MPEG 4 AC DC prediction H 264 AVC intra p...

Page 630: ...t notice FIMV MFC V1 0 embeds 16 bit DSP processor that is dedicated to processing bitstream and controlling the codec hardware General purpose registers and interrupt for communication between a host processor and the video IP Performance Up to full duplex VGA 30fps encoding decoding Up to half duplex 720x480 30fps 720x576 25fps encoding decoding Ease of integration AMBA 32 bit APB w PREADY inter...

Page 631: ...ntrols the video codec and communicates with a host processor through the host interface The BIT processor has program memory of 12KB and data memory of 4KB Figure 21 3 displays the block diagram of the BIT processor The special registers include command interrupt and code download registers The general purpose registers 64 32 bit registers can be used for the host processor to send parameters to ...

Page 632: ... module and interface with a host processor is divided into 2 parts One is for boot code that is downloaded by the host processor through the APB bus The size of the boot code is 1024 byte Another is for codes for codec processing such as MPEG 4 H 263 H 264 and VC 1 The procedure for downloading the firmware is executed only once at the initialization step Boot code Before running codec a host pro...

Page 633: ... memory and send information about the base address of the region by writing it to the CodeBufAddr register At run time part of firmware is automatically loaded to the internal BIT memory Boot Code Code Memory Base Address specified in the CodeBufAddr register Codec Firmware 1KB 79KB bit_code n 0 bit_code n 1 0 15 16 31 Boot code should be also loaded to the BIT internal memory at initialization F...

Page 634: ... simultaneously Each process can have difference format MPEG 4 H 263P3 H 264 or VC 1 and codec process encoding or decoding For example it is possible to handle 1 MPEG 4 encoding process 1 H 264 encoding process 1 H 263P3 decoding process and 1 VC 1 decoding process simultaneously You can encode image and or decode bitstream as following Create processes You can create and configure processes Runn...

Page 635: ...process is created with specific ID named as RunIndex range from 0 to 7 Basically the ID is assigned based on the order of creation After creating processes at initialization step a host processor commands the BIT processor to execute process specified with the RunIndex If processes are created sequentially as a MPEG 4 encoding b H 264 encoding c H 263P3 decoding for bitstream A d VC 1 decoding fo...

Page 636: ...t give you information about whether a requested process finished encoding or decoding 1 frame as specified format When the IP is under operation the BusyFlag is read as 1 If encoding or decoding 1 frame is finished and the IP is in the wait state that can accept a command from a host processor the BusyFlag becomes 0 At the time the BusyFlag becomes 1 the interrupt from the IP occurs A host proces...

Page 637: ... inter prediction module loads only chrominance data of the reference frame in encoding The luminance data are read from the local memory of the motion estimation module so that additional bus loading for the inter prediction is removed When the deblocking filter operates in the on the fly mode parts of reconstructed but not filtered pixel data are written to external memory for later use in the i...

Page 638: ...tional sampling needs fewer reference pixel data than the H 264 1 4 pel sampling PrP Rotator ME Inter predictor Transf Qaunt Qaunt 1 Transf 1 Buffer w reordering Residual Reconstruction Predicted MB buffer PP Rotator External SDRAM VLC by the BIT processor Reference MB Y only Current MB 1 Reference MB Cb Cr only Reconstructed coeff of adjacent MB 2 Reconstructed but not filtered bitstream 1 refere...

Page 639: ...00 No byte frame Byte frame 152064 460800 518400 Luminance data for 30 frames MB sec 3 041 9 216 10 368 Chrominance data for 30 frames MB sec 1 521 4 608 5 184 Frame data for 30 frames MB sec 4 562 13 824 15 552 Encoder bandwidth requirement for 30fps Item unit CIF VGA D1 Reading current frame data to be encoded for motion estimation and computing residual MB sec 4 562 13 824 15 552 Reading refere...

Page 640: ...low For the H 264 decoding process the decoding data path in the encoding loop is re used except following Bitstream is decoded by the BIT processor and decoded coefficients are stored in the coefficient buffer with hard wired reordering For the reference pixel data the inter prediction module reads both Y and Cb Cr data form external memory In case of encoding the data comes from the internal mem...

Page 641: ... No byte frame Byte frame 152064 460800 518400 Luminance data for 30 frames MB sec 3 041 9 216 10 368 Chrominance data for 30 frames MB sec 1 521 4 608 5 184 Frame data for 30 frames MB sec 4 562 13 824 15 552 Decoder bandwidth requirement for 30fps Item unit CIF VGA D1 Reading reference data for 16x16 block size MPEG 4 case It assumes all macroblocks have 16x16 block size MB se c 6 059 18 360 20 ...

Page 642: ... Pixel row read write for deblocking filtering MB se c 3 041 9 216 10 368 Coeff read write for AC DC prediction MPEG 4 case MB se c 3 041 9 216 10 368 Bitstream Loading MB se c 0 125 0 500 0 500 MPEG 4 16x16 Decode MB se c 13 787 41 900 47 075 MPEG 4 8x8 Decode MB se c 15 426 46 868 52 664 H 264 16x16 Decode MB se c 16 709 50 756 57 038 H 264 Typ Decode MB se c 23 624 71 708 80 609 H 264 4x4 Peak ...

Page 643: ...ec 3 041 9 216 10 368 Write back for display MB sec 4 562 13 824 15 552 Write back for reference MB sec 4 562 13 824 15 552 Bit Loading MB sec 0 125 0 500 0 500 VC 1 Decode worst case all reference 8x8 MB sec 28 661 86 972 97 781 Full duplex codec processing FIMV MFC V1 0 decoding data flow reuses the data path of the decoding in the encoding loop to reduce logic area For a full duplex codec appli...

Page 644: ... 21 9 Frame buffer configuration A frame buffer is specified with the base address and the stride line A complete image consists of Y U and V component Therefore an image requires 3 frame buffers for Y U and V components The stride line means the width of the luminance component buffer in pixel unit and must be multiple of 8 The stride line for the U and V frame buffers is a half of the Y frame bu...

Page 645: ...roduct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 21 10 Frame buffer address map in little endian ...

Page 646: ... FIMV MFC V1 0 uses output from the rotator module as input to the encoder without additional bandwidth consumption on the external SDRAM for rotation itself The rotated image is sent to the local buffer of the motion estimation module and re used in the intra prediction module for intra mode decision and residual computation module The PrP rotator module does not work in decoding process Figure 2...

Page 647: ... The Rotator modules support 8 types mode of 90 x n degree n 0 1 2 3 rotating and mirroring simultaneously The following table are the supporting rotating mirroring lists and these represents all possible combinations of rotating and mirroring There are two register sets One is for the PrP module and another for PP module Table 21 3 rotation mirroring modes MODE Rotated mirrored Image Descriptions...

Page 648: ...e Image Size 720x480 MIR_VERT Vertical mirroring Example Image Size 720x480 MIR_HOR_ROT_RIGHT_90 Horizontal mirroring and rotate right 90 Example Image Size 480x720 MIR_HOR_ROT_LEFT_90 Horizontal mirroring and rotate left 90 Example Image Size 480x720 Table 21 3 highlights rotation mirroring modes In above example input to all rotation mirroring modes is the same as the output image of the NONE_RO...

Page 649: ...and information herein are subject to change without notice Motion Estimation The Motion Estimation Block uses full search algorithm and the search range is 16 pixel or 8 pixel The following features are supported UMV Unrestricted Motion Vector mode Up to quarter pel search for H 264 BP Up to half pel search for MPEG4 SP Support 16x16 8x8 block for MPEG4 SP Support 16x16 16x8 8x16 8x8 block for H ...

Page 650: ... The ME block can impose high priority on zero motion vector by subtracting calculated SAD by user defined register value The prediction block size 16x16 16x8 8x16 8x8 decision can be prioritized in similar ways There are 3 offset registers for 8x8 block 8x16 block and 16x8 block You can impose high priority on large block size by adding calculated SAD by user defined registers The above figure hi...

Page 651: ...tion Core Block Diagram ME_CORE consist of command interface ME_CMD_IF integer pel search block FPS quarter half pel search block QPS and internal buffers SW_BUF RB_BUF SWH_BUF ME_CMD_IF block interfaces with BIT processor or CPU Current frame image is stored in RB_BUF and reference frame image is stored in SW_BUF and SWH_BUF Interger pel search block FPS uses RB_BUF for current frame and SW_BUF f...

Page 652: ...ta are not yet available Specifications and information herein are subject to change without notice ME DMA block SW SWH RB AXI Figure 21 15 Motion Estimation DMA Block Diagram ME_DMA services current and reference frame images to ME_CORE SW_DMA and SWH_DMA are reference search window data request channel SW_DMA and SWH_DMA read data from SDRAM RB_DMA reads current frame data through Pre rotator bl...

Page 653: ...ddress in spreg64x32 Interpolato r It interpolates reference picture data with 2 pel 4 pel resolution It uses temporal memory spreg64x32e16 for calculating H 264 quarter pels DMA Reads reference picture data from SDRAM decoding or ME local memory encoding and write it into local buffer memory dpreg60x96e8 dpreg36x96e8 Inter predictor supports all H 264 block mode 16x16 16x8 8x16 8x8 8x4 4x8 4x4 ha...

Page 654: ...6x96e8 Local Buffer Memory Main Controller spreg64x32 From SDRAM Decoding From ME local memory Encoding Control from BIT processor Interpolated data Figure 21 16 The Block Diagram of Inter prediction Figure 21 17 displays the local buffer memory configurations Y Y Y dpreg60x96e8 dpreg36x96e8 Cb Cr 12 pixel 36 depth 12 depth 12 depth Figure 21 17 The local buffer memory configuration The local buff...

Page 655: ...A 21x21 pixels for 16x16 quarter pel 13x13 pixels for 8x8 quarter pel 13x13 pixels for 8x8 quarter pel 13x13 pixels for 8x8 quarter pel 13x13 pixels for 8x8 quarter pel a 16x16 macroblock mode b 8x8 macroblock mode Figure 21 18 The example of the stored reference pixels in 16x16 mode and 8x8 mode The interpolator block of inter predictor calculates half or quarter pixel using reference pixel data ...

Page 656: ...tion N 1 Encoding N 1 Inter prediction N 2 Encoding N 2 Copy reference N th MB Y component from memory of ME to memory of intra predictor Inter prediction of N th MB Y component only Load reference N th MB U V components from external SDRAM to memory of intra predictor Inter prediction of N th MB U V components Issued by the ME at the end of searching MV of the N th MB Issued by the BIT processor ...

Page 657: ...of H 263P3 AIC Advanced Intra Coding mode the AC DC prediction is performed for the transformed coefficient not for quantized coefficient AC DC QUANT COEFF MEM QUANT 1 BIT PROCESSOR SCAN COEF_MEMWRAP Figure 21 21 a MPEG 4 AC DC prediction data flow Figure 21 21 b H 264 Intra prediction data flow Large parts of modules are shared in both encoding and decoding This module loads and stores the neighb...

Page 658: ...nd decoding is re ordered automatically based on the detected prediction mode For the H 264 intra prediction mode in encoding hardwired mode decision or software based mode decision is used In case of the hardwired mode decision a probable mode table is downloaded by the BIT processor This table is used for the intra prediction mode decision logic to search the best mode in some candidates The num...

Page 659: ...king buffer defined in the 3 2 In case of H 264 the required size of the memory and bandwidth on the external memory are different according to the coding option If the deblocking filter is operated in the stand alone manner the DMA controller only loads the neighboring pixels from the reconstructed frame buffer Therefore an additional memory is not needed for the intra prediction However in case ...

Page 660: ...cesses not only residual transform but also 4x4 luma dc transform In case of encoding the quantized coefficients are written to the coefficient buffer and the BIT processor reads them that are reordered in the coefficient buffer interface module In the same time the quantized coefficients are processed in the decoding loop of the encoding process For decoding processor the T Q module reads coeffic...

Page 661: ...otice TQ_CTRL controls encode and decode processing of the H 264 T Q block Figure 21 25 H 264 tranform quantization block diagram MPEG 4 H 263 The MPEG 4 H 263P3 transform quantization module supports only the method1 quantization mode for MPEG 4 bitstream It can process the AIC Advanced Intra Coding and the modified quantization mode for H 263P3 bitstream To process one macroblock in the MPEG 4 H...

Page 662: ...s not have any transform and quantization on its pixel data Therefore in case of I_PCM macroblock the T Q module by passes incoming data to the coefficient buffer memory and the inverse quantization module without any processing In case of inter macroblock and INTRA_16X16 macroblock the operation is very similar except transformation of the DC coefficient is performed for INTRA_16X16 For the H 264...

Page 663: ...Filtered frames are used as reference frames for motion compensation of subsequent coded frames But for MPEG4 the deblocking filter operates outside coding loop for only display The basic coding structure of H 264 is shown in Figure 21 28 Figure 21 28 H 264 deblocking filter data flow Processing modes FIMV MFC V1 0 supports 2 operating modes for each standard regarding to whether the filtering pro...

Page 664: ...de Another mode called as standalone mode performs filtering process after making reconstructed frame not macroblock In the stand alone mode the deblocking filter module reads an entire frame decoded already and writes it to specified frame buffer after filtering It needs more bandwidth of external memory bus compared to the on the fly mode In the on the fly mode the input to the filter is from a ...

Page 665: ...eg96x40 overlap deblock working buffer spreg272x44 Recon buffer deblock output output buffer spreg272x44 Figure 21 30 The main controller top_ctrl is controlled through ip bus by BIT processor The BIT processor writes control information processing mode filter mode H 263 H 264 MPEG 4 VC 1 run command etc into the control register in main controller Overlap smoothing filter is enabled in VC 1 mode ...

Page 666: ...s input for the filtering of the horizontal edges for the same macroblock The filter adjusts its strength depending upon compression mode of a macroblock Intra or Inter the quantization parameter motion vector and pixel values Parameters for filtering operation such as boundary strength indexA indexB are set by the BIT processor The Figure 21 31 highlights the valid data output in H 264 mode MB 0 ...

Page 667: ... edge need not be influenced by previous filtering across a vertical edge Parameters for filtering operation are set by the BIT processor The Figure 21 32 highlights the valid data output in H 263 Annex J mode MB 0 N 1 MB 0 P 1 MB N M 1 valid output valid output valid output valid output valid output MB 0 0 MB 0 N MB 0 P MB N 0 MB N 1 0 MB N M MB N 1 M MB N 1 M 1 MB N P 1 valid output MB N P MB N ...

Page 668: ... 128 will be added to each pixel of the block which will be clamped to the range 0 255 to produce the reconstructed output The BIT processor writes the neighboring block information for overlap smoothing filter The Figure 21 33 highlights the valid data output of VC 1 overlap smoothing filter MB 0 N 1 MB 0 P 1 MB N M 1 valid output valid output valid output valid output valid output MB 0 0 MB 0 N ...

Page 669: ...bblocks that have a horizontal boundary along the 4th 12th 20th etc horizontal lines will be filtered Next all blocks and subblocks that have a vertical boundary along the 8th 16th 24th etc vertical lines will be filtered Next all subblocks that have a vertical boundary along the 4th 12th 20th etc vertical lines will be filtered The Figure 21 34 highlights the valid data output of VC 1 deblocking ...

Page 670: ...a are not yet available Specifications and information herein are subject to change without notice MPEG 4 Deblocking filter for post processing FIMV MFC V1 0 can apply deblocking filtering for the MPEG 4 decoded image using either H 264 like filtering or H 263 like filtering operation The BIT processor generates parameters suitable for selected mode based on the result from the MPEG 4 decoding pro...

Page 671: ... to send variable length decoded coefficients to the video codec module for decoding process The coefficient buffer interface also performs reordering of coefficients based on the scan type Block diagram Figure 21 35 illustrates the block diagram of the coefficient buffer interface All sub modules related to processing coefficient as input or as output are connected to the coefficient buffer inter...

Page 672: ...processor reads or writes coefficient in the coefficient memory by specifying the block index scan type and the corresponding coefficient index Figure 21 36 illustrates how the BIT processor accesses the coefficient memory block index In case of the MPEG 4 H 263P3 each 8x8 block has its own index in range from 0 to 6 For the H 264 the range for the block index the size of block is 4x4 is from 1 to...

Page 673: ...ient buffer interface without any reordering When the BIT processor reads the coefficients they are reordered and the flags that indicate corresponding coefficient has a non zero value are sent to the BIT processor to check if there is coefficient to be encoded The BIT processor can know the number of the coefficients that have non zero value by simply counting number of bit that is not zero There...

Page 674: ... The BIT processor writes decoded coefficient without reordering inverse zig zag scanning The reordering process is performed when the inverse quantization module reads coefficients from the coefficient buffer interface The sub modules such as the quantizer and AC DC predictor handles zero if corresponding flag of coefficient is zero Figure 21 39 MPEG 4 decoding case Figure 21 39 H 264 decoding ca...

Page 675: ...roller to control all sub module of the video codec based on the configuration of pipelining by the BIT processor This scheme reduces the load on the BIT processor and guarantees the programmability of the IP Before the video codec encode or decode a macroblock the BIT processor configures how the pipeline of the codec is structured If all processes are completed for encoding decoding a macroblock...

Page 676: ...FIMV MFC V1 0 is communicated with a host processor through the APB bus interface Table 21 4 illustrates the address map of the region that could be accessed via the APB Table 21 4 Internal Register Address Map PADDR 11 9 Module Description 3 b000 Host interface of the BIT processor 3 b001 Macroblock controller sequencer 3 b010 Coefficient memory interface 3 b011 Deblocking filter 3 b100 Motion es...

Page 677: ...ese registers have reset values and the functions are fixed not configurable Address 0x100 0x1FC 64 registers are general purpose S W registers They have no reset values and are configurable by BIT firmware They are used as interface between host and BIT processor Upper 32 registers address 0x100 0x17C are used as static parameters The meanings or functions of those registers are not changed for a...

Page 678: ... 0 BitCurPc BIT Current PC Protected for Internal Use BASE 0x100 R W N A CodeBufAdddr CODE Table SDRAM Address BASE 0x104 R W N A WorkBufAddr Working Buffer SDRAM Address BASE 0x108 R W N A ParaBufAddr Argument Return Parameter Buffer SDRAM Address BASE 0x10C R W N A BitStreamCtrl Bit Stream Buffer Control BASE 0x110 R W N A FrameMemCtrl Frame Memory Control BASE 0x114 R W N A DecFuncCtrl Decoder ...

Page 679: ...dress of Run Index 4 BASE 0x148 R W N A BitStreamRdPtr5 Bit Stream Buffer Read Address of Run Index 5 BASE 0x14C R W N A BitStreamWrPtr5 Bit Stream Buffer Write Address of Run Index 5 BASE 0x150 R W N A BitStreamRdPtr6 Bit Stream Buffer Read Address of Run Index 6 BASE 0x154 R W N A BitStreamWrPtr6 Bit Stream Buffer Write Address of Run Index 6 BASE 0x158 R W N A BitStreamRdPtr7 Bit Stream Buffer ...

Page 680: ...er2 Address BASE 0x198 R W CMD_DEC_SEQ_TMP_BUF_3 Temporary Buffer3 Address BASE 0x19C R W CMD_DEC_SEQ_TMP_BUF_4 Temporary Buffer4 Address BASE 0x1A0 R W CMD_DEC_SEQ_TMP_BUF_5 Temporary Buffer5 Address6 INPUT ARGUMENT BASE 0x1A4 R W CMD_DEC_SEQ_START_BYTE Start byte of valid stream data BASE 0x1C0 R RET_DEC_SEQ_SUCCESS Command executing result status BASE 0x1C4 R RET_DEC_SEQ_SRC_SIZE Decoded source...

Page 681: ...ncode Source Frame Rate BASE 0x198 R W CMD_ENC_SEQ_MP4_PARA Encode MPEG4 Parameter BASE 0x19C R W CMD_ENC_SEQ_263_PARA Encode H 263 Parameter BASE 0x1A0 R W CMD_ENC_SEQ_264_PARA Encode H 264 Parameter BASE 0x1A4 R W CMD_ENC_SEQ_SLICE_MODE Encode Slice Mode BASE 0x1A8 R W CMD_ENC_SEQ_GOP_NUM Encode GOP Number BASE 0x1AC R W CMD_ENC_SEQ_RC_PARA Encode Rate Control Parameter BASE 0x1B0 R W CMD_ENC_SE...

Page 682: ...B Post rotated frame store CB address BASE 0x18C R W CMD_DEC_PIC_ROT_ADDR_CR Post rotated frame store CR address BASE 0x190 R W CMD_DEC_PIC_DBK_ADDR_Y Deblocked frame store Y address BASE 0x194 R W CMD_DEC_PIC_DBK_ADDR_CB Deblocked frame store CB address BASE 0x198 R W CMD_DEC_PIC_DBK_ADDR_CR Deblocked frame store CR address BASE 0x19C R W CMD_DEC_PIC_ROT_STRIDE Post rotated frame stride 11 BASE 0...

Page 683: ... frame buffer Y SDRAM address BASE 0x184 R W CMD_ENC_PIC_SRC_ADDR_CB Input source frame buffer CB SDRAM address BASE 0x188 R W CMD_ENC_PIC_SRC_ADDR_CR Input source frame buffer CR SDRAM address BASE 0x18C R W CMD_ENC_PIC_QS Encode picture quantization step BASE 0x190 R W CMD_ENC_PIC_ROT_MODE Input frame pre rotator mode INPUT ARGUMENT BASE 0x194 R W CMD_ENC_PIC_OPTION Encode picture option BASE 0x...

Page 684: ...e Description INPUT ARGUMENT BASE 0x180 R W CMD_ENC_HEADER_CODE Header code to be encoded OUTPUT RETURN Table 21 12 DEC PARA SET Parameter Register Summary DEC_PARA_SET Address Type Name Description BASE 0x180 R W CMD_DEC_PARA_SET_TYPE Sequence Picture Parameter Set type INPUT ARGUMENT BASE 0x184 R W CMD_DEC_PARA_SET_SIZE Sequence Picture Parameter Set RBSP byte size OUTPUT RETURN Table 21 13 ENC ...

Page 685: ...a and associated errata are not yet available Specifications and information herein are subject to change without notice Table 21 14 GET F W VER Parameter Register Summary GET_F W_VER Address Type Name Description INPUT ARGUMENT OUTPUT RETURN BASE 0x1C0 R RET_GET_FW_VER Returned Version Code with following format 31 16 Product No 0xF202 15 0 Ver No 0xMmrr for M m rr ...

Page 686: ...T code download data 0 28 16 CodeAddr W 13 bit BIT code download address BIT code word address 16 bit address Current design has 4 K code word space 8 KB Therefore CodeAddr 12 0 must be less than 4095 0 HostIntReq 0x008 Bit Name Type Function Reset Value 0 IntReq W Interrupt request to BIT processor Host can write 1 to this register to request interrupt to BIT Current firmware version does not use...

Page 687: ...y debugging purpose 0 CodeBufAddr 0x100 Bit Name Type Function Reset Value 31 0 CodeBufAddr R W BIT firmware code image start byte address which resides in SDRAM Host must set start SDRAM byte address of BIT code image to this register before start executing BIT processor Current design uses 80 KB for code buffer N A WorkBufAddr 0x104 Bit Name Type Function Reset Value 31 0 WorkBufAddr R W BIT pro...

Page 688: ...hat bit stream buffer is flushed at every end of encoding picture In encoding case after encoding one picture internal bit stream buffer is flushed to external SDRAM Therefore entire encoded bit stream data is available to host If this flag is 0 internal bit stream buffer is flushed only when internal bit stream buffer is filled to its maximal size 512 byte Therefore at the end of encoding one pic...

Page 689: ...e decoder In Picture Run state BIT processor can know the end of bitstream by checking this bit Host must set this flag after writing the whole bitstream to get the last picture of bitstream Host also can clear busy state while BIT is waiting for the rest of bitstream corresponding to one picture and get one picture by setting this flag Host can set clear this flag at any stage in decoding process...

Page 690: ...al Bit Stream Buffer read address of process index 0 to this register This register is updated at every bit stream data load by BIT processor and wrapped around by automatically Current design load 512 bytes to internal buffer for each transfer Therefore Bit Stream Read Pointer is increased to 512 after loading data completion N A BitStreamWrPtr0 0x124 Bit Name Type Function Reset Value 31 0 Strea...

Page 691: ...lue 31 0 StreamWrPtr1 R W External SDRAM Bit Stream Buffer write address of process index 1 N A BitStreamRdPtr2 0x130 Bit Name Type Function Reset Value 31 0 StreamRdPtr2 R W External SDRAM Bit Stream Buffer read address of process index 2 N A BitStreamWrPtr2 0x134 Bit Name Type Function Reset Value 31 0 StreamWrPtr2 R W External SDRAM Bit Stream Buffer write address of process index 2 N A BitStre...

Page 692: ...eset Value 31 0 StreamWrPtr4 R W External SDRAM Bit Stream Buffer write address of process index 4 N A BitStreamRdPtr5 0x148 Bit Name Type Function Reset Value 31 0 StreamRdPtr5 R W External SDRAM Bit Stream Buffer read address of process index 5 N A BitStreamWrPtr5 0x14C Bit Name Type Function Reset Value 31 0 StreamWrPtr5 R W External SDRAM Bit Stream Buffer write address of process index 5 N A ...

Page 693: ...essor is ready for host command The value of 1 means BIT processor is executing host command and not completed yet Host must check this bit before write RunCommand register If this bit is 1 host must wait until the value of 0 to set command N A RunCommand 0x164 Bit Name Type Function Reset Value 2 0 RunCommand R W Host writes the command code to this register Command code 3 b001 SEQ_INIT Encode De...

Page 694: ...ry by this command 3 b110 ENC PARA SET Encode SPS PPS to BIT processor s parameter set buffer In H 264 host can obtain SPS PPS by this command 3 b111 DEC PARA SET Add SPS PPS to BIT processor s parameter set buffer In H 264 multiple SPS PPS is allowed and host may inform one of the parameter set to BIT processor for use in decoding process 4 b1111 GET F W VER A command to check F W version This co...

Page 695: ...le 0x170 Bit Name Type Function Reset Value 15 0 IntEnable R W Interrupt Enable Flag register Each bit of this register is interrupt enable flag of various interrupt 1 means interrupt enable so BIT generates interrupt and 0 means interrupt disable 0th bit LSB Initialize complete This interrupt is generated at once after BIT run 1st bit SEQ_INIT command execution complete 2nd bit SEQ_END command ex...

Page 696: ...ice routine Host is responsible for resetting this register to 0 for next interrupt The interrupt matching of each bit field is same with IntEnable register N A CMD_DEC_SEQ_BIT_BUF_START 0x180 Bit Name Type Function Command 31 0 BitBufAddr R W Bitstream buffer SDRAM byte address Bitstream buffer must be 512 byte aligned Host must writes this register before executing DEC_SEQ_INIT command DEC_SEQ_I...

Page 697: ...tions ex Video telephony don t want such display delay Host may set this flag to 0 to disable output display buffer reordering Then BIT processor does not re order output buffer when pic_order_cnt_type is 0 or 1 In pic_order_cnt_type is 2 or MPEG4 H 263 case this flag is ignored because output display buffer reordering is not allowed If this flag is 1 BIT processor perform output decoded picture r...

Page 698: ...C1 and not used for mpeg4 Process buffer must be larger than MB number 4 for VC1 In case of AVC process buffer size is not estimated Therefore host process allocates some amount temporarily Process buffer must be maintained before instance closed Therefore host processor must allocate process buffer as instance number DEC_SEQ_I NIT CMD_DEC_SEQ_TMP_BUF_1 0x190 Bit Name Type Function Command 31 0 Te...

Page 699: ...cHeight 2 16 for AVC picWidth 10 for VC1 In case of mpeg4 temporary buffer 2 size is not estimated DEC_SEQ_I NIT CMD_DEC_SEQ_TMP_BUF_3 0x198 Bit Name Type Function Command 31 0 TempBufAddr R W Temporary buffer SDRAM byte address Temporary buffer must be 256 byte aligned Host must write this register before executing DEC_SEQ_INIT command Temporary buffer 3 is used as data partition part 2 save buff...

Page 700: ...ligned Host must write this register before executing DEC_SEQ_INIT command Temporary buffer 5 is used as slice save buffer for AVC and not used for VC1 and mpeg4 Max size of temporary buffer 5 may be picwidth picheight 1 5 DEC_SEQ_I NIT CMD_DEC_SEQ_START_BYTE 0x1A4 Bit Name Type Function Command 1 0 DecSeqVali dByteStart R W Byte Address of valid bitstream in input stream buffer DEC_SEQ_I NIT RET_...

Page 701: ...C Bit Name Type Function Command 4 0 FrameBufNeed R Minimum decoded frame buffer need to decode stream successfully In MPEG4 H 263 case this value will be 2 one for motion compensation reference one for current frame store In H 264 case this value may be bigger than 2 and maximal value may be 18 16 for reference 1 for current 1 for display Host must reserve frame buffer with the amount of minimum ...

Page 702: ...ding at the first DEC_PIC_RUN command because during first 5 frames there is no decoded picture to be displayed Maximum FrameBufDelay value may be 16 This value is 0 if ReorderEn flag is 0 at H 264 case In VC 1 decode case this value is 0 if there is no B picture 1 if there is a B picture regardless ReorderEn flag In MPEG4 H 263 case this value will be 0 no delay DEC_SEQ_I NIT RET_DEC_SEQ_INFO 0x1...

Page 703: ...re executing ENC_SEQ_INIT command Maximal bitstream buffer size is 4G byte ENC_SEQ_I NIT CMD_ENC_SEQ_OPTION 0x188 Bit Name Type Function Command 0 MbBitReport R W Bit position of every MB is stored to SDRAM buffer If this flag is 1 BIT processor store the start bit position of every MB to SDRAM Host may access this bit position value after encoding one picture The MB BIT buffer resides in ParaBufA...

Page 704: ...sociated errata are not yet available Specifications and information herein are subject to change without notice 2 AUDEnable R W Encode H 264 Access Unit Delimiter RBSP enable If this flag is 1 BIT encodes Access Unit Delimiter RBSP at every start of picture Access Unit Delimiter RBSP is used to simplify the detection of the picture boundary This flag is ignored at MPEG4 H 263 encode case ...

Page 705: ...height size in pixel Source picture height must be a multiple of 16 less than or equal to 576 19 10 PictureWidth R Encode source picture width size in pixel Source picture width must be a multiple of 16 less than or equal to 720 ENC_SEQ_I NIT CMD_ENC_SEQ_SRC_F_RATE 0x194 Bit Name Type Function Command 15 0 FrameRateRes R Encode source frame rate residual Number of time units of a clock operating a...

Page 706: ...ble used This bit is ignored if DataPartEn bit is 0 4 2 IntraDcVlcThr R W MPEG4 Intra DC VLC Threshold code The allowed range is 0 7 ENC_SEQ_ INIT CMD_ENC_SEQ_263_PARA 0x19C Bit Name Type Function Command 0 Annex T R W 0 Annex T off 1 Annex T on 1 Annex K R W 0 Annex K off 1 Annex K on 2 Annex J R W 0 Annex J off 1 Annex J on 3 Annex I R W 0 Annex I off 1 Annex I on Current design does not support...

Page 707: ...nable deblocking filter except slice boundary 11 8 DeblkAlphaOffset R W slice_alpha_c0_offset_div2 in slice header range 6 to 6 2 s complement signed 4 bit 15 12 DeblkBetaOffset R W slice_beta_offset_div2 in slice header range 6 to 6 2 s complement signed 4 bit CMD_ENC_SEQ_SLICE_MODE 0x1A4 Bit Name Type Function Command 0 SliceMode R W 0 one slice per picture 1 multiple slices per picture MPEG4 mo...

Page 708: ... 0 In H 263 Mode with Annex K 0 this bit is ignored CMD_ENC_SEQ_GOP_NUM 0x1A8 Bit Name Type Function Command 5 0 EncGopNum R W Encode GOP number I picture is inserted at every GOP picture number Maximum GOP number is 60 0 I P P P only first picture is I 1 I I I no P picture 2 I P I P 3 I P P I P P I ENC_SEQ_ INIT CMD_ENC_SEQ_RC_PARA 0x1AC Bit Name Type Function Command 0 RcEnable R W Rate Control ...

Page 709: ...lag is 1 BIT processor never skip the picture but encoded bitstream may be overflow than target bit rate at hard to encode sequences This flag is ignored if RcEnable is 0 CMD_ENC_SEQ_RC_BUF_SIZE 0x1B0 Bit Name Type Function Command 31 0 VbvBufSize R W Reference Decoder buffer size in bits This value is ignored if RcEnable 0 or InitDelay 0 Maximum allowed value is 0x7FFF_FFFF 0 do not check Referen...

Page 710: ...mmand 31 0 TempBufAddr R W Temporary buffer SDRAM byte address Temporary buffer must be 256 byte aligned Host must write this register before executing ENC_SEQ_INIT command Temporary buffer 1 is used as ACDC prediction Buffer for Mpeg4 and Intra Prediction Y buffer for AVC Temporary buffer 1 must be larger than picwidth 8 for mpeg4 stride picheight 16 for AVC ENC_SEQ_I NIT CMD_ENC_SEQ_TMP_BUF_2 0x...

Page 711: ...2 8 for AVC In case of mpeg4 temporary buffer 2 size is not estimated CMD_ENC_SEQ_TMP_BUF_3 0x1D8 Bit Name Type Function Command 31 0 TempBufAddr R W Temporary buffer SDRAM byte address Temporary buffer must be 256 byte aligned Host must write this register before executing ENC_SEQ_INIT command Temporary buffer 3 is used as data partition part 3 save Buffer for Mpeg4 and Intra Prediction Cr buffer...

Page 712: ... H 264 encoder The size of this buffer must be given by 32 KB FmoSliceNr For example if the number of slice group is 8 this buffer size should be 32x8 KB ENC_SEQ_I NIT RET_ENC_SEQ_SUCCESS 0x1C0 Bit Name Type Function Command 0 RetStatus R 0 ENC_SEQ_INIT command executed with error 1 ENC_SEQ_INIT command executed successfully ENC_SEQ_I NIT CMD_DEC_PIC_ROT_MODE 0x180 Bit Name Type Function Comman d ...

Page 713: ...image is stored to DecPicRotAddrY DecPicRotAddrCb DecPicRotAddrCr address addition to decoded image store for future reference If this field is 0 the post rotation is disabled and PostRotMode field is ignored CMD_DEC_PIC_ROT_ADDR_Y 0x184 Bit Name Type Function Comman d 31 0 DecRotAddrY R W Rotated display frame address of luminance If PostRotEn field is 1 the rotated image is stored to this addres...

Page 714: ...DEC_PIC_ RUN CMD_DEC_PIC_ROT_ADDR_CR 0x18C Bit Name Type Function Comman d 31 0 DecRotAddrCr R W Rotated display frame address of Cr In VC 1 mode this register is not used The rotated output will be one of the frames which previously allocated by RET_DEC_SEQ_FRAME_NEED 0x1CC DEC_PIC_ RUN CMD_DEC_PIC_DBK_ADDR_Y 0x190 Bit Name Type Function Comman d 31 0 DecDbkAddrY R W Deblocked display frame addre...

Page 715: ... only valid in file play mode and it will be used as size of stream data when BIT processor update write pointer of picture stream buffer DEC_PIC_ RUN CMD_DEC_PIC_BB_START 0x1AC Bit Name Type Function Comman d 31 0 DecPicBitBufStart R W 4 byte aligned byte address of the decoder input picture stream buffer This value will only be valid if decoder dynamic buffer allocation option is enabled as well...

Page 716: ...r address that host informs by SET_FRAME_BUF command If BIT return 1 0xFFFF it means that all pictures of given bitstream have already been decoded For example if host has given a bitstream containing 20 pictures host will get 1 value from 21th PICTURE_RUN In file play mode BIT return 3 0xFFFD when BIT does not have a picture to be displayed For example BIT does not have a picture to be displayed ...

Page 717: ... DEC_PIC_ RUN RET_DEC_PIC_SUCCESS 0x1D8 Bit Name Type Function Comman d 0 RetStatus R 0 DEC_PIC_RUN command executed with error 1 DEC_PIC_RUN command executed successfully 1 Invalid PPS R Invalid PPS This bit is set when there is no valid PPS in given stream This bit is set only in file play mode and valid when RetStatus bit is 0 DEC_PIC_ RUN CMD_ENC_PIC_SRC_ADDR_Y 0x180 Bit Name Type Function Com...

Page 718: ...oding source frame address of Cr ENC_PIC_ RUN CMD_ENC_PIC_QS 0x18C Bit Name Type Function Comman d 31 0 PictureQs R W Picture quantized step parameter for encoding process In MPEG4 H 263 mode allowed range is 1 to 31 In H 264 mode allowed range is 0 to 51 If rate control is enabled this register is ignored If rate control is disabled BIT encodes whole MBs in current picture with this value Host ma...

Page 719: ...0 PicSkipEn R W Picture skip flag If this field is 1 EncSrcAddrY EncSrcAddrCb EncSrcAddrCr are ignored and one skipped picture is encoded In that case the reconstructed image at decoder side is a copy of previous picture The skipped picture is encoded as P type Inter picture regardless of EncGopNum Host may set this field as 1 when next source frame to be encoded is not available For example of en...

Page 720: ... set IdrPic flag set 18th frame and EncGopNum is 15 encoded picture types are 1st frame I IDR automatically 2nd frame P 14th frame P 15th frame I 16th frame P 17th frame P 18th frame I IDR set by host 19th frame P 32nd frame I 33rd frame P In MPEG 4 H 263 case I Intra picture is sufficient for decoder refresh Host must set this filed as 1 periodically for inserting decoder refresh point in encoded...

Page 721: ...W Reconstructed frame index After BIT encodes one frame BIT return reconstructed frame index to this register Reconstructed frame is used for reference of future frame ENC_PIC_ RUN RET_ENC_PIC_SLICE_NUM 0x1CC Bit Name Type Function Comman d 14 0 EncSliceNum R W If SliceInfoReport flag in CMD_ENC_SEQ_OPTION register BIT returns encoded slice number to this register The encoded slice end position of...

Page 722: ... R W Line stride offset of picture frame memory Stride number is byte count SET_FRAM E_BUF CMD_ENC_HEADER_CODE 0x180 Bit Name Type Function Comman d 2 0 HeaderCode R W Encode header code In MPEG4 3 b000 VOL header 3 b001 VOS header 3 b010 VIS header In H 264 3 b000 SPS rbsp 3 b001 PPS rbsp In H 263 ENC_HEADER command is ignored ENC_HEA DER CMD_DEC_PARA_SET_TYPE 0x180 Bit Name Type Function Command...

Page 723: ...yet available Specifications and information herein are subject to change without notice CMD_ENC_PARA_SET_TYPE 0x180 Bit Name Type Function Command 0 EncParaSetType R W Parameter set type 0 Sequence Parameter Set 1 Picture Parameter Set ENC_PARA _SET RET_ENC_PARA_SET_SIZE 0x1C0 Bit Name Type Function Command 8 0 EncParaSetSize R W Encoded Sequence Picture parameter set RBSP byte size ENC_PARA _SET...

Page 724: ...urable and Address 0x100 0x1FC 64 registers are general purpose S W registers They have no reset values and are configurable by BIT firmware They are mainly used for interface between host and BIT processor Upper 32 registers address 0x100 0x17C are used as static parameters The meanings or functions of those registers are not changed for all kinds of run commands SEQ_INIT SEQ_END PICTURE_RUN and ...

Page 725: ...DRAM context switching For the initial BIT processor executing initial start after hardware reset initial booting code image must be downloaded directly by host Before executing the BIT processor by set CodeRun register host must directly downloads booting code image some amount of uppermost part of code image to the lowest code memory address 0 by set CodeDownLoad register The total byte size of ...

Page 726: ...eration never stops because of bit stream buffer status In this case the host processor does not need the writing current read write pointer to BitStreamRdPtr BitStreamWrPtr but host guarantee that bit stream overflow underflow will never occur If BufPicReset flag is in BitStreamCtrl register is 1 the external bit stream buffer does not operate as a ring buffer for encoding case only The encoded b...

Page 727: ...formation such as picture size Then the information is reported to DEC_SEQ_INIT return registers ENC_SEQ_INIT This command initiates an encoding process At ENC_SEQ_INIT command BIT processor reads encoding parameter from command argument registers and encodes sequence header The encoding parameters which exist in ENC_SEQ_INIT command argument register are applied to followed ENC_PIC_RUN commands a...

Page 728: ..._DEC_SEQ_FRAME_NEED register In encoding case two frame buffers are sufficient The number of total frame buffer is set to CMD_SET_FRAME_BUF_NUM register by host The decoding decode case reconstructing encode case image must be reserved for motion compensation reference until not used for reference Therefore the decoded reconstructed frame buffer is re used carefully BIT processor receives the whol...

Page 729: ...cture parameter set is activated at decoding slice header with the matched sequence picture parameter set id Multiple sequence picture parameter sets may be delivered to decoder They are distinguished by different sequence picture parameter set id The sequence parameter set id is encoded as 5 bits 0 31 in sequence parameter set RBSP The picture parameter set id is encoded as 8 bits 0 255 BIT proce...

Page 730: ...BufAddr MbY 128 MbX 2 The maximum encoding source picture height is 576 so the maximum size of the macro block bit number buffer is 128 576 16 4608 byte 4 5 KB The detailed format is illustrated in the following diagram Encoded Slice Information This is the output return data for ENC_PIC_RUN command If SliceInfoReport flag in CMD_ENC_SEQ_OPTION register is 1 BIT processor stores the end SDRAM addr...

Page 731: ...e the reconstructed pixel row buffer for MPEG4 AC DC prediction or H 264 intra prediction context saving buffer for running multiple processes bit stream re ordering buffer for MPEG4 data partition or H 264 FMO ASO and so on The required working buffer size is varied according to decode encode size and capability For example AC DC prediction buffer size is determined by picture width and maximum b...

Page 732: ...IC MP4_DEC MP4_DEC_DP2 Bit stream reordering buffer for data partition 48 MP4_ENC_ACDC AC DC prediction buffer of Y Cb Cr picWidth 8 MP4_ENC_DP1 Bit stream reordering buffer for data partition 48 TEMP_PIC MP4_ENC MP4_ENC_DP2 Bit stream reordering buffer for data partition 48 AVC_DEC_IP Intra prediction buffer of Y Cb Cr 72 AVC_DEC_FMO FMO group status buffer 5 5 AVC_DEC_SLICE_INFO Slice informatio...

Page 733: ...switching and static data storage of each instance Size of fixed static buffer is 78 KB Configurable static buffer is process buffer defined in register description section and is used when decode AVC and VC 1 Configurable static buffer must be allocated each instance and not be used as other usage before each instance Configurable temporal buffer is temporary buffer defined in register descriptio...

Page 734: ...uffer for data partition 48 AVC_DEC_IP_Y Intra prediction buffer of Y FrameBufferStride pic Hieght 16 1024 AVC_DEC_IP_Cb Intra prediction buffer of Cb FrameBufferStride 2 picHieght 2 8 1024 AVC_DEC_IP_Cr Intra prediction buffer of Cr FrameBufferStride 2 picHieght 2 8 1024 AVC_DEC_SLICE_INFO Slice information buffer Maximum 1620 slices per picture 12 66 TEMP_PI C AVC_DEC AVC_DEC_SLICE Slice data RB...

Page 735: ...ndard is different between previous and current process Therefore worst case context switching overhead SDRAM bandwidth is about 8KB R 8KB W 8KB R 30 Hz 8 process 5760 KB sec at 30 frame sec BIT processor requires about 0 75 cycles byte for reading or writing SDRAM data at burst mode Therefore worst case context switching overhead cycles are about 8K 8K 8K 0 75 30 Hz 8 process 4 4 M Cycles Descrip...

Page 736: ...applied to horizontal vertical flipped image In case of the post rotator the rotation field is applied prior to horizontal vertical mirroring then mirroring is applied to counterclockwise rotated image If counterclockwise rotation field is 1 90 degree or 3 270 degree the rotated image picture width height will be exchanged For example CIF size image 352 x 288 will be 288 x 352 after rotation and t...

Page 737: ...reliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Example of Single MPEG4 Decoder ...

Page 738: ...21 112 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Example of Single H 264 Encoder ...

Page 739: ... Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Example of H 264 Full Duplex ...

Page 740: ...antization Huffman coder marker process block and AHB slave interface control as shown in Figure 22 1 Both input output image data bus and compressed data bus are 8 bits It has control registers inside It is possible to set the operation modes specify the Huffman table number and DRI value into these registers FEATURE The JPEG CODEC includes the following features z Compression decompression up to...

Page 741: ...ontrol circuit internal registers AHB interface YUV4 2 2 RGB565 JPEG Codec JPG file YUV4 2 2 YUV4 2 0 Encoding Decoding JPG file YUV4 4 4 YUV4 2 2 YUV4 2 0 Gray JPEG Codec YUV4 2 2 Figure 22 1 JPEG Codec Block Diagram FUNCTIONAL DESCRIPTIONS CONTROL CIRCUIT AHB INTERFACE This block sets and initializes the operation mode It consists of in built registers It is possible to set the operation modes q...

Page 742: ...s is the RAM area where users can allocate HUFFMAN TABLE It is the place to store Huffman tables This is the RAM area where users can allocate REGISTER ACCESS The registers can be modified 1 After reset until a new job starts Or 2 After process completion interruption signal is generated until a new job starts Other conditions indicate that the core is in the normal operation therefore no modifica...

Page 743: ... the image size and sampling factor are ready to be read out after the marker analysis For interrupt 1 the normal process is finished To clear the pending interrupt request read the JPGSTS register If there no encoding or decoding error JPGIRQ will be read as 0x40 Canceling the interrupt 2 is also done by reading JPGIRQ If there is no header parsing error it will be read as 0x08 The interrupt 2 in...

Page 744: ...ring decompression The other markers except SOF1 SOFF and JPG will be ignored BITSTREAM OF COMPRESSED FILE The created JPEG Bit Stream is shown below SOI DQT DRI SOF0 DHT SOS ECS EOI Figure 22 3 Bit stream of JPEG file Block Diagram PROGRAMMER S MODEL Process start command instructs to start the encoding or decoding process of one frame after setting various registers It is set by writing 0x1 on t...

Page 745: ...e3 entry register Essential HDTBL0 HDCTBLG0 DC Huffman table0 entry register Essential HACTBL0 HACTBLG0 AC Huffman table0 entry register Essential HDCTBL1 HDCTBLG1 DC Huffman table1 entry register Essential HACTBL1 HACTBLG1 AC Huffman table1 entry register Essential The contents of any register in Table 2 will not be changed unless they are written again or they are reset Therefore it is possible ...

Page 746: ...e 22 4 Example flow chart of basic encoding Take the following steps for basic JPEG encoding 1 Set the process mode to encoding process and sub sampling mode in JPGMOD 2 Set the MCU and RST marker register JPGDRI 3 Set the Q and H table number register JPGQHNO 4 Set the JPGY and JPGX registers 5 Set the Coefficient register COEFF1 COEFF2 COEFF3 for color space conversion 6 Set the QTABLE and HTABL...

Page 747: ...ead JPGSTS Decoding more frame Figure 22 5 Example flow chart of software controlled decoding Take the following steps for software controlled JPEG decoding 1 Set the process mode to decoding process in JPGMOD 2 Set the destination address of 1st decoded image data IMG_ADDR0 and 2nd decoded image data address IMG_ADDR1 3 Set the source address of 1st JPEG file HUFADDR0 and next JPEG file Address H...

Page 748: ...Set MISC Set SW_JSTART N Encoding proc Finished Figure 22 6 Example flow chart of hardware controlled decoding Take the following steps for hardware controlled JPEG decoding 1 Set the process mode to decoding process in JPGMOD 2 Set the destination address of 1st decoded image data IMG_ADDR0 and 2nd decoded image data address IMG_ADDR1 3 Set the source address of 1st JPEG file HUFADDR0 and next JP...

Page 749: ...U which inserts RST marker 0x00000000 JPGY 0x78800010 R W Vertical resolution 0x00000000 JPGX 0x78800014 R W Horizontal resolution 0x00000000 JPGCNT 0x78800018 R The amount of the compressed data in bytes JPGIRQS 0x7880001C R W Interrupt setting register 0x00000000 JPGIRQ 0x78800020 R Interrupt status register QTBL0 0x78800400 0x788004FC W 8 bit Quantization of table number 0 64 data with the dist...

Page 750: ...0C00 0x78800C3C W The number of code per code length 16 data with the distance of 4 on address 8 bits register HDCTBLG1 0x78800C40 0x78800C6C W Group number of the order for occurrence 12 data with the distance of 4 on address 8 bits register HACTBL1 0x78800C80 0x78800C8C W The number of code per code length 16 data with the distance of 4 on address 8 bits register HACTBLG1 0x78800CC0 0x78800F44 W...

Page 751: ...bCr converter 0x00000000 COEF2 0x78801024 R W Coefficient values for RGB YCbCr converter 0x00000000 COEF3 0x78801028 R W Coefficient values for RGB YCbCr converter 0x00000000 MISC 0x7880102C R W Miscellaneous 0x00000000 JPGMOD Register Address Description Reset Value JPGMOD 0x78800000 Process mode register 0x00000000 JPGMOD Bit R W Description Reserved 31 4 Reserved Process_Mode 3 R W Process mode...

Page 752: ...NO Bit R W Description Reserved 31 14 Reserved Q_table_num3 13 12 R W Quantization table number for the 3rd color component Q_table_num2 11 10 R W Quantization table number for the 2nd color component Q_table_num1 9 8 R W Quantization table number for the 1st color component Reserved 7 6 R W Reserved H_table_num3_ac 5 R W Huffman table number for the 3rd color component AC H_table_num3_dc 4 R W Hu...

Page 753: ...nterval 15 0 R W It is the reset interval that identifies the distance between two adjacent RST markers in terms of MCU Note It is valid only in compression When JPGDRI is set zero DRI and RST markers will not be inserted JPGY Register Address Description Reset Value JPGY 0x78800010 Vertical resolution 0x00000000 JPGY Bit R W Description Reserved 31 16 Reserved VSIZE 15 0 R W It defines the image ...

Page 754: ...JPGIRQS Register Address Description Reset Value JPGIRQS 0x7880001C Interrupt setting register 0x00000000 JPGIRQS Bit R W Description Reserved 31 4 Reserved Intr_enb 3 R W Interrupt enable control 0 Disable to read the image size and sampling factor value in the result of compressed data analysis during decompression 1 Enable to read the image size and sampling factor value in the result of compre...

Page 755: ...Valid during Decompression only 0 Image size and sampling factor value cannot be read 1 Image size and sampling factor value can be read Reserved 2 0 Reserved Note The value of this register will be reset after reading QTBL0 Register Address Description Reset Value QTBL0 0x78800400 0x788004FC 8 bit Quantization of table number 0 64 data with the distance of 4 on address QTBL0 Bit R W Description R...

Page 756: ...2 Register Address Description Reset Value QTBL2 0x78800600 0x788006FC 8 bit Quantization of table number 2 64 data with the distance of 4 on address QTBL2 Bit R W Description Reserved 31 8 Reserved Q_val2 7 0 W It defines the quantizer table 2 The user must write some value in this Note Address offset is increased as 0x04 word addressing QTBL3 Register Address Description Reset Value QTBL3 0x7880...

Page 757: ...nes the number of code per code length in DC Huffman table 0 The user must write some value in this Note Address offset is increased as 0x04 word addressing HDCTBLG0 Register Address Description Reset Value HDCTBLG0 0x78800840 0x7880086C Group number of the order for occurrence 12 data with the distance of 4 on address HDCTBLG0 Bit R W Description Reserved 31 8 Reserved H_DC_G_val0 7 0 W It define...

Page 758: ...CTBLG0 0x788008C0 0x78800B44 Group number of the order for occurrence Group number 162 data with the distance of 4 on address HACTBLG0 Bit R W Description Reserved 31 8 Reserved H_AC_G_val0 7 0 W It defines the group number of the order for occurrence in AC Huffman table 0 The user must write some value in this Note Address offset is increased as 0x04 word addressing HDCTBL1 Register Address Descr...

Page 759: ...group number of the order for occurrence in DC Huffman table 1 The user must write some value in this Note Address offset is increased as 0x04 word addressing HACTBL1 Register Address Description Reset Value HACTBL1 0x78800C80 0x78800CBC The number of code per code length 16 data with the distance of 4 on address 8 bits register HDCTBL1 Bit R W Description Reserved 31 8 Reserved H_AC_val1 7 0 W It...

Page 760: ...GADDR0 0x78801000 Source or destination image address 0 0x0000_0000 IMGADDR0 Bit R W Description Image_addr0 31 0 R W Source or destination Image address 0 IMGADDR1 Register Address Description Reset Value IMGADDR1 0x78801004 Source or destination image address 1 0x0000_0000 IMGADDR1 Bit R W Description Image_addr1 31 0 R W Source or destination Image address 1 IMGADDR0 and IMGADDR1 are the start ...

Page 761: ...scription Huff_addr1 31 0 R W Source or destination JPEG file address 1 HUFADDR0 and HUFADDR1 are the start address for JPEG data Both encode mode and decode mode JPEG data are stored or read from this address If process encoding or decoding is ended HUFADDR0 or HUFADDR1 are swapped SW_JSTART Register Address Description Reset Value SW_JSTART 0x78801010 Start JPEG process 0x0000_0000 SW_JSTART Bit...

Page 762: ... mean high HD_IRQ value are detected S_JRSTART command is set high to start main decoding process SW_RESET_CON Register Address Description Reset Value SW_RESET_CON 0x78801018 SW Reset JPEG 0x0000_0001 SW_RESET_CON Bit R W Description Reserved 31 1 Reserved S_RESET 0 R W 0 Soft Reset enable 1 Soft Reset disable If S_RESET flag is low all registers except SW_RESET_CON are soft reset JPGCON Register...

Page 763: ...1 23 16 R W Coefficient value of COEF11 Reserved 15 8 Reserved COEF13 7 0 R W Coefficient value of COEF13 COEF2 Register Address Description Reset Value COEF2 0x78801024 Coefficient values for RGB YCbCr converter 0x0000_0000 COEF2 Bit R W Description Reserved 31 24 Reserved COEF21 23 16 R W Coefficient value of COEF21 COEF22 15 8 R W Coefficient value of COEF22 COEF23 7 0 R W Coefficient value of ...

Page 764: ...ionship matrix between RGB and YCbCr format MISC Register Address Description Reset Value MISC 0x7880102C Miscellaneous 0x0000_0000 MISC Bit R W Description Reserved 31 8 Reserved MODE_SEL 7 5 R W Mode selector 0x1 Memory YCbCr4 2 2 0x2 Memory RGB 565 Others are prohibited Reserved 4 2 Reserved It has to be zero MODE_Y16 1 R W MODE_Y16 0 c1 0 1 c1 16 Refer to the explanation of COEF11 COEF33 Reser...

Page 765: ...t_partial_lines signal is set to high Setting the signal high makes the JPEG unit decodes the next 8 or 16 lines of the decoded image This process repeats until the decoding is completed The JPEG unit always stores every group of the partial lines from the memory address indicated by the IMG_ADDRESS SFR The image source format of the encoded image determines the size of each group of the partial l...

Page 766: ...and the Modem chip can access that SRAM buffer using a typical asynchronous SRAM interface The size of the SRAM buffer is 8KByte For the buffer status and Interrupt Requests this specification also specifies a few of pre defined special addresses The Modem chip can write data in the data buffer and write interrupt control data to the interrupt port address for the interrupt request to the AP The A...

Page 767: ... dual port SRAM buffer Interrupt request for data exchange Programmable interrupt port address Memory Map Register Address R W Description Reset Value MSBM 0x74100000 0x74101FFF R W MSM I F SRAM buffer memory AP side 0x00000000 Register Address R W Description Reset Value INT2AP 0x74108000 R W Interrupt request to AP Register 0x00001FFE INT2MSM 0x74108004 R W Interrupt request to MSM modem Registe...

Page 768: ...pt is requested when The Interrupt is cleared when To AP 0x1FFE Modem chip writes AP writes to MSMINTCLR register in MSM interface block 2 To Modem 0x1FFC bit15 0 AP writes at least one bit High Modem chip writes High to the bits Note 1 This address is default value It can be set to the other value by the SFR Note 2 Modem interface block has one Interrupt Clear Registers MSMINTCLR Level type inter...

Page 769: ...ovides the boot area 8Kbyte memory for MODEM MODEM can boot using internal Dual Port SRAM memory inside MODEM_IF block In this case AP should provide MODEM Reset pin and AP should complete boot operation Also AP should download the MODEM boot code into its Dual Port SRAM If the chip select of the MODEM is connected to XhiCSn MODEM can boot without its external Boot Memory NAND Modem Host AP Client...

Page 770: ...al Modem Modem I F Indirect Modem I F Direct Modem I F SYSCON Stepping Stone M S S GPIO 8KByte DPRAM S M Boot Memory ARM WDT 1 2 3 1 AP write boot pgm to DPRAM read from NAND 2 AP release BB reset 3 BB read boot pgrm from Direct modem I F Figure 23 3 AP Booting for MODEM boot procedure Note 1 Reset pin of the MODEM is controlled the GPIO pin of the AP The pin must be in pull down mode when the ini...

Page 771: ...0x000 0x004 0x008 0x1FFC 0x00C 0x74100000 0x74100004 0x74100008 0x74101FFC 0x7410000C Modem half word Dual Port SRAM Buffer word Address map of S3C6400X word 8K Bytes buffer SRAM area 0x74108000 0x74108004 MSMIF AHB side SFR modem interface area 0x000 0x002 0x1FFE 0x1FFC 0x1FFA 0x1FF8 0x004 0x006 0x74108008 0x7410800C XhiADR 12 0 0x000 0x001 0x002 0x003 0x0FFF 0x0FFE 0x0FFD 0x0FFC One address of t...

Page 772: ...hen XhiCSn 0 Address mapping of the Modem Side is following XhiADDR 12 11 8 7 Host Modem Interface select description 0 XXX X Modem Interface Direct interface 1 0000 X Host Interface Indirect interface Xhi_ADDR 2 0 Indirect Host I F Xhi_ADDR 2 1 MDPIF 1 0001 0 SLEEP STOP mode Wakeup assert Write Operation 1 0001 1 SLEEP STOP mode Wakeup clear Write Operation 1 100X X LCD Bypass main 1 101X X LCD B...

Page 773: ... herein are subject to change without notice Timing Diagram XhiADR XhiCSn XhiWEn XhiDATA tAVWR tCSVWR tDHWR tWR tDSUWR tAWR Figure 23 5 Modem interface write timing diagram Table 23 2 Modem interface write timing Parameter Description Min ns Max ns Notes tAVWR Address valid to address invalid 16 ns tCSVWR Chip select active 16 ns tAWR Address valid to write active 4 ns tWR Write active 8 ns tDSUWR...

Page 774: ...iDATA tAVRD tCSVRD tACSDV tRD tRDH tRDDV tADH tCSRD Figure 23 6 Modem interface read timing diagram Table 23 3 Modem interface read timing Parameter Description Min ns Max ns Notes tAVRD Address valid to address invalid 50 ns tADH Address hold 0 ns tCSVRD Chip select active 50 ns tCSRD Chip select active to Read active 14 ns tRD Read active 36 ns tRDDV Read active to data valid 35 ns tRDH Read dat...

Page 775: ...ter INT2AP Register address R W Description Reset Value INT2AP 0x74108000 R W Interrupt request to AP register 0x00001FFE INT2AP Bit Description Initial State Reserved 31 13 Reserved 0 INT2AP_ADR 12 0 Modem interface requests the interrupt to AP when modem chip writes this address This interrupt is cleared by the interrupt controller of AP and write access to the MSMINTCLR register 1FFE Interrupt ...

Page 776: ...rved 1 Reserved 0 Fixed 0 Fixed to 0 0 Modem Interface Port Control Register MIFPCON Register Address R W Description Reset Value MIFPCON 0x7410800C R W Modem Interface Port Control register 0x00000008 MIFCON Bit Description Initial State Reserved 31 6 0 Reserved 5 Fixed to 0 0 INT2M_LEVEL 4 Interrupt to MSM Modem Active High MSM_nIRQ interrupt signal make active high when this bit is set to High ...

Page 777: ...r Register MSMINTCLR Register Address R W Description Reset Value MSMINTCLR 0x74108010 W MSM Modem Interface Pending Interrupt Request Clear MSMINTCLR Bit Description Initial State 31 0 Write access to this register with any data will clear the interrupt pending register of MSM modem interface Note The interrupt controllers of AP S3C6400X VIC receive level triggered type interrupt requests Therefo...

Page 778: ...t access of the external host device Ex Modem Chip By the selected host interface protocol the following operations are supported z Read of a 16 bit protocol register z Write of a 16 bit protocol register z Single Write on the SFR memory in the system memory map z Single Read from the SFR memory in the system memory map z Burst Write on the SFR memory in the system memory map z Burst Read from the...

Page 779: ...change without notice AP S3C6400 HOST IF Indirect Host I F CPUIF_CLIENT M M External Modem MODEM IF Direct Modem I F LCD Bypass CPU I F To LCD out S S MODEM_IF Decoder Address Decoding MDP I F S M a b c d Figure 24 2 Data flow of the the External Host device MODEM and the AP The External Host Interface of the AP supports a the Direct Modem Interface path MODEM_IF b Indirect Modem Interface path HO...

Page 780: ...en XhiCSn 0 Address mapping of the Modem Side is following XhiADDR 12 11 8 7 Host Modem Interface select description 0 XXX X Modem Interface Direct interface 1 0000 X Host Interface Indirect interface Xhi_ADDR 2 0 Indirect Host I F Xhi_ADDR 2 1 MDPIF 1 0001 0 SLEEP STOP mode Wakeup assert Write Operation 1 0001 1 SLEEP STOP mode Wakeup clear Write Operation 1 100X X LCD Bypass main 1 101X X LCD By...

Page 781: ...Write FIFO and Read FIFO to support burst write read transfer up to 1 Kbytes z A 32 bit in mailbox register and a 32 bit out mailbox register for data exchange Functional Description hDATAL a 16 bit lower data hDATAH a 16 bit upper data hDATA a 32 bit data a A 32 bit Protocol Register Write Read hDATAL ie lower 16 bits Read hDATAH ie upper 16 bits Read hDATA b A 32 bit Protocol Register Read BSEL ...

Page 782: ...ocol Register To access a 16 bit protocol register take the following steps 1 First select a corresponding bank by writing BSEL then 2 Read or write the protocol register Read and Write of Two 16 bit Protocol Registers in the Same Bank To access two 16 bit protocol registers in the same bank take the following steps 1 First select a corresponding bank by writing BSEL 2 Read or write the lower 16 b...

Page 783: ...t Read from a Source area A is issued and Single Read from a Source area B is issued without waiting for the result of Burst Read the result of Single Read can arrive at the read buffer earlier As a result the address of the received result must be compared with the requested address However for multiple Read operations to the same Source area the orders of the results are maintained The simple wa...

Page 784: ...are not yet available Specifications and information herein are subject to change without notice Burst Write hDATA a 32 bit address hDATA a 32 bit data CTRL RW Write BLEN 1 Read STAT STAT 15 8 BLEN 3 2 Single Burst Packet is sent from Write_FIFO BLEN times Change Bank BSEL Select Bank 0 Change Bank BSEL Select Bank 8 Figure 24 6 Burst Write Procedure Burst Read Figure 24 7 Burst Read Procedure ...

Page 785: ...the CPUIF Client as shown in Figure 24 7 Then the CPU initializes the DMA with source information i e the start address1 and data length2 of the large data and destination information i e a 32b address where the CPU interface3 is mapped While the DMA reads a large data from source and writes them into the CPU interface port the CPU can execute the remaining jobs This scheme can be also applied to ...

Page 786: ...Host Modem controls AP booting including Reset In this case AP does not need to have External Boot Memory NAND Modem download the AP boot code from its Boot Memory to the Stepping Stone memory area 4Kbyte inside AP through HOST I F indirect modem I F block Then Modem assert the boot done bit 0 field in the SYS_CTRL register signal for release CPU operation of the AP Modem Host AP Client Boot Memor...

Page 787: ...t to change without notice NFCON External Modem Modem I F Indirect Modem I F Direct Modem I F ARM SYSCON Stepping Stone M S S GPIO 8KByte DPRAM S SYSTEM BUS M Boot Memory WDT OM 1 Modem release AP Reset All system except ARM and WDT go to normal state 2 Modem write booting code to S S Thru Indirect Host I F 3 Modem set boot done field HOST I F SFR to High 4 SYSCON release reset to ARM and WDT so A...

Page 788: ...e freely defined by the application The in mailbox flag in the CPUIF Client is automatically cleared when the AP S3C6400 s CPU reads the in mailbox When the AP S3C6400 s CPU writes a 32 bit data into the out mailbox the CPUIF Client generates an interrupt to the modem so that the modem will read the out mailbox to know the requests from the AP S3C6400 s CPU The format of the out mailbox can be fre...

Page 789: ...ansfer a bulk data from the host to AP S3C6400 the host first writes the data into a memory in AP S3C6400 by using Burst Write of the CPUIF Client After checking the completion of Burst Write by reading the status register ie STAT 1 0 the host writes a message into the in mailbox In order to transfer a bulk data from the AP S3C6400 to the host AP S3C6400 first prepares the data in its memory and w...

Page 790: ...erface by modem and 2 Special Function Registers that are accessed through SYSTEM bus by the bus master By using protocol registers modem can execute the following operations 1 Single transfer Host Interface 2 Burst transfer Host Interface 3 Reading of all address areas of the S3C6400 including Special Function Registers 4 Writing of all address areas of the S3C6400 including Special Function Regi...

Page 791: ...atus Register 0x90A2 CTRL1 00 R W Control1 Register 0x0000 INTE1 01 R W Interrupt Enable1 Register 0x0000 STAT1 0x1 10 R Status1 Register 0x0002 IMBL 00 R W In Mail Box Low Register 0x0000 IMBH 0x2 01 R W In Mail Box High Register 0x0000 OMBL 00 R Out Mail Box Low Register 0x0000 OMBH 0x3 01 R Out Mail Box High Register 0x0000 hDATAL 00 R W Host Interface Data Low Register hDATAH 0x8 01 R W Host I...

Page 792: ...4 0100 Bank5 0101 Bank6 0110 Bank7 0111 00 CTRL CTRL1 IMBL OMBL Reserved Reserved Reserved Reserved 01 INTE INTE1 IMBH OMBH Reserved Reserved Reserved Reserved 10 STAT STAT1 reserved reserved Reserved Reserved Reserved Reserved 11 BSEL 3 0 Table 24 3 Protocol Register Matrix Bank8 Bank15 Protocol Register Selected by BSEL 3 0 MP_A 1 0 Bank8 1000 Bank9 1001 Bank10 1010 Bank11 1011 Bank12 1100 Bank1...

Page 793: ...urst Write is treated as Repeated Burst Write 0 CPUIF_RESET 2 Reset of the CPUIF Client 0 This bit is used a soft reset signal of the CPUIF Client 1 Therefore this bit must be de asserted by software 0 Reserved 1 This field must be fixed to 0 0 READ_WRITE 0 Read or Write 0 Write operation 1 Read operation 0 Interrupt Enable Register INTE BSEL 3 0 0000 MP_A 1 0 01 R W Reset value 0x2000 Field Bit D...

Page 794: ...ifo so that the CPU can write 16 words immediately Note that the reset value is 0x90 so that 288 words can be written without overflow Practically since the packet head and address must be written into WFIFO the recommend maximum data payload size is 256 word 0x90 WFIFO_PEMPTY 7 WFIFO partial empty flag from CPUIF_CLIENT itself This flag becomes 1 when the number of empty elements in WFIFO is larg...

Page 795: ...y Default 01 3ns delay 10 1ns delay 11 0ns delay 00 Interrupt Enable1 Register INTE1 BSEL 3 0 0001 MP_A 1 0 01 R W Reset value 0x0000 Field Bit Description Initial State Reserved 15 2 0 IMB_EMPTY 1 IMB empty interrupt enable Interrupt occurs when INTE1 1 1 and STAT1 1 1 0 OMB_FILLED 0 OMB filled interrupt enable Interrupt occurs when INTE1 0 1 and STAT1 0 1 0 Status1 Register STAT1 BSEL 3 0 0001 M...

Page 796: ...Bit Description Initial State IMBH 15 0 Upper 16 bits of In Mail Box register After CPU writes a 16 bit data into IMBH CPUIF Client asserts IMB_flag an internal signal in order to notify that a 32 bit IMB contains a new value IMB_flag is automatically cleared when IMB is read by software 0x0000 Out Mail Box Low Register OMBL BSEL 3 0 0011 MP_A 1 0 00 R Reset value 0x0000 Field Bit Description Init...

Page 797: ... Bit Description Initial State DATAH 15 0 Data Register System Control Register SYS_CTRL BSEL 3 0 1011 MP_A 1 0 00 R W Reset value 0x0000 Field Bit Description Initial State Reserved 15 1 Data Register 0 BOOTDONE 0 Boot Done for Modem Booting When this bit is set to High boot done signal is asserted to System Controller S3C6400 AP boot operation starts Host Modem must clear this bit to Low after M...

Page 798: ... W CPUIF Client Temporary Register 0x0000_0000 Reserved 0x00C Reserved 0x0000_0000 CPUIFC_IMB 0x010 R CPUIF Client IMB Register 0x0000_0000 CPUIFC_OMB 0x014 R W CPUIF Client OMB Register 0x0000_0000 CPUIFC_MR_STAT 0x020 R W CPUIF Client Status Mirrored Register 0x0000_90A2 CPUIFC_MR_STAT1 0x024 R W CPUIF Client Status1 Mirrored Register 0x0000_0002 CPUIFC_STAT2 0x028 R W CPUIF Client Status2 Regis...

Page 799: ...W when an interrupt occurs Note INV_INTR field of the HOST I F block and INT2M_LEVEL of the MODEM I F block must have same polarity 1 Reserved 28 24 Reserved 0x0 Reserved 23 16 Reserved 0xFF Reserved 15 9 Reserved 0x0 Reserved 8 0 Reserved 0x100 CPUIF Client Temporary Register CPUIFC_TMP Offset 0x08 R W Reset Value 0x0000_0000 Field Bit Description Initial State DATA 31 0 Temporary register This r...

Page 800: ...e subject to change without notice CPUIF Status Mirrored Register CPUIFC_MR_STAT Offset 0x20 R W Reset Value 0x0000_90A2 Field Bit Description Initial State Reserved 31 16 Reserved 0x0000 STAT 15 0 Mirrored Protocol Register of STAT 15 0 0x90A2 CPUIF Status1 Mirrored Register CPUIFC_MR_STAT1 Offset 0x24 R W Reset Value 0x0000_0002 Field Bit Description Initial State Reserved 31 16 Reserved 0x0000 ...

Page 801: ...17 IMB In Mail Box filled flag This flag is set when the in mailbox is written by the modem In order to clear this flag HIGH value should be written in this bit 0 OMB_EMPTY 16 OMB Out Mail Box empty flag This flag is an inversion of the OMB_FILLED ie STAT1 0 1 Reserved 15 8 Reserved 0x00 L_RFIFO_OVER_RUN 7 The over run flag of Local RFIFO L_RFIFO in the CPUIF Client HOSTIF 0 L_RFIFO_UNDER_RUN 6 Th...

Page 802: ... INTERFACE 24 25 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice ...

Page 803: ...0_2000 Field Bit Description Initial State Reserved 31 16 0x0000 INTE 15 0 Mirrored Protocol Register of INTE 15 0 0x2000 CPUIF Interrupt Enable1 Mirrored Register CPUIFC_MR_INTE1 Offset 0x34 R W Reset Value 0x0000_0000 Field Bit Description Initial State Reserved 31 16 0x0000 INTE1 15 0 Mirrored Protocol Register of INTE1 15 0 0x0000 CPUIF Interrupt Enable2 Register CPUIFC_INTE2 Offset 0x38 R W R...

Page 804: ... INTERFACE 24 27 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice ...

Page 805: ...1 0 compatible USB Rev1 1 compatible Two down stream ports Support for both LowSpeed and FullSpeed USB devices HCI SLAVE BLOCK APP_SADR 8 APP_SDATA 32 HCI_DATA 32 CONTROL CONTROL OHCI REGS USB STATE CONTROL LIST PROCESSOR BLOCK ED TD REGS Cntl HCI MASTER BLOCK CONTROL ED TD_DATA 32 ED TD STATUS 32 64x8 FIFO Cntl HC_DATA 8 DF_DATA 8 APP_MDATA 32 HCM_ADR DATA 32 CONTROL STATUS CONTROL CTRL CTRL RH_D...

Page 806: ...Interrupt Status Register 0x0000_0000 HcInterruptEnable 0x74300010 R W USB Host Controller Interrupt Enable Register 0x0000_0000 HcInterruptDisable 0x74300014 R W USB Host Controller Interrupt Disable Register 0x0000_0000 HcHCCA 0x74300018 R W USB Host Controller HCCA Register 0x0000_0000 HcPeriodCuttentED 0x7430001C R USB Host Controller Period Current ED Register 0x0000_0000 HcControlHeadED 0x74...

Page 807: ...Host Controller Root Hub Descriptor A Register 0x0200_1202 HcRhDescriptorB 0x7430004C R W USB Host Controller Root Hub Descriptor B Register 0x0000_0000 HcRhStatus 0x74300050 R W USB Host Controller Root Hub Status Register 0x0000_0000 HcRhPortStatus1 0x74300054 R W USB Host Controller Root Hub Port Status 1 Register 0x0000_0100 HcRhPortStatus2 0x74300058 R W USB Host Controller Root Hub Port Stat...

Page 808: ...SB2 0 HS OTG features include the following z Complies with the On The Go Supplement to the USB 2 0 Specification Revision 1 0a z Operates in High Speed 480 Mbps Full Speed 12 Mbps and Low Speed 1 5 Mbps Host only modes z Supports UTMI Level 3 interface Revision 1 0 z Supports SRP Session Request Protocol and HNP Host Negotiation Protocol z Supports only 32 bit data on the AHB z 1 Control Endpoint...

Page 809: ...S OTG controller is composed of two independent blocks USB 2 0 OTG Link Core and USB 2 0 PHY Control Each has an AHB Slave which provides the microcontroller with read and write access to the Control and Status Registers CSRs The OTG Link has an AHB Master to enable the link to transfer data on the AHB The S3C6400x USB system shown in Figure 26 1 can be configured as following 1 USB 1 1 Host 1 Por...

Page 810: ...action level operation The application handles one data packet at a time per channel endpoint in transaction level operations In pipelined transaction level operation the application can program the OTG to perform multiple transactions The advantage of pipelined operation is that the application is not interrupted on packet basis SYSTEM CONTROLLER SETTING A register in SYSTEM CONTROLLER has to be ...

Page 811: ...sified as follows Core Global Registers Host Mode Registers Host Global Registers Host Port CSRs Host Channel Specific Registers Device Mode Registers Device Global Registers Device Endpoint Specific Registers Only the Core Global and Host Port registers can be accessed in both Host and Device modes When the OTG Link is operating in either Device or Host mode the application must not access regist...

Page 812: ...map Host and Device mode registers occupy different addresses All registers are implemented in the AHB Clock domain OTG LINK BASE 0000h OTG LINK BASE 0400h OTG LINK BASE 0800h OTG LINK BASE 0E00h OTG LINK BASE 1000h OTG LINK BASE 2000h OTG LINK BASE 3000h OTG LINK BASE F000h OTG LINK BASE 10000h Core Global CSRs 1 KB Host Mode CSRs 1 KB Device Mode CSRs 1 5 KB Reserved Device EP 0 Host Channel 0 F...

Page 813: ...il in the field s description Read Write Self Set and Self Clear R_W_SS_SC Register field can be read and written by the application Read and Write set to 1 b1 by the core on certain USB events Self Set and cleared to 1 b0 by the core Self Clear Read Self set and Write Clear R_SS_WC Register field can be read by the application Read can be set to 1 b1 by the core on certain internal or USB or AHB ...

Page 814: ... 0x024 R W Receive FIFO Size Register 0x0000_1800 GNPTXFSIZ 0x028 R W Non Periodic Transmit FIFO Size Register 0x1800_1800 GNPTXSTS 0x02C R Non Periodic Transmit FIFO Queue Status Register 0x0008_1800 HPTXFSIZ 0x100 R W Host Periodic Transmit FIFO Size Register 0x0300_5A00 DPTXFSIZ1 0x104 R W Device Periodic Transmit FIFO 1 Size Register 0x0300_3000 DPTXFSIZ2 0x108 R W Device Periodic Transmit FIF...

Page 815: ...DMA Address Register 0x0000_0000 HCCHAR1 0x520 R W Host Channel 1 Characteristics Register 0x0000_0000 HCSPLT1 0x524 R W Host Channel 1 Spilt Control Register 0x0000_0000 HCINT1 0x528 R W Host Channel 1 Interrupt Register 0x0000_0000 HCINTMSK1 0x52C R W Host Channel 1 Interrupt Mask Register 0x0000_0000 HCTSIZ1 0x530 R W Host Channel 1 Transfer Size Register 0x0000_0000 HCDMA1 0x534 R W Host Chann...

Page 816: ...l 6 DMA Address Register 0x0000_0000 HCCHAR7 0x5E0 R W Host Channel 7 Characteristics Register 0x0000_0000 HCSPLT7 0x5E4 R W Host Channel 7 Spilt Control Register 0x0000_0000 HCINT7 0x5E8 R W Host Channel 7 Interrupt Register 0x0000_0000 HCINTMSK7 0x5EC R W Host Channel 7 Interrupt Mask Register 0x0000_0000 HCTSIZ7 0x5F0 R W Host Channel 7 Transfer Size Register 0x0000_0000 HCDMA7 0x5F4 R W Host C...

Page 817: ...l 13 Characteristics Register 0x0000_0000 HCSPLT13 0x6A4 R W Host Channel 13 Spilt Control Register 0x0000_0000 HCINT13 0x6A8 R W Host Channel 13 Interrupt Register 0x0000_0000 HCINTMSK13 0x6AC R W Host Channel 13 Interrupt Mask Register 0x0000_0000 HCTSIZ13 0x6B0 R W Host Channel 13 Transfer Size Register 0x0000_0000 HCDMA13 0x6B4 R W Host Channel 13 DMA Address Register 0x0000_0000 HCCHAR14 0x6C...

Page 818: ...x914 R W Device IN Endpoint 0 DMA Address Register 0x0000_0000 DIEPCTL1 0x920 R W Device Control IN Endpoint 1 Control Register 0x0000_0000 DIEPINT1 0x928 R W Device IN Endpoint 1 Interrupt Register 0x0000_0000 DIEPTSIZ1 0x930 R W Device IN Endpoint 1 Transfer Size Register 0x0000_0000 DIEPDMA1 0x934 R W Device IN Endpoint 1 DMA Address Register 0x0000_0000 DIEPCTL2 0x940 R W Device Control IN End...

Page 819: ...0 DIEPDMA9 0xA34 R W Device IN Endpoint 9 DMA Address Register 0x0000_0000 DIEPCTL10 0xA40 R W Device Control IN Endpoint 10 Control Register 0x0000_0000 DIEPINT10 0xA48 R W Device IN Endpoint 10 Interrupt Register 0x0000_0000 DIEPTSIZ10 0xA50 R W Device IN Endpoint 10 Transfer Size Register 0x0000_0000 DIEPDMA10 0xA54 R W Device IN Endpoint 10 DMA Address Register 0x0000_0000 DIEPCTL11 0xA60 R W ...

Page 820: ...0_0000 DOEPCTL3 0xB60 R W Device Control OUT Endpoint 3 Control Register 0x0000_0000 DOEPINT3 0xB68 R W Device OUT Endpoint 3 Interrupt Register 0x0000_0000 DOEPTSIZ3 0xB70 R W Device OUT Endpoint 3 Transfer Size Register 0x0000_0000 DOEPDMA3 0xB74 R W Device OUT Endpoint 3 DMA Address Register 0x0000_0000 DOEPCTL4 0xB80 R W Device Control OUT Endpoint 4 Control Register 0x0000_0000 DOEPINT4 0xB88...

Page 821: ...0xC74 R W Device OUT Endpoint 11 DMA Address Register 0x0000_0000 DOEPCTL12 0xC80 R W Device Control OUT Endpoint 12 Control Register 0x0000_0000 DOEPINT12 0xC88 R W Device OUT Endpoint 12 Interrupt Register 0x0000_0000 DOEPTSIZ12 0xC90 R W Device OUT Endpoint 12 Transfer Size Register 0x0000_0000 DOEPDMA12 0xC94 R W Device OUT Endpoint 12 DMA Address Register 0x0000_0000 DOEPCTL13 0xCA0 R W Devic...

Page 822: ...al Operation 1 b1 Analog block power down 1 b1 xo_powerdown 2 R_W XO block power down in PHY2 0 1 b0 XO block power up PLL reference is XO block output 1 b1 XO block power down PLL reference is clk_core input Note clk_sel 1 0 bus must be set to 2 b00 1 b1 pll_powerdown 1 R_W PLL power down in PHY2 0 1 b0 PLL power up The digital logic uses a 480 MHz clock 1 b1 PLL power down The digital logic uses...

Page 823: ...nb 5 R_W Reference Clock Select for XO Block 1 b0 external crystal 1 b1 external clock oscillator 1 b0 common_on_n 4 R_W Force XO Bias Bandgap and PLL to Remain Powered During a Suspend This bit controls the power down signals of sub blocks in the Common block when the USB 2 0 OTG PHY is suspended 1 b0 48MHz clock on clk48m_ohci is available at all times except in Suspend mode 1 b1 48MHz clock on ...

Page 824: ...ge without notice Figure 26 3 OTG PHY Clock Path OTG RESET CONTROL REGISTER ORSTCON Register Address R W Description Reset Value ORSTCON 0x7C10_0008 R W OTG Reset Control Register 32 bits ORSTCON Bit R W Description Initial State 31 3 Reserved 29 h0 phylnk_sw_rst 2 R_W OTG Link Core phy_clock domain S W Reset 1 b0 link_sw_rst 1 R_W OTG Link Core hclk domain S W Reset 1 b0 phy_sw_rst 0 R_W OTG PHY ...

Page 825: ...OTG Control and Status Register 32 bits GOTGCTL Bit R W Description Initial State 31 20 Reserved 12 h0 BSesVld 19 RO B Session Valid Indicates the Device mode transceiver status 1 b0 B session is not valid 1 b1 B session is valid 1 b0 ASesVld 18 RO A Session Valid Indicates the Host mode transceiver status 1 b0 A session is not valid 1 b1 A session is valid 1 b0 DbncTime 17 RO Long Short Debounce ...

Page 826: ...t Negotiation Success The core sets this bit when host negotiation is successful The core clears this bit when the HNP Request HNPReq bit in this register is set 1 b0 Host negotiation failure 1 b1 Host negotiation success 1 b0 7 2 Reserved 6 h0 SesReq 1 R_W Session Request The application sets this bit to initiate a session request on the USB The core clears this bit when the HstNegSucStsChng bit ...

Page 827: ...success or failure of a USB host negotiation request 1 b0 SesReqSucStsCh ng 8 R_SS_ WC Session Request Success Status Change The core sets this bit on the success or failure of a session request 1 b0 7 3 Reserved 5 h0 SesEndDet 2 R_SS_ WC Session End Detected The core sets this bit when the b_valid signal is deasserted 1 b0 1 0 Reserved 2 h0 OTG AHB CONFIGURATION REGISTER GAHBCFG This register can...

Page 828: ...Reserved 1 b0 DMAEn 5 R_W DMA Enable 1 b0 Core operates in Slave mode 1 b1 Core operates in a DMA mode 1 b0 HBstLen 4 1 R_W Burst Length Type Internal DMA Mode AHB Master burst type 4 b0000 Single 4 b0001 INCR 4 b0011 INCR4 4 b0101 INCR8 4 b0111 INCR16 Others Reserved 4 b0 GlblIntrMsk 0 R_W Global Interrupt Mask The application uses this bit to mask or unmask the interrupt line assertion to itself...

Page 829: ...p 9 R_W HNP Capable The application uses this bit to control the OTG cores s HNP capabilities 1 b0 HNP capability is not enabled 1 b1 HNP capability is enabled 1 b0 SRPCap 8 R_W SRP Capable The application uses this bit to control the OTG core s SRP capabilities 1 b0 SRP capability is not enabled 1 b1 SRP capability is enabled 1 b0 7 4 Reserved 4 h0 PHYIf 3 R_W PHY Interface The application uses t...

Page 830: ...it selectively flushes a single or all transmit FIFOs but cannot do so if the core is in the midst of a transaction The application must only write this bit after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO The application must wait until the core clears this bit before performing any operations This bit takes 8 clocks to clear 1 b0 RxFFlsh 4 R_WS_ SC RxFIFO...

Page 831: ...ate 1 b0 CSftRst 0 R_WS_ SC Core Soft Reset Resets the hclk and phy_clock domains as follows Clears the interrupts and all the CSR registers except the following register bits HCFG FSLSPclkSel DCFG DevSpd All module state machines except the AHB Slave Unit are reset to the IDLE state and all the transmit FIFOs and the receive FIFO are flushed Any transactions on the AHB Master are terminated as so...

Page 832: ...n Device mode this interrupt is asserted when the b_valid signal goes high 1 b0 DisconnInt 29 R_SS_ WC Disconnect Detected Interrupt Asserted when a device disconnect is detected 1 b0 ConIDStsChng 28 R_SS_ WC Connector ID Status Change The core sets this bit when there is a change in connector ID status 1 b0 27 Reserved 1 b0 PTxFEmp 26 RO Periodic TxFIFO Empty Asserted when the Periodic Transmit F...

Page 833: ...c IN NAK handshake Disables In endpoints Flushes the FIFO Determines the token sequence from the IN Token Sequence Learning Queue Re enables the endpoints Clears the global non periodic IN NAK handshake If the global non periodic IN NAK is cleared the core has not yet fetched data for the IN endpoint and the IN token received the core generates an IN token received when FIFO empty interrupt The OT...

Page 834: ...dicate that an interrupt is pending on one of the IN endpoints of the core in Device mode The application must read the Device All Endpoints Interrupt DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred and then read the corresponding Device IN Endpoint n Interrupt DIEPINTn register to determine the exact cause of the interrupt The application must clear...

Page 835: ...is bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register 1 b0 GINNakEff 6 RO Global IN Non Periodic NAK Effective Indicates that the Set Global Non Periodic IN NAK bit in the Device Control register DCTL SGNPInNak set by the application has taken effect in the core That is the core has sampled the Global IN NAK bit set by the application This bit can be cleared ...

Page 836: ...this interrupt The application must clear the appropriate status bit in the GOTGINT register to clear this bit 1 b0 ModeMis 1 R_SS_ WC Mode Mismatch Interrupt The core sets this bit when the application is trying to access A Host mode register when the core is operating in Device mode A Device mode register when the core is operating in Host mode 1 b0 CurMod 0 RO Current Mode Of Operation Indicate...

Page 837: ...ask 1 b0 16 Reserved 1 b0 EOPFMsk 15 R_W End of Periodic Frame Interrupt Mask 1 b0 ISOOutDropMsk 14 R_W Isochronous OUT Packet Dropped Interrupt Mask 1 b0 EnumDoneMsk 13 R_W Enumeration Done Mask 1 b0 USBRstMsk 12 R_W USB Reset Mask 1 b0 USBSuspMsk 11 R_W USB Suspend Mask 1 b0 ErlySuspMsk 10 R_W Early Suspend Mask 1 b0 9 Reserved 1 b0 8 Reserved 1 b0 GOUTNakEffMsk 7 R_W Global OUT NAK Effective Ma...

Page 838: ...atus Read and Pop Registers 32 bits GRXSTSR GRXSTSP Bit R W Description Initial State 31 21 Reserved 11 h0 PktSts 20 17 RO Packet Status Indicates the status of the received packet 4 b0010 IN data packet received 4 b0011 IN transfer completed triggers an interrupt 4 b0101 Data toggle error triggers an interrupt 4 b0111 Channel halted triggers an interrupt others Reserved 4 b0 DPID 16 15 RO Data PI...

Page 839: ...010 OUT data packet received 4 b0011 OUT transfer completed triggers an interrupt 4 b0100 SETUP transaction completed triggers an interrupt 4 b0110 SETUP data packet received others Reserved 4 b0 DPID 16 15 RO Data PID Indicates the Data PID of the received OUT data packet 2 b00 DATA0 2 b01 DATA1 2 b10 DATA2 2 b11 MDATA 2 b0 BCnt 14 4 RO Byte Count Indicates the byte count of the received data pac...

Page 840: ...31 16 R_W Non Periodic TxFIFO Depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 32768 The power on reset value of this register is specified as the Largest Non Periodic Tx Data FIFO Depth 6144 A new value must be written to this field Programmed values must not exceed the power on value set 16 h1800 NPTxFStAddr 15 0 R_W Non Periodic Transmit Start Address This field...

Page 841: ...odic Transmit Request Queue This queue holds both IN and OUT requests in Host mode Device mode has only IN requests 8 h0 Non Periodic Transmit Request Queue is full 8 h1 1 location available 8 h2 2 locations available n n locations available 0 n 8 Others Reserved NPTxFSpcAvail 15 0 RO Non Periodic TxFIFO Space Available Indicates the amount of free space available in the Non Periodic TxFIFO Values...

Page 842: ...s field Programmed values must not exceed the power on value set 16 h3000 DEVICE PERIODIC TRANSMIT FIFO n SIZE REGISTER DPTXFSIZn FIFO_number 1 n 15 This register holds the memory start address of each periodic TxFIFO to implement in Device mode Each periodic FIFO holds the data for one periodic IN endpoint This register is repeated for each periodic FIFO instantiated Register Address R W Descript...

Page 843: ... 4 16 h3900 n 5 16 h3C00 n 6 16 h3F00 n 7 16 h4200 n 8 16 h4500 n 9 16 h4800 n 10 16 h4B00 n 11 16 h4E00 n 12 16 h5100 n 13 16 h5400 n 14 16 h5700 n 15 16 h5A00 HOST MODE REGISTERS These registers affect the operation of the core in the Host mode Host mode registers must not be accessed in Device mode as the results are undefined Host Mode registers can be categorized as follows Host Global regist...

Page 844: ...OST FRAME NUMBER FRAME TIME REMAINING REGISTER HFNUM This register indicates the current frame number It also indicates the time remaining in the current frame Register Address R W Description Reset Value HFNUM 0x7C00_0408 R Host Frame Number Frame Time Remaining Register 32 bits HFNUM Bit R W Description Initial State FrRem 31 16 RO Frame Time Remaining Indicates the amount of time remaining in t...

Page 845: ... Space Available Indicates the number of free locations available to be written in the Periodic Transmit Request Queue This queue holds both IN and OUT requests 8 h0 Periodic Transmit Request Queue is full 8 h1 1 location available 8 h2 2 location available n n locations available 0 n 8 Others Reserved PTxFSpcAvail 15 0 RO Periodic Transmit Data FIFO Space Available Indicates the number of free lo...

Page 846: ...t R W Description Initial State 31 16 Reserved 16 h0 HAINTMsk 15 0 R_W Channel Interrupt Mask One bit per channel Bit 0 for Channel 0 bit 15 for Channel 15 16 h0 HOST PORT CONTROL AND STATUS REGISTERS HOST PORT CONTROL AND STATUS REGISTER HPRT This register is available in both Host and Device modes Currently the OTG Host supports only one port A single register holds USB port related information ...

Page 847: ...urrent logic level USB data lines Bit 10 Logic level of D Bit 11 Logic level of D 2 b0 9 Reserved 1 b0 PrtRst 8 R_W Port Reset When the application sets this bit a reset sequence is started on this port The application must time the reset period and clear this bit after the reset sequence is complete 1 b0 Port not in reset 1 b1 Port in reset The application must leave this bit set for at least a m...

Page 848: ...1 b0 No resume driven 1 b1 Resume driven 1 b0 PrtOvrCurrChng 5 R_SS_ WC Port Overcurrent Change The core sets this bit when the status of the Port Overcurrent Active bit bit 4 in this register changes 1 b0 PrtOvrCurrAct 4 RO Port Overcurrent Active Indicates the overcurrent condition of the port 1 b0 No overcurrent condition 1 b1 Overcurrent condition 1 b0 PrtEnChng 3 R_SS_ WC Port Enable Disable ...

Page 849: ... channel is complete The application must wait for the Channel Disabled interrupt before treating the channel as disabled 1 b0 OddFrm 29 R_W Odd Frame This field is set reset by the application to indicate that the OTG host must perform a transfer in an odd micro frame This field is applicable for only periodic transactions 1 b0 Even micro frame 1 b1 Odd micro frame 1 b0 DevAddr 28 22 R_W Device A...

Page 850: ...r Indicates the endpoint number on the device serving as the data source or sink 4 h0 MPS 10 0 R_W Maximum Packet Size Indicates the maximum packet size of the associated endpoint 11 h0 HOST CHANNEL n SPLIT REGISTER HCSPLTn Channel_number 0 n 15 Register Address R W Description Reset Value HCSPLTn 0x7C00_0504 n 20h R W Host Channel n Split Register 32 bits HCSPLTn Bit R W Description Initial State...

Page 851: ... must read this register when the Host Channels Interrupt bit of the Core Interrupt register is set Before the application can read this register it must first read the Host All Channels Interrupt register to get the exact channel number for the Host Channel n Interrupt register The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS...

Page 852: ...s register reflects the mask for each channel status described in the previous section Mask interrupt 1 b0 Unmask interrupt 1 b1 Register Address R W Description Reset Value HCINTMSKn 0x7C00_050 C n 20h R W Host Channel n interrupt Mask Register 32 bits HCINTMSKn Bit R W Description Initial State 31 11 Reserved 21 h0 DataTglErrMsk 10 R_W Data Toggle Error Mask 1 b0 FrmOvrunMsk 9 R_W Frame Overrun ...

Page 853: ...ket Once this count reaches zero the application is interrupted to indicate normal completion 10 b0 XferSize 18 0 R_W Transfer Size For an OUT this field is the number of data bytes the host will send during the transfer For an IN this field is the buffer size that the application has reserved for the transfer The application is expected to program this field as an integer multiple of the maximum ...

Page 854: ...ster 32 bits DCFG Bit R W Description Initial State 31 23 Reserved 9 h0 EPMisCnt 22 18 R_W IN Endpoint Mismatch Count The application programs this field with a count that determines when the core generates an Endpoint Mismatch interrupt The core loads this value into an internal counter and decrements it The counter is reloaded whenever there is a match or when the counter expires The width of th...

Page 855: ...ed 2 b00 High speed USB 2 0 PHY clock is 30 Mhz or 60 Mhz 2 b01 Full speed USB 2 0 PHY clock is 30 Mhz or 60 Mhz 2 b10 Low speed USB 1 1 transceiver clock is 6 Mhz If you select 6 MHz LS mode you must do a soft reset 2 b11 Full speed USB 1 1 transceiver clock is 48 Mhz 2 b0 DEVICE CONTROL REGISTER DCTL Register Address R W Description Reset Value DCTL 0x7C00_0804 R W Device Control Register 32 bit...

Page 856: ...1 b1 No data is written to the RxFIFO irrespective of space availability Sends a NAK handshake on all packets except on SETUP transactions All isochronous OUT packets are dropped 1 b0 GNPINNakSts 2 RO Global Non Periodic IN NAK Status 1 b0 A handshake is sent based on the data availability in the transmit FIFO 1 b1 A NAK handshake is sent out on all non periodic IN endpoints irrespective of the da...

Page 857: ...s 2 5μ s High speed Not Idle or Suspended Performing transactions 125μ s Full speed Low speed Suspended 1ms 2 5μ s Full speed Low speed Idle 2 5μ s Full speed Low speed Not Idle or Suspended Performing transactions 2 5μ s DEVICE STATUS REGISTER DSTS This register indicates the status of the core with respect to USB related events It must be read on interrupts from Device ALL Interrupts DAINT regis...

Page 858: ...d of time The core comes out of the suspend When there is any activity on the line_state signal When the application writes to the Remote Wakeup Signaling bit in the Device Control register 1 b0 DEVICE IN ENDPOINT COMMON INTERRUPT MASK REGISTER DIEPMSK This register works with each of the Device IN Endpoint Interrupt registers for all endpoints to generate an interrupt per IN endpoint The IN endpo...

Page 859: ...ndpoint Disabled Applies to control OUT endpoints only 1 b0 SetUPMsk 3 R_W SETUP Phase Done Mask Applies to control endpoints only 1 b0 AHBErrMsk 2 R_W AHB Error 1 b0 EPDisbldMsk 1 R_W Endpoint Disabled Interrupt Mask 1 b0 XferComplMsk 0 R_W Transfer Completed Interrupt Mask 1 b0 DEVICE ALL ENDPOINTS INTERRUPT REGISTER DAINT When a significant event occurs on an endpoint a Device All Endpoints Int...

Page 860: ...Msk 31 16 R_W OUT EP Interrupt Mask Bits One bit per OUT endpoint Bit 16 for OUT EP 0 bit 31 for OUT EP 15 16 h0 InEpMsk 15 0 R_W IN EP Interrupt Mask Bits One bit per IN endpoint Bit 0 for IN EP 0 bit 15 for IN EP 15 16 h0 DEVICE IN TOKEN SEQUENCE LEARNING QUEUE READ REGISTER 1 DTKNQR1 The queue is 4 bits wide to store the endpoint number A read from this register returns the first 5 endpoint ent...

Page 861: ...Bit R W Description Initial State EPTkn 31 0 RO Endpoint Token Four bits per token represent the endpoint number of the token Bits 31 28 Endpoint number of Token 13 Bits 27 24 Endpoint number of Token 12 Bits 7 4 Endpoint number of Token 7 Bits 3 0 Endpoint number of Token 6 32 h0 DEVICE IN TOKEN SEQUENCE LEARNING QUEUE READ REGISTER 3 DTKNQR3 Read from this register returns the next 8 endpoint en...

Page 862: ...number of Token 28 Bits 7 4 Endpoint number of Token 23 Bits 3 0 Endpoint number of Token 22 32 h0 DEVICE VBUS DISCHARGE TIME REGISTER DVBUSDIS This register specifies the Vbus discharge time after Vbus pulsing during SRP Register Address R W Description Reset Value DVBUSDIS 0x7C00_0828 R W Device VBUS Discharge Time Register 32 bits DVBUSDIS Bit R W Description Initial State 31 16 Reserved 16 h0 ...

Page 863: ... 0 Control Register 32 bits DIEPCTL0 Bit R W Description Initial State EPEna 31 R_WS_ SC Endpoint Enable Indicates that data is ready to be transmitted on the endpoint The core clears this bit before setting any of the following interrupts on this endpoint Endpoint Disabled Transfer Completed 1 b0 EPDis 30 R_WS_ SC Endpoint Disable The application sets this bit to stop transmitting data on an endp...

Page 864: ...ore the core stops transmitting data even if there is data available in the TxFIFO Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake 1 b0 16 Reserved 1 b0 USBActEP 15 RO USB Active Endpoint This bit is always set to 1 indicating that control endpoint 0 is always active in all configurations and interfaces 1 b1 NextEp 14 11 R_W Next Endpoint App...

Page 865: ...ble control OUT endpoint 0 1 b0 29 28 Reserved 2 b0 SetNAK 27 WO Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK handshakes on an endpoint The core can also set this bit on a Transfer Completed interrupt or after a SETUP is received on the endpoint 1 b0 CNAK 26 WO Clear NAK A write to this bit clears the NAK bit for t...

Page 866: ...point 0 is always active in all configurations and interfaces 1 b1 14 2 Reserved 13 h0 MPS 1 0 RO Maximum Packet Size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0 2 b00 64 bytes 2 b01 32 bytes 2 b10 16 bytes 2 b11 8 bytes 2 h0 DEVICE ENDPOINT n CONTROL REGISTER DIEPCTLn DOEPCTLn Endpoint_number 1 n 15 The application uses this regist...

Page 867: ... PID Applies to interrupt bulk IN and OUT endpoints only Writing to this field sets the Endpoint Data PID DPID field in this register to DATA1 SetD1PID SetOddFr 29 WO Set Odd micro frame Applies to isochronous IN and OUT endpoints only Writing to this field sets the Even Odd micro frame field to odd micro frame 1 b0 Set DATA0 PID Applies to interrupt bulk IN and OUT endpoints only Writing to this ...

Page 868: ...set this bit and the core clears it when a SETUP token is received for this endpoint If a NAK bit Global Non Periodic IN NAK or Global OUT NAK is set along with this bit the STALL bit takes priority Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake 1 b0 Snp 20 R_W Snoop Mode Applies to OUT endpoints only This bit configures the endpoint to Snoo...

Page 869: ...pplies to isochronous IN and OUT endpoints only Indicates the micro frame number in which the core transmits receives isochronous data for this endpoint The application must program the even odd micro frame number in which it intends to transmit receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register 1 b0 Even micro frame 1 b1 Odd micro frame 1 b0 USBActE...

Page 870: ...ue DIEPINTn DOEPINTn 0x7C00_0908 n 20h 0x7C00_0B08 n 20h R W Device Endpoint n Interrupt Register 32 bits DIEPINTn DOEPINTn Bit R W Description Initial State EPEna 31 7 Reserved 25 h0 IN Endpoint NAK Effective Applies to periodic IN endpoints only Indicates that the IN endpoint NAK bit set by the application has taken effect in the core This bit can be cleared when the application clears the IN en...

Page 871: ...P Phase Done Applies to control OUT endpoints only Indicates that the SETUP phase for the control endpoint is complete and no more back to back SETUP packets were received for the current control transfer On this interrupt the application can decode the received SETUP data packet 1 b0 AHBErr 2 R_SS_ WC AHB Error Applies to IN and OUT endpoints This is generated only in Internal DMA mode when there...

Page 872: ...s the application only after it has exhausted the transfer size amount of data The transfer size can be set to the maximum packet size of the endpoint to be interrupted at the end of each packet The core decrements this field every time a packet from the external memory is written to the TxFIFO 7 h0 DEVICE OUT ENDPOINT 0 TRANSFER SIZE REGISTER DOEPTSIZ0 Register Address R W Description Reset Value...

Page 873: ...gister once the core has cleared the Endpoint Enable bit This register is used only for endpoints other than Endpoint 0 Register Address R W Description Reset Value DIEPTSIZn DOEPTSIZn 0x7C00_0910 n 20h 0x7C00_0B10 n 20h R W Device Endpoint n Transfer Size Register 32 bits DIEPTSIZn DOEPTSIZn Bit R W Description Initial State 31 Reserved 1 b0 Multi Count Applies to IN endpoints only For periodic I...

Page 874: ...ted every time a packet is written to the RxFIFO 10 h0 XferSize 18 0 R_W Transfer Size This field contains the transfer size in bytes for the current endpoint The core only interrupts the application after it has exhausted the transfer size amount of data The transfer size can be set to the maximum packet size of the endpoint to be interrupted at the end of each packet IN Endpoints The core decrem...

Page 875: ...s this address stores control OUT data packets as well as SETUP transaction data packets If multiple SETUP packets are received back to back the SETUP data packet in the memory is overwritten 32 h0 POWER AND CLOCK GATING CONTROL REGISTER PCGCCTL The application can use this register to control OTG s clock gating Register Address R W Description Reset Value PCGCCTL 0x7C00_0E00 R W Power and Clock G...

Page 876: ... HS OTG 26 69 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTE ...

Page 877: ... is compatible for SD Association s SDA Host Standard Specification You can interface your system with SD card and MMC card The performance of this host is very powerful you would get 50Mhz clock rate and access 8 bit data pin simultaneously FEATURES The High Speed MMC controller supports z SD Standard Host Specification ver 1 0 compatible z SD Memory Card Specification ver 2 0 HSMMC Specification...

Page 878: ...d errata are not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM SFR SDCLK Domain HCLK Domain System Bus AHB CMD ARG Control Status AHB slave I F DMA controller AHB master FIFO DATA packet Status Control CMDRSP packet Status Control RSP Line Control Pad I F INTREQ BaseCLK Clock Control DPSRAM Control Figure 27 1 HSMMC block diagram ...

Page 879: ...n the flow chart SD CARD DETECTION SEQUENCE Figure 27 2 SD Card Detect Sequence The flow chart for detecting a SD card is shown in Figure 27 2 Each step is executed as follows 1 To enable interrupt for card detection write 1 to the following bits Card Insertion Status Enable in the Normal Interrupt Status Enable register Card Insertion Signal Enable in the Normal Interrupt Signal Enable register C...

Page 880: ...able Set SD Clock ON End 1 2 3 4 Figure 27 3 SD Clock Supply Sequence The sequence for supplying SD Clock to a SD card is described in Figure 27 3 The clock shall be supplied to the card before one of the following actions is taken a Issuing a SD command b Detect an interrupt from a SD card in 4 bit mode 1 Calculate a divisor to determine SD Clock frequency for SD Clock by reading Base Clock Frequ...

Page 881: ...e flow chart for stopping the SD Clock is shown in Figure 27 4 The Host Driver does not stop the SD Clock when a SD transaction takes place on the SD Bus namely when either Command Inhibit DAT or Command Inhibit CMD in the Present State register is set to 1 1 Set SD Clock Enable in the Clock Control register to 0 Then the Host Controller stops supplying the SD Clock SD CLOCK FREQUENCY CHANGE SEQUE...

Page 882: ...oltage Set SD Bus Power Get OCR value of the SD Card SD Bus voltage changed Clr SD Bus Power Set SD Bus voltage select Set SD Bus Power END 1 2 3 4 5 6 7 8 change no change Figure 27 6 SD Bus Power Control Sequence The sequence for controlling the SD Bus Power is described in Figure 27 6 and steps are described below 1 By reading the Capabilities register get the support voltage of the Host Contro...

Page 883: ...SD Bus Voltage Select in the Power Control register 8 Set SD Bus Power in the Power Control register to 1 Note Step 2 and step 3 can be executed at same time Also step 7 and step 8 can be executed at same time CHANGE BUS WIDTH SEQUENCE Disable Card Interrupt in Host 1 START SD Memory Only Card 2 Mask Card Interrupt in Card 3 Change Bit Mode in Card 4 Change Bit Mode for Host 5 SD Memory Only Card ...

Page 884: ...t Status Enable register to 1 TIMEOUT SETTING FOR DAT LINE Calculate a Divisor for detecting Timeout 1 START Set Timeout Detection Timer 2 END Figure 27 8 Timeout Setting Sequence In order to detect timeout errors on DAT line the Host Driver will execute the following two steps before any SD transaction 1 Calculate a divisor to detect timeout errors by reading Timeout Clock Frequency and Timeout C...

Page 885: ...s specification the first and the second case s transactions are classified as Transaction Control without Data Transfer using DAT Line the third case s transaction is classified as Transaction Control with Data Transfer using DAT Line Please refer to the specifications below for the detailed specifications on the SD Command itself SD Memory Card Specification Part 1 PHYSICAL LAYER SPECIFICATION V...

Page 886: ...MMAND ISSUE SEQUENCE Figure 27 9 Timeout Setting Sequence Take the following steps for Timeout Setting 1 Check Command Inhibit CMD in the Present State register Repeat this step until Command Inhibit CMD is 0 That is when Command Inhibit CMD is 1 the Host Driver will not issue a SD Command 2 If the Host Driver issues a SD Command with busy signal go to step 3 If without busy signal go to step 5 3 ...

Page 887: ...nd Complete in the Normal Interrupt Status register to clear this bit 3 Read the Response register and get necessary information in accordance with the issued command 4 Judge whether the command uses the Transfer Complete Interrupt or not If it uses Transfer Complete proceed with step 5 If not go to step 7 5 Wait for the Transfer Complete Interrupt If the Transfer Complete Interrupt has occurred g...

Page 888: ...rmation herein are subject to change without notice START Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int Wait for Transfer Complete Int Clr Transfer Complete Status Transfer Complete Int occur Check Response Data no No error Return Status No Error Return Status Response Contents Error Error END 1 2 3 4 5 6 7...

Page 889: ...the sequences for SD transfers are basically classified according to how the number of blocks is specified The three kinds of classification are as follows 1 Single Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is always one 2 Multiple Block Transfer The number of blocks is specified to the Host Controller before the tran...

Page 890: ...nd Complete Status Command Complete Int occur Get Response Data Write or Read 6 7 8 Wait for Buffer Write Ready Int Buffer Write Ready Int occur Clr Buffer Write Ready Status Set Block Data More Blocks write read 9 10 W 11 W 12 W 13 W yes no Wait for Buffer Read Ready Int Buffer Read Ready Int occur Clr Buffer Read Ready Status Get Block Data 11 R 12 R 10 R More Blocks yes 13 R no Single Multi Inf...

Page 891: ...ponse register and get necessary information in accordance with the issued command 9 If this sequence is for write to a card proceed to step 10 W In case of read from a card go to step 10 R 10 W Wait for Buffer Write Ready Interrupt 11 W Write 1 to the Buffer Write Ready in the Normal Interrupt Status register for clearing this bit 12 W Write block data in according to the number of bytes specifie...

Page 892: ...r Complete Int occur Clr DMA Status Interrupt Set System Address Reg 10 11 12 13 Clr Transfer Complete status Clr DMA Interrupt status 14 END Figure 27 12 Transaction Control with Data Transfer Using DAT Line Sequence Using DMA 1 Set the system address for DMA in the System Address register 2 Set the value corresponding to the executed data byte length of one block in the Block Size register 3 Set...

Page 893: ...bit 9 Read Response register and get necessary information in accordance with the issued command 10 Wait for the Transfer Complete Interrupt and DMA Interrupt 11 If Transfer Complete is set 1 go to Step 14 else if DMA Interrupt is set to 1 proceed to Step 12 Transfer Complete is higher priority than DMA Interrupt 12 Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this...

Page 894: ...ta transfer stopped by using Stop At Block Gap Request in the Block Gap Control register DMA TRANSACTION DMA allows a peripheral to read and write memory without intervention from the CPU Only one SD command transaction can be executed by DMA Host Controllers that support DMA shall support both single block and multiple block transfers The System Address register points to the first data address a...

Page 895: ...these bits are ignored RW or R W Read write register Register bits are read write and may be either set or cleared by software to the desired state RW1C Read only status Write 1 to clear status Register bits indicate status when read a set bit indicating a status event may be cleared by writing a 1 Writing a 0 to RW1C bits has no effect RWAC Read Write automatic clear register The Host Driver requ...

Page 896: ...int to the system address of the next contiguous data position It can be accessed only if no transaction is executing i e after a transaction has stopped Read operations during transfers may return an invalid value The Host Driver shall initialize this register before starting a DMA transaction After DMA has stopped the next system address of the next contiguous data position can be read from this...

Page 897: ...Host Controller generates the DMA Interrupt to request the Host Driver to update the System Address register In case of this register is set to 0 buffer size 4K bytes lower 12 bit of byte address points data in the contiguous buffer and the upper 20 bit points the location of the buffer in the system memory The DMA transfer stops when the Host Controller detects carry out of the address from bit 1...

Page 898: ...oduct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 0003h 3 Bytes 0002h 2 Bytes 0001h 1 Byte 0000h No data transfer ...

Page 899: ...ock Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers The Host Driver shall set this register to a value between 1 and the maximum block count The Host Controller decrements the block count after each block transfer and stops when the count reaches zero Setting the block count to 0 results in no data blocks being transferred This register must be...

Page 900: ...otice ARGUMENT REGISTER This register contains the SD Command Argument Register Address R W Description Reset Value ARGUMENT0 0x7C200008 R W Command Argument Register Channel 0 0x0 ARGUMENT1 0x7C300008 R W Command Argument Register Channel 1 0x0 ARGUMENT2 0x7C400008 R W Command Argument Register Channel 2 0x0 Name Bit Description Initial Value ARG 31 0 Command Argument The SD Command Argument is s...

Page 901: ...l 1 0x0 TRNMOD2 0x7C40000C R W Transfer Mode Setting Register Channel 2 0x0 Name Bit Description Initial Value 15 10 Reserved 0 9 8 Command Completion Signal Control 00 No CCS Operation Normal operation Not CE ATA mode 01 Read or Write data transfer CCS enable Only CE ATA mode 10 Without data transfer CCS enable Only CE ATA mode 11 Abort Completion Signal ACS generation Only CE ATA mode 0 7 6 Rese...

Page 902: ... 0 Disable 0 0 DMA Enable This bit enables DMA functionality DMA can be enabled only if it is supported as indicated in the DMA Support in the Capabilities register If DMA is not supported this bit is meaningless and shall always read 0 If this bit is set to 1 a DMA operation shall begin when the Host Driver writes to the upper byte of Command register 00Fh 1 Enable 0 Disable 0 Table below shows t...

Page 903: ...ommand Type There are three types of special commands Suspend Resume and Abort These bits shall be set to 00b for all other commands Suspend Command If the Suspend command succeeds the Host Controller shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line The Host Controller shall de assert Read Wait for read transactions and stop checki...

Page 904: ...ommand CRC Check Enable If this bit is set to 1 the Host Controller shall check the CRC field in the response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the CRC field is not checked The number of bits checked by the CRC field value changes according to the length of the response 1 Enable 0 Disable 2 Reserved 1 0 Response Type Select 00 No Response 01 Resp...

Page 905: ...Description Reset Value RSPREG0_2 0x7C400010 ROC Response Register 0 Channel 2 0x0 RSPREG1_2 0x7C400014 ROC Response Register 1 Channel 2 0x0 RSPREG2_2 0x7C400018 ROC Response Register 2 Channel 2 0x0 RSPREG3_2 0x7C40001C ROC Response Register 3 Channel 2 0x0 Name Bit Description Initial Value 127 0 Command Response The Table below describes the mapping of command responses from the SD Bus to this...

Page 906: ... in the Response register This enables the Host Driver to efficiently read 32 bits of response data in one read cycle on a 32 bit bus system Parts of the response the Index field and the CRC are checked by the Host Controller as specified by the Command Index Check Enable and the Command CRC Check Enable bits in the Command register and generate an error interrupt if an error is detected The bit r...

Page 907: ...BUFFER DATA PORT REGISTER 32 bit data port register to access internal buffer Register Address R W Description Reset Value BDATA0 0x7C200020 R W Buffer Data Register Channel 0 0x0 BDATA1 0x7C300020 R W Buffer Data Register Channel 1 0x0 BDATA2 0x7C400020 R W Buffer Data Register Channel 2 0x0 Name Bit Description Initial Value Buffer Data The Host Controller buffer can be accessed through this 32 ...

Page 908: ...usy signal level from DAT 0 D23 DAT 3 D22 DAT 2 D21 DAT 1 D20 DAT 0 Note DAT port is mapped to SD0_DAT pin Line State 19 Write Protect Switch Pin Level RO The Write Protect Switch is supported for memory and combo cards This bit reflects the SDWP pin 1 Write enabled SDWP 1 0 Write protected SDWP 0 Note SDWP port is mapped to SD0_nWP pin In S3C6400 case SD _nWP port is fixed to High 1 18 Card Detec...

Page 909: ...ual to 4 word this status bit is set to HIGH When others clears automatically Write Tx mode when this bit is HIGH more than or equal to 4 word can be written by CPU side Read Rx mode when this bit is HIGH more than or equal to 4 word can be read by CPU side 0 DIFF1 W 12 FIFO Pointer Difference 1 Word ROC When the difference of the address pointer between AHB side and SD side is more than or equal ...

Page 910: ...is 0 it means no valid write data exists in the Host Controller This bit is set in either of the following cases 1 After the end bit of the write command 2 When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer This bit is cleared in either of the following cases 1 After getting the CRC status of the last data block as specified by the transfer count Sin...

Page 911: ...ister to continue a write transfer This bit can be cleared in either of the following cases 1 When the SD card releases write busy of the last data block the Host Controller will detect if output is not busy If SD card does not drive busy signal for 8 SD Clocks the Host Controller will consider the card drive Not Busy 2 When the SD card releases write busy prior to waiting for write transfer as a ...

Page 912: ...d conflict error Refer to Command CRC Error or because of Command Not Issued By Auto CMD12 Error this bit shall remain 1 and the Command Complete is not set Status issuing Auto CMD12 is not read from this bit 1 Cannot issue command 0 Can issue command using only CMD line Note Buffer Write Enable in Present register must not be asserted for DMA transfers since it generates Buffer Write Ready interr...

Page 913: ...ion data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 27 3 Timing of Command Inhibit DAT and Command Inhibit CMD with data transfer Figure 27 4 Timing of Command Inhibit DAT for the case of response with busy Figure 27 5 Timing of Command Inhibit CMD for the case of no response command ...

Page 914: ...er Width It is for MMC 8bit card 1 8 bit operation 0 the bit width is designated by the bit 1 Data Transfer Width 0 4 3 Reserved 0 2 High Speed Enable This bit is optional Before setting this bit the Host Driver shall check the High Speed Support in the Capabilities register If this bit is set to 0 default the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock up to...

Page 915: ...nt State Register Channel 2 0x0 Name Bit Description Initial Value 7 4 Reserved 3 1 SD Bus Voltage Select By setting these bits the Host Driver selects the voltage level for the SD card Before setting this register the Host Driver will check the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System will not supply SD Bus voltage 111b 3 3V Typ 110b ...

Page 916: ... the DAT 2 line Otherwise the Host Controller has to stop the SD Clock to hold read data which restricts commands generation When the Host Driver detects an SD card insertion it will set this bit according to the CCCR of the SDIO card If the card does not support read wait this bit will never be set to 1 otherwise DAT line conflict may occur If this bit is set to 0 Suspend Resume cannot be support...

Page 917: ...State register Regarding detailed control of bits D01 and D00 RW 1 Stop 0 Transfer There are three cases to restart the transfer after stop at the block gap Which case is appropriate depends on whether the Host Controller issues a Suspend command or the SD card accepts the Suspend command Cases are as follows 1 If the Host Driver does not issue a Suspend command the Continue Request can be used to...

Page 918: ...akeup Control Register Channel 0 0x0 WAKCON1 0x7C30002B R W Wakeup Control Register Channel 1 0x0 WAKCON2 0x7C40002B R W Wakeup Control Register Channel 2 0x0 Name Bit Description Initial Value 7 3 Reserved 0 2 Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register FN_WUS Wake Up Support in CIS does not affect this bi...

Page 919: ...se clock divided by 16 04h base clock divided by 8 02h base clock divided by 4 01h base clock divided by 2 00h base clock 10MHz 63MHz Setting 00h specifies the highest frequency of the SD Clock Setting multiple bits the most significant bit is used as the divisor But multiple bits must not be set The two default divider values can be calculated by the frequency that is defined by the Base Clock Fr...

Page 920: ...DCLK 0 If the Card Inserted in the Present State register is cleared this bit will be cleared RW 1 Enable 0 Disable 0 1 Internal Clock Stable This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1 The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1 Note This is useful when using PLL for a clock oscillator that requires ...

Page 921: ...timeout generation Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value When setting this register prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable in the Error Interrupt tatus Enable register 1111b Reserved 1110b TMCLK x 227 1101b TMCLK x 226 0001b TMCLK x 214 0000b TMCLK x 213 0 SOFTWARE RESET REGISTER A reset pulse is ...

Page 922: ...set For CMD Line Only part of command circuit is reset RWAC The following registers and bits are cleared by this bit Present State register Command Inhibit CMD Normal Interrupt Status register Command Complete 1 Reset 0 Work 0 0 Software Reset For All This reset affects the entire Host Controller except for the card detection circuit Register bits of type ROC RW RW1C RWAC are cleared to 0 During i...

Page 923: ...r Channel 1 0x0 NORINTSTS2 0x7C400030 ROC RW1C Normal Interrupt Status Register Channel 2 0x0 Name Bit Description Initial Value 15 Error Interrupt If any of the bits in the Error Interrupt Status register are set then this bit is set Therefore the Host Driver can efficiently test for an error by checking this bit first This bit is read only ROC 0 No Error 1 Error 0 StaFIA3 14 FIFO SD Address Poin...

Page 924: ...t statuses latched in the Host Controller and to stop driving the interrupt signal to the Host System After completion of the card interrupt service It must reset interrupt factors in the SD card and the interrupt signal may not be asserted set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again ROC RW1C 1 Generate Card Interrupt 0 No Card Interrupt 0 7 Card Removal Thi...

Page 925: ...to use this function 2 Case of Write Transaction This bit is set at the falling edge of Write Transfer Active Status After getting CRC status at SD Bus timing 1 Transaction stopped at block gap 0 No Block Gap Event 0 1 Transfer Complete This bit is set when a read write transfer is completed 1 In the case of a Read Transaction This bit is set at the falling edge of Read Transfer Active Status Ther...

Page 926: ...response Except Auto CMD12 Refer to Command Inhibit CMD in the Present State register The table below shows that Command Timeout Error has higher priority than Command Complete If both bits are set to 1 it can be considered that the response was not received correctly RW1C Command Complete Command Timeout Error Meaning of the status 0 0 Interrupted by another factor Don t care 1 Response not recei...

Page 927: ...r Interrupt Status Register Channel 2 0x0 Name Bit Description Initial Value 15 9 Reserved 0 8 Auto CMD12 Error Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1 This bit is set to 1 not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error 1 Error 0 No Error 0 7 Current Limit Error N...

Page 928: ...CMD line to 1 level but detects 0 levels on the CMD line at the next SDCLK edge then the Host Controller will abort the command Stop driving CMD line and set this bit to 1 The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict 1 CRC Error generated 0 No Error 0 0 Command Timeout Error Occurs only if no response is returned within 64 SDCLK cycles from the end bit of the c...

Page 929: ...0 EnStaFIA3 14 FIFO SD Address Pointer Interrupt 3 Status Enable 1 Enabled 0 Masked 0 EnStaFIA2 13 FIFO SD Address Pointer Interrupt 2 Status Enable 1 Enabled 0 Masked 0 EnStaFIA1 12 FIFO SD Address Pointer Interrupt 1 Status Enable 1 Enabled 0 Masked 0 EnStaFIA0 11 FIFO SD Address Pointer Interrupt 0 Status Enable 1 Enabled 0 Masked 0 EnStaRWait 10 Read Wait interrupt status enable 1 Enabled 0 Ma...

Page 930: ...ilable Specifications and information herein are subject to change without notice 0 Masked 5 Buffer Read Ready Status Enable 1 Enabled 0 Masked 0 4 Buffer Write Ready Status Enable 1 Enabled 0 Masked 0 3 DMA Interrupt Status Enable 1 Enabled 0 Masked 0 2 Block Gap Event Status Enable 1 Enabled 0 Masked 0 1 Transfer Complete Status Enable 1 Enabled 0 Masked 0 0 Command Complete Status Enable 1 Enab...

Page 931: ...or Interrupt Status Enable Register Channel 1 0x0 ERRINTSTSEN2 0x7C400036 R W Error Interrupt Status Enable Register Channel 2 0x0 Name Bit Description Initial Value 15 9 Reserved 0 8 Auto CMD12 Error Status Enable 1 Enabled 0 Masked 0 7 Current Limit Error Status Enable This function is not implemented in this version 1 Enabled 0 Masked 0 6 Data End Bit Error Status Enable 1 Enabled 0 Masked 0 5 ...

Page 932: ...ster Channel 1 0x0 NORINTSIGEN2 0x7C400038 R W Normal Interrupt Signal Enable Register Channel 2 0x0 Name Bit Description Initial Value 15 Fixed to 0 The Host Driver shall control error interrupts using the Error Interrupt Signal Enable register 0 EnSigFIA3 14 FIFO SD Address Pointer Interrupt 3 Signal Enable 1 Enabled 0 Masked 0 EnSigFIA2 13 FIFO SD Address Pointer Interrupt 2 Signal Enable 1 Ena...

Page 933: ... available Specifications and information herein are subject to change without notice 5 Buffer Read Ready Signal Enable 1 Enabled 0 Masked 0 4 Buffer Write Ready Signal Enable 1 Enabled 0 Masked 0 3 DMA Interrupt Signal Enable 1 Enabled 0 Masked 0 2 Block Gap Event Signal Enable 1 Enabled 0 Masked 0 1 Transfer Complete Signal Enable 1 Enabled 0 Masked 0 0 Command Complete Signal Enable 1 Enabled 0...

Page 934: ...ster Channel 0 0x0 ERRINTSIGEN1 0x7C30003A R W Error Interrupt Signal Enable Register Channel 1 0x0 ERRINTSIGEN2 0x7C40003A R W Error Interrupt Signal Enable Register Channel 2 0x0 Name Bit Description Initial Value 15 9 Reserved 0 8 Auto CMD12 Error Signal Enable 1 Enabled 0 Masked 0 7 Current Limit Error Signal Enable This function is not implemented in this version 1 Enabled 0 Masked 0 6 Data E...

Page 935: ...1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error D04 D01 in this register 1 Not Issued 0 No error 0 6 5 Reserved 0 4 Auto CMD12 Index Error Occurs if the Command Index error occurs in response to a command 1 Error 0 No Error 0 3 Auto CMD12 End Bit Error Occurs when detecting that the end bit of command response is 0 1 End Bit Error Generated 0 No Error 0 2 Auto CMD12 CRC Error Occurs ...

Page 936: ...ller is going to issue Auto CMD12 Set D00 to 1 if Auto CMD12 cannot be issued due to an error in the previous command Set D00 to 0 if Auto CMD12 is issued 2 At the end bit of an Auto CMD12 response Check received responses by checking the error bits D01 D02 D03 and D04 Set to 1 if error is detected Set to 0 if error is not detected 3 Before reading the Auto CMD12 Error Status bit D07 Set D07 to 1 ...

Page 937: ...ed 0 1 8V Not Supported 1 25 Voltage Support 3 0V HWInit 1 3 0V Supported 0 3 0V Not Supported 0 24 Voltage Support 3 3V HWInit 1 3 3V Supported 0 3 3V Not Supported 1 23 Suspend Resume Support HWInit This bit indicates whether the Host Controller supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the Host Driver does not issue either Susp...

Page 938: ...ue Refer to the SDCLK Frequency Select in the Clock Control register and it does not exceed upper limit of the SD Clock frequency The supported clock range is 10MHz to 63MHz If these bits are all 0 the Host System has to get information via another method Not 0 1MHz to 63MHz 000000b Get information via another method 0 7 Timeout Clock Unit HWInit This bit shows the unit of base clock frequency use...

Page 939: ...od all Maximum Current Capabilities register will be 0 Register Address R W Description Reset Value MAXCURR0 0x7C200048 HWInit Maximum Current Capabilities Register Channel 0 0x0 MAXCURR1 0x7C300048 HWInit Maximum Current Capabilities Register Channel 1 0x0 MAXCURR2 0x7C400048 HWInit Maximum Current Capabilities Register Channel 2 0x0 Name Bit Description Initial Value 31 24 Reserved 23 16 Maximum...

Page 940: ... Condition Selection 0 Card Removed condition is Not Card Insert State When the transition from Card Inserted state to Debouncing state in Figure 27 2 1 Card Removed state is Card Out State When the transition from Debouncing state to No Card state in Figure 27 2 0 FltClkSel 27 24 Filter Clock iFLTCLK Selection Filter Clock period 2 FltClkSel 5 x iSDCLK period 0000 25 x iSDCLK 0001 26 x iSDCLK 111...

Page 941: ...e Host Device Manual 0 DisBufRD 6 Buffer Read Disable 0 Normal mode user can read buffer FIFO data using 0x20 register 1 User cannot read buffer FIFO data using 0x20 register In this case the buffer memory only can be read through memory area Debug purpose 0 SelBaseClk 5 4 Base Clock Source Select 00 or 01 HCLK 10 EPLL out Clock from SYSCON 11 External Clock source XTI or XEXTCLK 00 PwrSync 3 SD O...

Page 942: ...egister 3 FIFO 512Byte Buffer memory word address unit Initial value 0x7F generates at 512 byte 128 word position 0x7F FCSel2 23 Feedback Clock Select 2 Reference Note 1 0x0 FIA2 22 16 FIFO Interrupt Address register 2 FIFO 512Byte Buffer memory word address unit Initial value 0x5F generates at 384 byte 96 word position 0x5F FCSel1 15 Feedback Clock Select 1 Reference Note 2 0x0 FIA1 14 8 FIFO Int...

Page 943: ...Value HCVER0 0x7C2000FE HWInit Host Controller Version Register Channel 0 0x1300 HCVER1 0x7C3000FE HWInit Host Controller Version Register Channel 1 0x1300 HCVER2 0x7C4000FE HWInit Host Controller Version Register Channel 2 0x1300 Name Bit Description Initial Value 15 8 Vendor Version Number This status is reserved for the vendor version number The Host Driver must not use this status 0x3 SDMMC3 0...

Page 944: ...ROPROCESSOR 27 68 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice ...

Page 945: ...OR MIPI HSI 28 1 28 MIPI HSI INTERFACE CONTROLLER OVERVIEW MIPI HSI interface is a kind of high speed synchronous serial interface Figure 28 1 MIPI HSI signal definition Block Diagram Figure 28 2 MIPI HSI transmitting example Block Diagram ...

Page 946: ...dule z Status register 9 FIFO status fifo full fifo empty fifo write point fifo read point 9 MIPI status internal status current status next status z Configuration register 9 Operation mode select stream mode or frame mode 9 Fixed channel ID mode 9 Number of channel 9 Generated Error clear 9 TxHOLD state timer enable 9 TxIDLE state timer enable 9 TxREQ state timer enable z Interrupt source registe...

Page 947: ...atus next status z Configuration register 0 9 Operation mode select stream mode or frame mode 9 Fixed channel ID mode 9 Number of channel 9 Generated Error clear 9 RxACK state timer enable 9 Rx state timer z Configuration register 1 9 Rx FIFO clear 9 Rx FIFO timer enable z Interrupt source register 9 Rx FIFO full 9 Rx FIFO timeout 9 Data Receiving Done 9 Break frame received 9 Break frame receivin...

Page 948: ...rein are subject to change without notice BLOCK DIAGRAM TOP LEVEL BLOCK DIAGRAM Basic architectures of the Rx module part the Tx module part are similar Figure 28 3 MIPI HSI interface controller Tx module Top Block Diagram APB IF module MIPI HSI Rx FSM MIPI HSI Serial To Parallel module APB BUS MRx_Data MRx_Flag MRx_ Wake MRx_ Ready Ch ID 3bit Data FIFO 32bit width DMAreq Figure 28 4 MIPI HSI inte...

Page 949: ...and information herein are subject to change without notice Tx module part parallel to serial block ChannelID F D PRE_D FLAG DATA MSB LSB Shift data Tx F I F O Data Flag PCLK Data DATA 31 0 DATA 31 0 DATA 31 0 DATA 31 0 Figure 28 5 Parallel to Serial block Tx module Part Rx module part serial to parallel block DATA 31 0 Channel ID F DATA 31 0 DATA 31 0 DATA 31 0 Ch ID REG Figure 28 6 Serial to Par...

Page 950: ...ss PWRITE 1 I APB bus write PRDATA 32 O APB bus read data PWDATA 32 I APB bus write data PSEL 1 I APB module select PENABLE 1 I APB module enable Interrupt DMA Request Signals INT_MIPI_TX 1 O Interrupt request DMAREQ_TX 1 O DMA request DMAREQ_CLR 1 I DMA request clearing signal from DMAC MIPI HSI interface Signals Tx TX_DATA 1 O MIPI HSI data line TX_FLAG 1 O MIPI HSI flag line TX_WAKE 1 O MIPI HS...

Page 951: ...rupt DMA Request Signals INT_MIPI_RX 1 O Interrupt request DMAREQ_RX 1 O DMA request DMAREQ_CLR 1 I DMA request clearing signal from DMAC SYSCON wakeup Signals Rx MIPI_WAKEUP 1 O Wake up signal for SYSCON wakeup_enn 1 O Wake up signal enable for FPC MIPI HSI interface Signals Rx RX_DATA 1 I MIPI HSI data line RX_FLAG 1 I MIPI HSI flag line RX_WAKE 1 I MIPI HSI wake up line from the other side Tx R...

Page 952: ...ribe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice TIMING DIAGRAM WAVEFORM Figure 28 7 Waveform Block Diagram SIGNAL TIMINGS Table 28 3 Signal timings ...

Page 953: ...ample of Burst channel ID mode Block Diagram In the Single channel ID mode channel ID is attached in front of each data to send In the Burst channel ID mode channel ID is attached only in front of the first data frame which is sent after the IDLE state and then only 32bit data are sent until going into IDLE mode again The variable channel mode has a wider bandwidth in transferring a large data com...

Page 954: ...t to change without notice FRAME MODE Normal mode Figure 28 10 Example of Frame mode normal mode Block Diagram Break frame Figure 28 11 Break frame Block Diagram The flag line continues to toggle until the transfer is finished because the break frame is transferring more than 36 0 s Tx module does not monitor the ready signal while it transfers the break frame which is different than the normal mo...

Page 955: ...chine IDLE INT_fifo_empty active TxWAKE inactive TxREQ TxWAKE active Tx If br_frame clr_brframe active TxIDLE Waiting ready for next trans Data out include C ID Tx module sleeping Wake up Rx Waiting ready for new trans fifo_empty Ready Err_clr state_timeout fifo_empty tx_end fifo_empty Tx_ready fifo_empty TxHOLD Holding trans Shift_cnt data_2ndbit Ready Ready ERR Error generated state_timeout stat...

Page 956: ...xRST RxReady inactive Reset shift register Frame_mode frame_bit 0 shift_cnt expected_dat a_cnt state_timeout Figure 28 13 FSM of Rx module Part Rx state is operated by a timer which is set as the clock frequency input through MIPI HSI interface the operation mode and the number of channel IDs For example let s assume that the clock frequency of MIPI is 100MHz the number of channel IDs is 3 the ope...

Page 957: ...G 0x7E006014 Tx controller software reset 0x00000000 CHID_REG 0x7E006018 MIPI HSI Tx controller channel ID register 0x00000000 DATA_REG 0x7E00601C MIPI HSI Tx controller data register FIFO input 0x00000000 Table 28 4 Tx Controller Register Map Table MIPI HSI Rx Controller Register Map Table Register Address Description Reset Value STATUS_REG 0x7E007000 MIPI HSI Rx controller status register 0x0001...

Page 958: ...eserved Reserved bit R 0x0 30 28 next_state Next state R 0x0 27 reserved Reserved bit R 0x0 26 24 current state Current state R 0x0 23 18 reserved Reserved bits R 0x00 17 FIFO_full TxFIFO full 0 FIFO not full 1 FIFO full R 0x0 16 FIFO_empty TxFIFO empty 0 FIFO not empty 1 FIFO empty R 0x1 15 13 reserved Reserved bits R 0x0 12 8 tx_rd_point TxFIFO read point R 0x00 7 5 reserved Reserved bits R 0x0 ...

Page 959: ... TxIDLE time_en TxIDLE state timer enabler 0 disable 1 enable R W 0x0 5 TxREQ time_en TxREQ state timer enabler 0 disable 1 enable R W 0x0 4 Err_clr Generated Error clear 0 stay 1 clear R W 0x0 3 2 Width of CHID Width of channel ID R W 0x0 1 Burst_mode Fixed channel ID mode 0 Burst ch ID mode 1 Single ch ID mode R W 0x1 0 Frame_mode Frame mode 0 Stream mode 1 Frame mode R W 0x0 Table 28 7 CONFIG_R...

Page 960: ... is interrupt mask DMA request enabler register Address BASEADDR 0x10 0x7E00_6010 Bits Name Description R W Reset Value 31 DMA_req_en DMA request signal enable 0 enable 1 disable R W 0x1 30 5 Reserved Reserved bits R 0x0000000 4 TxH_timeout_ms k TxHOLD state timeout interrupt mask 0 unmask 1 mask R W 0x1 3 TxI_timeout_msk TxIDLE state timeout interrupt mask 0 unmask 1 mask R W 0x1 2 TxR_timeout_ms...

Page 961: ...ame_clr Stop break frame continuing transfer W 0x0 28 3 Reserved Reserved bits R 0x0000000 2 0 CHID Channel ID R W 0x0 Table 28 11 CHID_REG register description Note In order to send data with a constant channel ID the CHID_REG must be set only once and then the data to be transfered are pushed into the data fifo Then the same channel ID is attached to each of the data with sent through TxDATA If ...

Page 962: ...Specifications and information herein are subject to change without notice Address BASEADDR 0x1C Bits Name Description R W Reset Value 31 0 TxFIFO in TxFIFO data input for transmitting W 0x0 Table 28 12 DATA_REG register description Note If willing to transfer data is loaded on TxFIFO data which is located on FIFO is transferred to the other side s RX through MIPI HSI Tx controller until TxFIFO is...

Page 963: ...served Reserved bit R 0x0 30 28 Next_state Next state R 0x0 27 Reserved Reserved bit R 0x0 26 24 Curr_state Current state R 0x0 23 19 Reserved Reserved bits R 0x00 18 FIFO_timeout RxFIFO read timeout 0 in time 1 time out R 0x0 17 FIFO_full RxFIFO full 0 FIFO not full 1 FIFO full R 0x0 16 FIFO_empty RxFIFO empty 0 FIFO not empty 1 FIFO empty R 0x1 15 14 Reserved Reserved bits R 0x0 13 8 Rx_rd_point...

Page 964: ...ive when valid data in FIFO is 0x00 full 0x01 more than 4word 0x10 more than 8word 0x11 more than 16word R W 0x00 27 16 Rx_state time Rx state timer setting value R W 0xFFF 15 8 RxACK time RxACK state timer setting value R W 0xFF 7 Reserved Reserved bit R 0x0 6 RxACK time_en RxACK state timer enabler 0 disable 1 enable R W 0x0 5 Break_clr RxBREAK state clear bit 0 disable 1 enable R W 0x0 4 Err_cl...

Page 965: ... 15 CONFIG1_REG register description INTSRC_REG INTSRC_REG is interrupt source panding register Address BASEADDR 0x0C Bits Name Description R W Reset Value 31 8 Reserved Reserved bits R 0x000000 7 Break_done Received Break frame in Frame mode set 1 for clearing R W 0x0 6 Added_clock Added clock input set 1 for clearing R W 0x0 5 Missed_clock Missed clock input interrupt set 1 for clearing R W 0x0 ...

Page 966: ...its R 0x0000000 8 wakeup_enn MIPI wake up enabler 0 enable 1 disable R W 0x1 7 Break_done_ms k Break frame done interrupt mask 0 unmask 1 mask R W 0x1 6 Added_clock_ms k Added clock input interrupt mask 0 unmask 1 mask R W 0x1 5 Missed_clock_m sk Missed clock input interrupt mask 0 unmask 1 mask R W 0x1 4 RxACK_timeout_ msk RxACK state timeout interrupt mask 0 unmask 1 mask R W 0x1 3 Brframe_err_m...

Page 967: ...w_rst Software reset 0 set 1 reset R W 0x0 Table 28 18 SWRST_REG register description CHID_REG CHID_REG is channel ID RxFIFO output Address BASEADDR 0x18 Bits Name Description R W Reset Value 31 3 Reserved Reserved bits R 0x0000000 2 0 CURR_ID Current Channel ID R 0x0 Table 28 19 CHID_REG register description Note Channel ID is read once when Data is written in FIFO again after FIFO become empty b...

Page 968: ...l ID Put the Data at FIFO Change Channel ID FIFO empty Y N FIFO full Y Y Wait FIFO not full N N Wait FIFO empty Figure 28 14 Basic Tx module programming flow chart Figure 28 17 is programming guide for Tx module s operation First configuration register must be set up in order to transfer data Basically number of channel id frame stream mode and burst single mode must be set and the other values re...

Page 969: ...subject to change without notice Rx module programming guide flow chart Start Wait interrupt ISR RxDONE FIFO full FIFO time out Read channel ID reg Read Data FIFO Y N Y FIFO empty N Figure 28 15 Basic Rx module programming flow chart Figure 28 18 is the basis flow chart that shows how to handle transferred Data in Rx module If Data exists in FIFO first Read channel ID register and decide the Data ...

Page 970: ...smission and receiving respectively During SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface FEATURES The SPI supports the following features z Full duplex z 8 16 32 bit shift register for TX RX z 8 bit prescale logic z 3 clock source z 8bit 1...

Page 971: ...IFO to external device RX channel has the path from external device to RX FIFO CPU or DMA must write data on the register SPI_TX_DATA to write data in FIFO Data on the register are automatically moved to Tx FIFOs To read data from Rx FIFOs CPU or DMA must access the register SPI_RX_DATA and then data are automatically sent to the register SPI_RX_DATA OPERATION MODE HS_SPI has 2 modes master and sl...

Page 972: ... to be received just set the SFR Packet_Count_reg how many packets have to be received SPI stops generating SPICLK when the number of packets is the same as what you set It is mandatory to follow software or hardware reset before this function is reloaded Software reset can clear all registers except special function registers but hardware reset clears all registers NCS CONTROL nCS can be selected...

Page 973: ...describes four waveforms for SPICLK Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO MSB CPOL 1 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1...

Page 974: ...figuration register if necessary 6 Set Tx or Rx Channel on 7 Set nSSout low to start Tx or Rx operation A Set nSSout Bit to low then start TX data writing B If auto chip selection bit is set should not control nCS SPECIAL FUNCTION REGISTER Register Address R W Description Reset Value CH_CFG Ch0 0x7F00B000 R W SPI configuration register 0x0 CH_CFG Ch1 0x7F00C000 R W SPI configuration register 0x0 C...

Page 975: ...stem controller must be set to on 2 b0 ENCLK 8 R W Clock on off 0 disable 1 enable 1 b0 Prescaler Value 7 0 R W SPI clock out division rate SPI clock out Clock source 2 x Prescaler value 1 8 h0 Register Address R W Description Reset Value MODE_CFG Ch0 0x7F00B008 R W SPI FIFO control register 0x0 MODE_CFG Ch1 0x7F00C008 R W SPI FIFO control register 0x0 MODE_CFG Bit Description Initial State Ch_tra...

Page 976: ...n Reset Value Slave_slection_reg Ch0 0x7F00B00C R W Slave selection signal 0x1 Slave_slection_reg Ch1 0x7F00C00C R W Slave selection signal 0x1 Slave_slection_reg Bit Description Initial State nCS_time_count 9 4 R W nSSout inactive time nCS_time_count 3 2 x SPICLKout 6 b0 reserved 3 2 reserved Auto_n_Manual 1 R W Chip select toggle manual or auto selection 0 manual 1 Auto 1 b0 nSSout 0 R W Slave s...

Page 977: ...FifoRdy 0 R W Interrupt Enable for TxFifoRdy INT mode 0 Disable 1 Enable 1 b0 Register Address R W Description Reset Value SPI_STATUS Ch0 0x7F00B014 R SPI status register 0x0 SPI_STATUS Ch1 0x7F00C014 R SPI status register 0x0 SPI_STATUS Bit Description Initial State TX_done 21 R Indication of transfer done in Shift register 0 all case except blow case 1 when tx fifo and shift register are empty 1...

Page 978: ...TX_DATA Ch1 0x7F00C018 W SPI TX DATA register 0x0 SPI_TX_DATA Bit Description Initial State TX_DATA 31 0 W This field contains the data to be transmitted over the SPI channel 32 b0 Register Address R W Description Reset Value SPI_RX_DATA Ch0 0x7F00B01C R SPI RX DATA register 0x0 SPI_RX_DATA Ch1 0x7F00C01C R SPI RX DATA register 0x0 SPI_RX_DATA Bit Description Initial State RX_DATA 31 0 R This fiel...

Page 979: ...clr_reg Ch0 0x7F00B024 R W Pending clear register 0x0 Pending_clr_reg Ch1 0x7F00C024 R W Pending clear register 0x0 Status_Pending _clear_reg Bit Description Initial State TX_underrun_clr 4 R W TX underrun pending clear bit 0 non clear 1 clear 1 b0 TX_overrun_clr 3 R W TX overrun pending clear bit 0 non clear 1 clear 1 b0 RX_underrun_clr 2 R W RX underrun pending clear bit 0 non clear 1 clear 1 b0...

Page 980: ...eset Value SWAP_CFG Ch0 0x7F00B028 R W SWAP config register 0x0 SWAP_CFG Ch1 0x7F00C028 R W SWAP config register 0x0 SWAP_CFG Bit Description Initial State RX_Half word swap 7 R W 0 off 1 swap 1 b0 RX_Byte swap 6 R W 0 off 1 swap 1 b0 RX_Bit swap 5 R W 0 off 1 swap 1 b0 RX_SWAP_en 4 R W Swap enable 0 normal 1 swap 1 b0 TX_Half word swap 3 R W 0 off 1 swap 1 b0 TX_Byte swap 2 R W 0 off 1 swap 1 b0 ...

Page 981: ...hange without notice Register Address R W Description Reset Value FB_Clk_sel Ch0 0x7F00B02C R W Feedback clock selecting register 0x3 FB_Clk_sel Ch1 0x7F00C02C R W Feedback clock selecting register 0x3 SWAP_CFG Bit Description Initial State SPICLKout delay 2 R W 0 no additional delay 1 2 7ns delay base on typical 1 b0 FB_Clk_sel 1 0 R W 00 0nS additional delay 01 3nS additional delay 10 6nS additi...

Page 982: ... the S3C6400X uses Standard bus arbitration procedure To control multi master IIC bus operations values must be written to the following registers Multi master IIC bus control register IICCON Multi master IIC bus control status register IICSTAT Multi master IIC bus Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines must be bo...

Page 983: ...pment for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice PCLK Address Register SDA 4 bit Prescaler IIC Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register IICDS Data Bus SCL Figure 30 1 IIC Bus Block Diagram ...

Page 984: ...be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated A Stop condition will make the IIC bus ...

Page 985: ...Receiver SCL S 1 2 7 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte Complete Interrupt within Receiver Clock Line Held Low by receiver and or transmitter Figure 30 3 Data Transfer on the IIC Bus Block Diagram ACK SIGNAL TRANSMISSION To complete a one byte transfer operation the receiver must send an ACK bit to the transmitter The ACK pulse occurs at the ninth clock of the SCL line Eig...

Page 986: ...hich full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Data Output by Transmitter Data Output by Receiver SCL from Master Start Condition Clock Pulse for Acknowledgment Clock to Output 9 8 7 S 1 2 Figure 30 4 Acknowledge on the IIC Bus Block Diagram ...

Page 987: ...s High However when the masters simultaneously lower the SDA line each master evaluates whether the mastership is allocated itself or not For the purpose of evaluation each master must detect the address bits While each master generates the slave address it ealso detects the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master genera...

Page 988: ...ions 1 Write own slave address on IICADD register if needed 2 Set IICCON register a Enable interrupt b Define SCL period 3 Set IICSTAT to enable Serial Output Write slave address to IICDS Write 0xF0 M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write 0xD0 M T Stop to IICSTAT Write new data transmitted to IICDS Stop Clear pending bit to resume Th...

Page 989: ...e subject to change without notice Write slave address to IICDS Write 0xB0 M R Start to IICSTAT The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Write 0x90 M R Stop to IICSTAT Read a new data from IICDS Stop Clear pending bit to resume SDA is shifted to IICDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition takes ef...

Page 990: ... and information herein are subject to change without notice IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address Write data to IICDS The IIC address match interrupt is generated Clear pending bit to resume The data of the IICDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 30 7 Op...

Page 991: ...fications and information herein are subject to change without notice IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address Read data from IICDS The IIC address match interrupt is generated Clear pending bit to resume SDA is shifted to IICDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 30 8 Operatio...

Page 992: ... this bit is read as 1 the IICSCL is tied to L and the IIC is stopped To resume the operation clear this bit as 0 0 1 No interrupt pending when read 2 Clear pending condition Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write 0 Transmit clock value 4 3 0 IIC Bus transmit clock prescaler IIC Bus transmit clock frequency is determined by this 4 bit prescaler value ac...

Page 993: ...0 read Not busy when read write STOP signal generation 1 read Busy when read write START signal generation The data in IICDS will be transferred automatically just after the start signal 0 Serial output 4 IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx 0 Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration fail...

Page 994: ...ddress latched from the IIC bus When serial output enable 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 XXXXXXXX MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Register Address R W Description Reset Value IICDS 0x7F00400C R W IIC Bus transmit receive d...

Page 995: ...TER Register Address R W Description Reset Value IICLC 0x7F004010 R W IIC Bus multi master line control register 0x00 IICLC Bit Description Initial State Filter enable 2 IIC bus filter enable bit When SDA port is operating as input this bit should be High This filter can prevent from occurred error by a glitch during double of PCLK time 0 Filter disable 1 Filter enable 0 SDA output delay 1 0 IIC B...

Page 996: ...en the UART can operate at higher speed Each UART channel contains two 64 byte FIFOs for both reception and transmission The S3C6400 UART includes programmable baud rates infra red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator a transmitter a receiver and a control unit as shown in Figure 31 1 Th...

Page 997: ...or Control Unit Transmitter Receiver Peripheral BUS TXDn Clock Source RXDn Transmit FIFO Register FIFO mode Transmit Holding Register Non FIFO mode Receive FIFO Register FIFO mode Receive Holding Register Non FIFO mode only In FIFO mode all 64 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Transmit Shifter Transmit Buff...

Page 998: ...on word is transmitted completely After the break signal transmission it continuously transmits data into the Tx FIFO Tx holding register in the case of Non FIFO mode DATA RECEPTION Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detec...

Page 999: ... FIFO is ready to receive data Before the UART receives data nRTS has to be activated when its receive FIFO has a spare of more than 2 byte and has to be inactivated when its receive FIFO has a spare under 1 byte in AFC nRTS means that its own receive FIFO is ready to receive data RxD nRTS UART A TxD nCTS UART B TxD nCTS UART A RxD nRTS UART B Transmission case in UART A Reception case in UART A F...

Page 1000: ...FO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level Rx interrupt is generated Rx interrupt is generated if Receive mode in control register UCONn is selected as 1 Interrupt request or polling mode In the Non FIFO mode transferring the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode W...

Page 1001: ... any error interrupt because the character which was received with an error has not been read yet The error interrupt will occur when the character is read out Figure 31 3 shows the UART receiving the five characters including the two errors Type FIFO Mode Non FIFO Mode Rx interrupt Generated whenever receive data reaches the trigger level of receive FIFO Generated when the number of data in FIFO ...

Page 1002: ...ing UART Receiving 5 Characters with 2 Errors INFRA RED IR MODE The S3C6400 UART block supports infra red IR transmission and reception which can be selected by setting the Infra red mode bit in the UART line control register ULCONn Figure 31 4 illustrates how to implement the IR mode Time Sequence Flow Error Interrupt Note 0 When no character is read out 1 A B C D and E is received 2 After A is r...

Page 1003: ...the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value see the frame timing diagrams shown in Figure 31 6 and Figure 31 7 IrDA Tx Encoder 0 1 0 1 IrDA Rx Decoder TxD RxD TxD IRS RxD RE UART Block Figure 31 4 IrDA Function Block Diagram Start Bit St...

Page 1004: ...ta are not yet available Specifications and information herein are subject to change without notice 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width 3 16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 31 6 Infra Red Transmit Mode Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR Receive Frame 0 0 0 0 1 1 1 1 1 Figure 31 7 Infra Red Receive Mode Frame Timing Diagram ...

Page 1005: ...tion refer to the GPIO chapter of this manual for proper GPIO settings Name Type Source Destination Description XuRXD 0 Input Pad Receive data for UART0 XuTXD 0 Output Pad Transmit data for UART0 XuCTSn 0 Input Pad Clear to Send active low for UART0 XuRTSn 0 Output Pad Request to Send active low for UART0 XuRXD 1 Input Pad Receive data for UART1 XuTXD 1 Output Pad Transmit data for UART1 XuCTSn 1 ...

Page 1006: ... UDIVSLOT0 0x7F00502C R W UART channel 0 Dividing slot register 0x0000 UINTP0 0x7F005030 R W UART channel 0 Interrupt Pending Register 0x0 UINTSP0 0x7F005034 R W UART channel 0 Interrupt Source Pending Register 0x0 UINTM0 0x7F005038 R W UART channel 0 Interrupt Mask Register 0x0 ULCON1 0x7F005400 R W UART channel 1 line control register 0x00 UCON1 0x7F005404 R W UART channel 1 control register 0x0...

Page 1007: ...00582C R W UART channel 2 Dividing slot register 0x0000 INTP2 0x7F005830 R W UART channel 2 Interrupt Pending Register 0x0 UINTSP2 0x7F005834 R W UART channel 2 Interrupt Source Pending Register 0x0 UINTM2 0x7F005838 R W UART channel 2 Interrupt Mask Register 0x0 ULCON3 0x7F005C00 R W UART channel 3 line control register 0x00 UCON3 0x7F005C04 R W UART channel 3 control register 0x00 UFCON3 0x7F005...

Page 1008: ...ol register 0x00 ULCON2 0x7F005800 R W UART channel 2 line control register 0x00 ULCON3 0x7F005C00 R W UART channel 3 line control register 0x00 ULCONn Bit Description Initial State Reserved 7 0 Infra Red Mode 6 Determine whether or not to use the Infra Red mode 0 Normal mode operation 1 Infra Red Tx Rx mode 0 Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit ...

Page 1009: ... herein are subject to change without notice UART CONTROL REGISTER There are three UART control registers including UCON0 UCON1 UCON2 and UCON3 in the UART block Register Address R W Description Reset Value UCON0 0x7F005004 R W UART channel 0 control register 0x00 UCON1 0x7F005404 R W UART channel 1 control register 0x00 UCON2 0x7F005804 R W UART channel 2 control register 0x00 UCON3 0x7F005C04 R ...

Page 1010: ...O mode or reaches Rx FIFO Trigger Level in FIFO mode 0 Rx Time Out Enable 7 Enable Disable Rx time out interrupts when UART FIFO is enabled The interrupt is a receive interrupt 0 Disable 1 Enable 0 Rx Error Status Interrupt Enable 6 Enable the UART to generate an interrupt upon an exception such as a break frame error parity error or overrun error during a receive operation 0 Do not generate recei...

Page 1011: ...Buad Rate Configure Registers 2 S3C6400 is using a level triggered interrupt controller Therefore these bits must be set to 1 for every transfer 3 When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the you must check the FIFO status and read out the rest 4 EXT_UCLK0 c...

Page 1012: ...t check the FIFO status and read out the rest Register Address R W Description Reset Value UFCON0 0x7F005008 R W UART channel 0 FIFO control register 0x0 UFCON1 0x7F005408 R W UART channel 1 FIFO control register 0x0 UFCON2 0x7F005808 R W UART channel 2 FIFO control register 0x0 UFCON3 0x7F005C08 R W UART channel 3 FIFO control register 0x0 UFCONn Bit Description Initial State Tx FIFO Trigger Leve...

Page 1013: ... 1 Modem control register 0x0 Reserved 0x7F00580C Reserved Undef Reserved 0x7F005C0C Reserved Undef UMCONn Bit Description Initial State RTS trigger Level 7 5 When AFC bit is enabled these bits determine when to inactivate nRTS signal 000 When RX FIFO contains 63 bytes 001 When RX FIFO contains 56 bytes 010 When RX FIFO contains 48 bytes 011 When RX FIFO contains 40 bytes 100 When RX FIFO contains...

Page 1014: ...ransmitter empty 2 Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty 0 Not empty 1 Transmitter transmit buffer shifter register empty 1 Transmit buffer empty 1 Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mo...

Page 1015: ...RT channel 1 Rx error status register 0x0 UERSTAT2 0x7F005814 R UART channel 2 Rx error status register 0x0 UERSTAT3 0x7F005C14 R UART channel 3 Rx error status register 0x0 UERSTATn Bit Description Initial State Break Detect 3 Set to 1 automatically to indicate that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested 0 Frame Error 2 Set to 1 automatically wh...

Page 1016: ...ister 0x00 UFSTAT2 0x7F005818 R UART channel 2 FIFO status register 0x00 UFSTAT3 0x7F005C18 R UART channel 3 FIFO status register 0x00 There are three UART FIFO status registers including UFSTAT0 UFSTAT1 UFSTAT2 and UFSTAT3 in the UART block UFSTATn Bit Description Initial State Reserved 15 0 Tx FIFO Full 14 Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte T...

Page 1017: ... 31 8 nCTS and Delta CTS Timing Diagram Register Address R W Description Reset Value UMSTAT0 0x7F00501C R UART channel 0 Modem status register 0x0 UMSTAT1 0x7F00541C R UART channel 1 Modem status register 0x0 Reserved 0x7F00581C Reserved Undef Reserved 0x7F005C1C Reserved Undef UMSTAT0 Bit Description Initial State Reserved 7 5 reserved 000 Delta CTS 4 Indicate that the nCTS input to the S3C6400 h...

Page 1018: ...egister Address R W Description Reset Value URXH0 0x7F005024 R UART channel 0 receive buffer register 0x00 URXH1 0x7F005424 R UART channel 1 receive buffer register 0x00 URXH2 0x7F005824 R UART channel 2 receive buffer register 0x00 URXH3 0x7F005C24 R UART channel 3 receive buffer register 0x00 Note When an overrun error occurs the URXHn must be read If not the next received data will also make an...

Page 1019: ...g UDIVSLOT you can make more accurate baud rate For example if the baud rate is 115200 bps and PCLK EXT_UCLK0 or EXT_UCLK1 is 40 MHz UBRDIVn and UDIVSLOTn are DIV_VAL 40000000 115200 x 16 1 21 7 1 20 7 UBRDIVn 20 integer part of DIV_VAL num of 1 s in UDIVSLOTn 16 0 7 then num of 1 s in UDIVSLOTn 11 so UDIVSLOTn can be 16 b1110_1110_1110_1010 or 16 b0111_0111_0111_0101 etc We recommend selecting UD...

Page 1020: ...are not yet available Specifications and information herein are subject to change without notice BAUD RATE ERROR TOLERANCE UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK tUPCLK Real UART Clock tEXTUARTCLK 1Frame baud rate tEXTUARTCLK Ideal UART Clock UART error tUPCLK tEXTUARTCLK tEXTUARTCLK x 100 NOTE 1FRAME START BIT DATA BIT PARITY BIT STOP BIT ...

Page 1021: ...er 1 0x0000 UBRDIV2 0x7F005828 R W Baud rate divisior register 2 0x0000 UBRDIV3 0x7F005C28 R W Baud rate divisior register 3 0x0000 UBRDIV n Bit Description Initial State UBRDIV 15 0 Baud rate division value UBRDIVn 0 Register Address R W Description Reset Value UDIVSLOT0 0x7F00502C R W Baud rate divisior register 0 0x0000 UDIVSLOT1 0x7F00542C R W Baud rate divisior register 1 0x0000 UDIVSLOT2 0x7...

Page 1022: ...upt Mask Register Register Address R W Description Reset Value UINTSP0 0x7F005034 R W Interrupt Source Pending Register 0 0x0 UINTSP1 0x7F005434 R W Interrupt Source Pending Register 1 0x0 UINTSP2 0x7F005834 R W Interrupt Source Pending Register 2 0x0 UINTSP3 0x7F005C34 R W Interrupt Source Pending Register 3 0x0 Register Address R W Description Reset Value UINTP0 0x7F005030 R W Interrupt Pending ...

Page 1023: ...even in such a case the corresponding bit of UINTSPn register is set to 1 If the mask bit is 0 the interrupt request can be serviced from the corresponding interrupt source Note that even in such a case the corresponding bit of UINTSPn register is set to 1 Register Address R W Description Reset Value UINTM0 0x7F005038 R W Interrupt Mask Register for UART channel 0 0x0 UINTM1 0x7F005438 R W Interru...

Page 1024: ...r divided by 2 4 8 or 16 Alternatively the Timers select a clock source from an external pin Timers 0 and 1 can select the external clock TCLK0 Timers 2 3 and 4 can select the external clock TCLK1 Each timer has its own 32 bit down counter which is driven by the timer clock The down counter is initially loaded from the Timer Count Buffer register TCNTBn When the down counter reaches zero the timer...

Page 1025: ...32 1 Simple Example of PWM Cycle Block Diagram 1 Initialize the TCNTBn with 160 50 110 and the TCMPBn with 110 2 Start Timer by setting the start bit and manual update bit off The TCNTBn value of 160 is loaded into the down counter the output is driven low 3 When down counter counts down to the value in the TCMPBn register 110 the output is changed from low to high 4 When the down counter reaches ...

Page 1026: ...which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice The Figure 32 2 depicts the block diagram for PWM Timer Figure 32 2 PWMTIMER Block Diagram INTF _PWM COUNT _PWM CONTROL _PWM TIMER _REQ APB DMAAC K DMARE Q INT0 4 TOUT0 4 PCLK PCLK PCLK PCLK INTRGEN_SEL ...

Page 1027: ...ducts that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 32 3 PWMTIMER Clock Tree Diagram The Figure 32 3 and Figure 32 4 depict the clock generation scheme for individual PWM Channels ...

Page 1028: ...rmation herein are subject to change without notice Figure 32 4 PWMTIMER Detailed Clock Tree Diagram 8 Bit Clock Prescalar 1 1 2 4 8 1 2 4 8 TCLK0 PWM 1 Core PWM 2 Core PWM 3 Core PWM 4 Core PWM 5 Core M U X M U X M U X M U X M U X 8 Bit Clock Prescalar 2 16 16 1 2 4 8 1 2 4 8 16 16 1 2 4 8 1 2 4 8 16 16 1 2 4 8 1 2 4 8 16 16 1 2 4 8 1 2 4 8 16 16 TCLK0 TCLK1 TCLK1 TCLK1 Clock Divider Clock Divide...

Page 1029: ...rts DMA Transfers Optional Pulse or Level Interrupt Generation The PWM has two operation modes Auto Reload Mode Continuous PWM pulses are generated based on programmed duty cycle and polarity One Shot Pulse Mode Only one PWM pulse is generated based on programmed duty cycle and polarity To control the functionality of PWM 18 special function registers are provided The PWM is a programmable output ...

Page 1030: ...annel 5 has TCNTBn TCNTn TCMPBn and TCMPn TCNTBn and TCMPBn are loaded into TCNTn and TCMPn when the timer reaches 0 When TCNTn reaches 0 the interrupt request will occur if the interrupt is enabled TCNTn and TCMPn are the names of the internal registers The TCNTn register can be read from the TCNTOn register AUTO RELOAD AND DOUBLE BUFFERING The Timers have a double buffering feature which can cha...

Page 1031: ...e The auto reload is the operation which copies the TCNTBn into TCNTn when TCNTn reaches 0 The value written into TCNTBn is loaded to TCNTn only when the TCNTn reaches to 0 and auto reload is enabled If the TCNTn is 0 and the auto reload bit is 0 the TCNTn does not operate further Write TCNTBn 100 Write TCNTBn 200 Start auto_reload TCNTBn 150 150 200 100 100 If TCNT is 0 interrupt signal is genera...

Page 1032: ...rt Timer by setting the start bit and manual update bit off 3 When TCNTn has the same value with TCMPn the logic level of TOUTn is changed from low to high 4 When TCNTn reaches to 0 TCNTn is reloaded automatically with TCNTBn At the same time the interrupt request is generated 5 In the ISR interrupt service routine the TCNTBn and TCMPBn is set as 80 20 60 and 60 which is used for next duration 6 W...

Page 1033: ...alue into TCNTBn and TCMPBn 2 Set the manual update bit of the corresponding timer Recommended setting the inverter on off bit whether using inverter or not 3 Set the start bit of the corresponding timer to start the timer and clear only manual update bit PWM PULSE WIDTH MODULATION Write TCMPBn 60 Write TCMPBn 50 Write TCMPBn 40 Write TCMPBn 30 Write TCMPBn 30 Write TCMPBn next PWM 60 50 40 30 30 ...

Page 1034: ...ing the timer start stop bit to 0 If TCNTn TCMPn the ouput level is high If TCNTn TCMPn the output level is low 3 TOUTn can be inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level DEAD ZONE GENERATOR The deadzone is for the PWM control of power devices This feature is used to insert the time gap between a turn off of a switching device ...

Page 1035: ... as the source or destination but rather to have the timer simply control the timing of data movement between two other devices The timer will keep the DMA request signal DMA_REQ active high until the timer receives the ACK signal from the DMA unit When the timer receives the ACK signal it makes the request signal inactive Only one Timer at a time can be configured as the DMA request source The ti...

Page 1036: ...ation DMA mode DMA request INT0 INT1 INT2 INT3 INT4 0 0 0 No Select ON if enabled ON if enabled ON if enabled ON if enabled ON if enabled 0 0 1 Timer 0 ON if enabled ON if enabled ON if enabled ON if enabled ON if enabled 0 1 0 Timer 1 ON if enabled ON if enabled ON if enabled ON if enabled ON if enabled 0 1 1 Timer 2 ON if enabled ON if enabled ON if enabled ON if enabled ON if enabled 1 0 0 Time...

Page 1037: ...sed on programmed value in TINT_CSTAT register PROGRAMMER S MODEL OVERVIEW For controlling and observing the status of PWM following registers can be used 1 TCFG0 Clock Prescalar and Dead Zone Configurations 2 TCFG1 Clock Multiplexers and DMA Mode Select 3 TCON Timer Control Register 4 TCNTB0 Timer 0 Count Buffer Register 5 TCMPB0 Timer 0 Compare Buffer Register 6 TCNTO0 Timer 0 Count Observation ...

Page 1038: ...00 TCMPB0 0x7F006010 R W Timer 0 Compare Buffer Register 0x0000_0000 TCNTO0 0x7F006014 R Timer 0 Count Observation Register 0x0000_0000 TCNTB1 0x7F006018 R W Timer 1 Count Buffer Register 0x0000_0000 TCMPB1 0x7F00601c R W Timer 1 Compare Buffer Register 0x0000_0000 TCNTO1 0x7F006020 R Timer 1 Count Observation Register 0x0000_0000 TCNTB2 0x7F006024 R W Timer 2 Count Buffer Register 0x0000_0000 TCM...

Page 1039: ...imer 2 3 and 4 0x01 Prescaler 0 7 0 R W Prescaler 0 value for timer 0 1 0x01 TCFG1 TIMER CONFIGURATION REGISTER Register Offset R W Description Reset Value TCFG1 0x7F006004 R W Timer Configuration Register 1 that controls 5 MUX and DMA Mode Select Bit 0x0000_0000 TCFG1 Bit R W Description Initial State Reserved 31 24 R Reserved Bits 0x00 DMA mode 23 20 R W Select DMA Request Channel Select Bit 000...

Page 1040: ...Timer 4 0x0 Timer 3 Auto Reload on off 19 R W 0 One Shot 1 Interval Mode Auto Reload 0x0 Timer 3 Output Inverter on off 18 R W 0 Inverter Off 1 TOUT3 Inverter On 0x0 Timer 3 Manual Update 17 R W 0 No Operation 1 Update TCNTB3 TCMPB3 0x0 Timer 3 Start Stop 16 R W 0 Stop 1 Start Timer 3 0x0 Timer 2 Auto Reload on off 15 R W 0 One Shot 1 Interval Mode Auto Reload 0x0 Timer 2 Output Inverter on off 14...

Page 1041: ...IMER0 COMPARE REGISTER Register Offset R W Description Reset Value TCMPB0 0x7F006010 R W Timer 0 Compare Buffer Register 0x0000_0000 TCMPB0 Bit R W Description Initial State Timer 0 Compare Buffer 31 0 R W Timer 0 Compare Buffer Register 0x00000000 TCNTO0 TIMER0 OBSERVATION REGISTER Register Offset R W Description Reset Value TCNTO0 0x7F006014 R Timer 0 Count Observation Register 0x0000_0000 TCNTO...

Page 1042: ...1 TIMER1 OBSERVATION REGISTER Register Offset R W Description Reset Value TCNTO1 0x7F006020 R Timer 1 Count Observation Register 0x0000_0000 TCNTO1 Bit R W Description Initial State Timer 1 Count Observation 31 0 R Timer 1 Count Observation Register 0x00000000 TCNTB2 TIMER2 COUNTER REGISTER Register Offset R W Description Reset Value TCNTB2 0x7F006024 R W Timer 2 Count Buffer Register 0x0000_0000 ...

Page 1043: ...TCNTB3 TIMER3 COUNTER REGISTER Register Offset R W Description Reset Value TCNTB3 0x7F006030 R W Timer 3 Count Buffer Register 0x0000_0000 TCNTB3 Bit R W Description Initial State Timer 3 Count Buffer 31 0 R W Timer 3 Count Buffer Register 0x00000000 TCMPB3 TIMER3 COMPARE REGISTER Register Offset R W Description Reset Value TCMPB3 0x7F006034 R W Timer 3 Compare Buffer Register 0x0000_0000 TCMPB3 B...

Page 1044: ...ervation 31 0 R Timer 4 Count Observation Register 0x00000000 TINT_CSTAT INTERRUPT CONTROL AND STATUS REGISTER Register Offset R W Description Reset Value TINT_CSTAT 0x7F006044 R W Timer Interrupt Control and Status Register 0x0000_0000 TINT_CSTAT Bit R W Description Initial State Reserved 31 10 R Reserved Bits 0x00000 Timer 4 Interrupt Status 9 R W Timer 4 Interrupt Status Bit Clears by writing 1...

Page 1045: ...ization data and associated errata are not yet available Specifications and information herein are subject to change without notice Timer 2 interrupt Enable 2 R W Timer 2 Interrupt Enable 1 Enabled 0 Disabled 0x0 Timer 1 interrupt Enable 1 R W Timer 1 Interrupt Enable 1 Enabled 0 Disabled 0x0 Timer 0 interrupt Enable 0 R W Timer 0 Interrupt Enable 1 Enabled 0 Disabled 0x0 ...

Page 1046: ...ime Clock RTC unit can be operated by the backup battery when the system power is off The data include the time by second minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and can perform the alarm function FEATURES The Real Time Clock includes the following features BCD number second minute hour date day month and year Leap year generator Alarm function al...

Page 1047: ...ar or not For example it cannot discriminate between 1900 and 2000 To solve this problem the RTC block in S3C6400 has hard wired logic to support the leap year in 2000 Note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 in S3C6400 denote 2000 not 1900 READ WRITE REGISTER Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block To displ...

Page 1048: ...erates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode the alarm interrupt ALMINT is activated In the power off mode the power management wakeup PMWKUP signal is activated as well as the ALMINT The RTC alarm register RTCALM determines the alarm enable disable status and the condition of the alarm time setting TICK TIME INTERRUPT The RTC t...

Page 1049: ...et available Specifications and information herein are subject to change without notice 32 768KHZ X TAL CONNECTION EXAMPLE The Figure 33 2 shows a circuit of the RTC unit oscillation at 32 768Khz XTIrtc XTOrtc 32768Hz 15 22pF Figure 33 2 Main Oscillator Circuit Example EXTERNAL INTERFACE Name Direction Description XTI Input 32 KHz RTC Oscillator Clock Input XTO Input 32 KHz RTC Oscillator Clock ou...

Page 1050: ...0 ALMSEC 0x7E005054 R W Alarm second data Register 0x0 ALMMIN 0x7E005058 R W Alarm minute data Register 0x00 ALMHOUR 0x7E00505C R W Alarm hour data Register 0x0 ALMDATE 0x7E005060 R W Alarm date data Register 0x01 ALMMON 0x7E005064 R W Alarm month data Register 0x01 ALMYEAR 0x7E005068 R W Alarm year data Register 0x0 BCDSEC 0x7E005070 R W BCD second Register Undefined BCDMIN 0x7E005074 R W BCD min...

Page 1051: ...er Address R W Description Reset Value RTCCON 0x7E005040 R W RTC control Register 0x0 RTCCON Bit Description Initial State TICEN 8 Tick timer enable 0 Disable 1 Enable 0 Reserved 7 4 Reserved CLKRST 3 RTC clock count reset 0 No reset 1 Reset 0 CNTSEL 2 BCD count select 0 Merge BCD counters 1 Reserved Separate BCD counters 0 CLKSEL 1 BCD clock select 0 XTAL 1 215 divided clock 1 Reserved XTAL clock...

Page 1052: ...t Description Initial State Reserved 7 0 ALMEN 6 Alarm global enable 0 Disable 1 Enable 0 YEAREN 5 Year alarm enable 0 Disable 1 Enable 0 MONEN 4 Month alarm enable 0 Disable 1 Enable 0 DATEEN 3 Date alarm enable 0 Disable 1 Enable 0 HOUREN 2 Hour alarm enable 0 Disable 1 Enable 0 MINEN 1 Minute alarm enable 0 Disable 1 Enable 0 SECEN 0 Second alarm enable 0 Disable 1 Enable 0 ALARM SECOND DATA AL...

Page 1053: ...Alarm day data Register 0x01 ALMDATE Bit Description Initial State Reserved 7 6 00 5 4 BCD value for alarm date from 0 to 28 29 30 31 0 3 00 DATEDATA 3 0 0 9 0001 ALARM MONTH DATA ALMMON REGISTER Register Address R W Description Reset Value ALMMON 0x7E005064 R W Alarm month data Register 0x01 ALMMON Bit Description Initial State Reserved 7 5 00 4 BCD value for alarm month 0 1 0 MONDATA 3 0 0 9 000...

Page 1054: ...or second 0 5 SECDATA 3 0 0 9 BCD MINUTE BCDMIN REGISTER Register Address R W Description Reset Value BCDMIN 0x7E005074 R W BCD minute Register Undefined BCDMIN Bit Description Initial State 6 4 BCD value for minute 0 5 MINDATA 3 0 0 9 BCD HOUR BCDHOUR REGISTER Register Address R W Description Reset Value BCDHOUR 0x7E005078 R W BCD hour Register Undefined BCDHOUR Bit Description Initial State Rese...

Page 1055: ... 2 0 BCD value for a day of the week 1 7 BCD MONTH BCDMON REGISTER Register Address R W Description Reset Value BCDMON 0x7E005084 R W BCD month Register Undefined BCDMON Bit Description Initial State Reserved 7 5 4 BCD value for month 0 1 MONDATA 3 0 0 9 BCD YEAR BCDYEAR REGISTER Register Address R W Description Reset Value BCDYEAR 0x7E005088 R W BCD year Register Undefined BCDYEAR Bit Description...

Page 1056: ...notice INTERRUPT PENDING REGISTER Register Address R W Description Reset Value INTP 0x7E005030 R W BCD year Register Undefined You can clear specific bits of INTP register by writing 1 s to the bits that you want to clear regardless of the value of RTCEN INTP Bit Description Initial State Reserved 7 2 Reserved 00 ALARM 1 Alarm interrupt pending bit 0 no interrupt occurred 1 interrupt occurred 0 Ti...

Page 1057: ...RVIEW The S3C6400X RISC microprocessor watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal Advantage in using WDT instead of PWM timer is that WDT generates the reset signal FEATURES The Watchdog T...

Page 1058: ...ncy division factor are specified in the watchdog timer control WTCON register Valid prescaler values range from 0 to 28 1 The frequency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor WTDAT WTCNT Once the watchdog timer is ena...

Page 1059: ... Watchdog timer is used to resume the S3C6400 restart on mal function after its power on if controller restart is not desired the Watchdog timer must be disabled If the user wants to use the normal timer provided by the Watchdog timer enable the interrupt and disable the Watchdog timer Register Address R W Description Reset Value WTCON 0x7E004000 R W Watchdog timer control register 0x8021 WTCON Bi...

Page 1060: ...UNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note The content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially so the WTCNT register must be set to an initial value before enabling it Register Address R W Description Reset Value WTCNT 0x7E004008 R...

Page 1061: ...ple to an analog audio waveform Controller receives the stereo PCM data and the mono Mic data from Codec then store in memories This chapter describes the programming model for the AC97 Controller Unit The prerequisite in this chapter requires an understanding of the AC97 revision 2 0 specifications FEATURE The AC97 Controller includes the following features z Independent channels for stereo PCM I...

Page 1062: ... AC97 Controller operation such as AC Link Power down sequence and Wake up sequence BLOCK DIAGRAM Figure 35 1 shows the functional block diagram of S3C6400 AC97 Controller The AC97 signals form the AC link which is a point to point synchronous serial inter connecting that supports full duplex data transfers All digital audio streams and command status information are communicated over the AC link ...

Page 1063: ...ternal data path of S3C6400 AC97 Controller It has stereo Pulse Code Modulated PCM In Stereo PCM Out and mono Mic in buffers which consist of 16 bit and 16 entries buffer It also has 20 bit I O shift register via AC link Command Addr Register Command Data Register PCM Out Buffer Regfile 16 bit x 2 x 16 Entry PWDATA Response Data Register Mic In Buffer RegFile 16 bit x16 Entry PCM In Buffer Regfile...

Page 1064: ...hen you enable the codec ready interrupt You can check codec ready interrupt by polling or interrupt When interrupt is occurred you must de assert codec ready interrupt You can now transmit data from memory to register or from register to memory by using DMA or PIO directly to write data to register If internal FIFOs TX FIFO or RX FIFO are not empty then let data be transmitted In addition you can...

Page 1065: ...ws the slot definitions supported by S3C6400 AC97 Controller The S3C6400 AC97 Controller provides synchronization for all data transaction on the AC link A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame Time slot 0 is called the Tag Phase and it is 16 bits long The other 12 time slots are called the Data Phase The Tag Phase conta...

Page 1066: ... the frame as follows In slot 0 the valid bit for 1 2 slots are set In slot 1 bit 19 is set read or clear write Bits 18 12 of slot 1 are configured to specify the index to the CODEC register Others are filled with 0 s reserved In slot 2 it configured with the data which is for writing because of output frame Slot 2 Command Data Port In slot 2 this is the write data with 16 bit resolution 19 4 is v...

Page 1067: ...f the accompanying status address matches the last valid command address issued during the most recent read command For multiple sample rate output the CODEC examines its sample rate control registers its FIFOs states and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTREQ bits asserted during the current audio input...

Page 1068: ...valid bit positions in the slot with zeroes Slot 4 PCM Right channel audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec If a sample has a resolution that is less than 16 bits the AC97 Codec fills all training non valid bit positions in the slot with zeroes Slot 6 Microphone Record Data The AC97 Controller only supports 16 bit resolution for the MIC in chann...

Page 1069: ...not transmit data to slots 3 12 when it writes to the Power down register bit PR4 data 0x1000 and it does not require the Codec to process other data when it receives a power down request When the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level The AC97 Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL registe...

Page 1070: ...et A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL Asserting and deasserting nRESET activates BITCLK and SDATA_OUT All AC97 control registers are initialized to their default power on reset values nRESET is an asynchronous AC97 input Warm AC97 Reset A Warm AC97 reset reactivates the AC link without altering the current AC97 register values A warm reset is generated...

Page 1071: ...7 PCM Out In Channel FIFO Data Register 0x00000000 AC_MICDATA 0x7F00101C R W AC97 MIC In Channel FIFO Data Register 0x00000000 AC97 GLOBAL CONTROL REGISTER AC_GLBCTRL This is the global register of the AC97 controller There are interrupt control registers DMA control registers AC Link control register data transmission control register and related reset control register Register Address R W Descri...

Page 1072: ...Disable 1 Enable FIFO is half full 0 15 14 Reserved 00 PCM out channel transfer mode 13 12 00 Off 01 PIO 10 DMA 11 Reserved 00 PCM in channel transfer mode 11 10 00 Off 01 PIO 10 DMA 11 Reserved 00 MIC in channel transfer mode 9 8 00 Off 01 PIO 10 DMA 11 Reserved 00 7 4 Reserved 0000 Transfer data enable using AC link 3 0 Disable 1 Enable 0 AC Link on 2 0 Off 1 SYNC signal transfer to Codec 0 Warm...

Page 1073: ...ng you must set the Read enable bit If you want to write data to the AC97 Codec you set the index or address of the AC97 Codec and data Register Address R W Description Reset Value AC_CODEC_CMD 0x7F001008 R W AC97 Codec Command Register 0x00000000 AC_CODEC_CMD Bit Description Initial State 31 24 Reserved 0x00 Read enable 23 0 Command write 1 1 Status read 0 Address 22 16 Codec command address 0x00...

Page 1074: ...he internal PCM FIFOs address Register Address R W Description Reset Value AC_PCMADDR 0x7F001010 R AC97 PCM Out In Channel FIFO Address Register 0x00000000 AC_PCMADDR Bit Description Initial State 31 28 Reserved 0000 Out read address 27 24 PCM out channel FIFO read address 0000 23 20 Reserved 0000 In read address 19 16 PCM in channel FIFO read address 0000 15 12 Reserved 0000 Out write address 11 ...

Page 1075: ...eset Value AC_PCMDATA 0x7F001018 R W AC97 PCM Out In Channel FIFO Data Register 0x00000000 AC_PCMDATA Bit Description Initial State Right data 31 16 PCM out in right channel FIFO data Read PCM in right channel Write PCM out right channel 0x0000 Left data 15 0 PCM out in left channel FIFO data Read PCM in left channel Write PCM out left channel 0x0000 AC97 MIC IN CHANNEL FIFO DATA REGISTER AC_MICDA...

Page 1076: ...s is used which consist of a line for two time multiplexed data channels a word select line and a clock line to minimize the number of pins required and to keep wiring simple IIS interface transmits or receives sound data from external stereo audio codec For transmitting and receiving data two 32x16 FIFOs First In First Out data structures are included DMA transfer mode for transmitting or receivi...

Page 1077: ...2SSDO I2SSDI CDCLK Figure 36 1 IIS Bus Block Diagram SIGNAL DESCRIPTIONS IIS external pads are shared with other IPs like PCM AC97 and etc In order to use these pads for IIS GPIO must be set before the IIS started For more information refer to the GPIO chapter of this manual for proper GPIO setting Name Type Source Destination Description Xi2sCLK 0 Input Output Pad IIS bus0 serial clock Xi2sCDCLK ...

Page 1078: ...plied to external device Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing The IIS pre scaler clock divider is employed for generating a root clock with divided frequency from internal system clock In external master mode the root clock can be fed from IIS external directly The I2SSCLK and I2SLRCLK are supplied from the pin GPIOs in slave mode Master Slave mode is di...

Page 1079: ...with the MSB first with a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period after the I2SLRCLK is changed Serial data sent by the transmitter may be synchronized with either the trailing or the leading edge of the clock signal However the serial data must be latched into the receiver on the leading edge of t...

Page 1080: ... and I2SLRCLK makes transition every 24 cycle of I2SBCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency BCLK LRCLK LEFT RIGHT SD I2 S Format N 8 or 16 BCLK LRCLK LEFT RIGHT SD MSB Justified Left Justified Format N 8 or 16 BCLK LRCLK LEFT RIGHT SD LSB Justified Right Justified Format N 8 or 16 MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd ...

Page 1081: ...Hz 22 050 kHz 32 000 kHz 44 100 kHz 48 000 kHz 64 000 kHz 88 200 kHz 96 000 kHz 256fs 2 0480 2 8224 4 0960 5 6448 8 1920 11 2896 12 2880 16 3840 22 5792 24 5760 384fs CODECLK 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640 MHz 512fs 4 0960 5 6448 8 1920 11 2900 16 3840 22 5790 24 5760 32 7680 45 1580 49 1520 768fs 6 1440 8 4672 12 2880 16 9340 24 5760 33 8690 36 8640 49...

Page 1082: ... t distinguish Master Slave mode from TX RX mode you must study Master Slave mode and TX RX mode For more information please refer to Master Slave chapter 2 Configure I2SMOD register and I2SPSR IIS pre scaler register correctly 3 To operate system in stability the internal TXFIFO must be nearly full before transmission DMA starts because of this reason 4 IIS bus doesn t support the interrupt You c...

Page 1083: ...008 R W IIS interface FIFO control register 0x0 IISPSR 0x7F00200C 0x7F00300C R W IIS interface clock divider control register 0x0 IISTXD 0x7F002010 0x7F003010 W IIS interface transmit data register 0x0 IISRXD 0x7F002014 0x7F003014 R IIS interface receive data register 0x0 Note All registers of IIS interface are accessible by word unit with STR LDR instructions IISCON Register Address Description R...

Page 1084: ...or receive data from channel TXDMAPAUSE 6 R W Tx DMA operation pause command Note that when this bit is activated at any time the DMA request will be halted after current on going DMA transfer is completed 0 No pause DMA operation 1 Pause DMA operation RXDMAPAUSE 5 R W Rx DMA operation pause command Note that when this bit is activated at any time the DMA request will be halted after current on go...

Page 1085: ...ced to stop immediately 0 Inactive 1 Active I2SACTIVE 0 R W IIS interface active start operation 0 Inactive 1 Active IISMOD Register Address Description Reset Value IISMOD 0x7F002004 0x7F003004 IIS interface mode register 0x0000_0000 IISMOD Bit R W Description 31 13 R W Reserved Program to zero CDCLKCON 12 R W Determine codec clock source 0 Use internal codec clock source 1 Get codec clock source ...

Page 1086: ...left channel and high for right channel 1 High for left channel and low for right channel SDF 6 5 R W Serial data format 00 IIS format 01 MSB justified left justified format 10 LSB justified right justified format 11 Reserved RFS 4 3 R W IIS root clock codec clock frequency select 00 256 fs where fs is sampling frequency 01 512 fs 10 384 fs 11 768 fs BFS 2 1 R W Bit clock frequency select 00 32 fs...

Page 1087: ... count FIFO has 16 dept so value ranges from 0 to 16 N Data count N of FIFO RFLUSH 7 R W RX FIFO flush command 0 No flush 1 Flush 6 5 R W Reserved Program to zero FRXCNT 4 0 R RX FIFO data count FIFO has 16 dept so value ranges from 0 to 16 N Data count N of FIFO IISPSR Register Address Description Reset Value IISPSR 0x7F00200C 0x7F00300C IIS interface clock divider control register 0x0000_0000 II...

Page 1088: ...IS interface transmit data register 0x0000_0000 IISTXD Bit R W Description IISTXD 31 0 W TX FIFO write data Note that the left right channel data is allocated as the following bit fields R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC IISRXD Register Address Description Reset Value IISRXD 0x7F002014 0x7F003014 IIS interface receive data register 0x0000_0000 IISRXD Bit R W Description I...

Page 1089: ...he functions and usage of PCM Audio interface in S3C6400X RISC microprocessor OVERVIEW The PCM Audio Interface module provides PCM bi directional serial interface to an external Codec FEATURE The PCM Audio interface includes the following features z Master mode This block always sources the main shift clock z All PCM serial timings strobes and the main shift clock are based on an external PCM Audi...

Page 1090: ...6 bits have been shifted out an interrupt can optionally be generated indicating the end of the transfer When the data is being shifted out the PCMSIN input is used to serially shift data in from the external codec The data is received MSB first and is clocked in the falling edge of PCMSCLK The position of the first bit is programmable to be coincident with the PCMSYNC or one PCMSCLK later The fir...

Page 1091: ...SCLK input pcm_irq sync to DSP clk 14 15 13 1 0 dont care 15 14 input internal PCMSIN PCMCODEC_CLK datain_reg_valid Figure 37 1 PCM timing POS_MSB_WR RD 0 Figure 37 2 shows a PCM transfer with the MSB configured one shift clock after the PCMSYNC This MSB positioning corresponds to setting the MSB_POS_WR and MSB_POS_RD bits in PCMCTL register to be HIGH PCMSYNC PCMSOUT 15 14 1 0 dont care 15 output...

Page 1092: ...on herein are subject to change without notice PCM Input Clock Diagram 1 N PCLK EXT_CODEC_CLKIN CTL_SERCLK_SEL PCM EPLL APLL or MPLL System Controlller XpcmEXTCLK 0 XpcmEXTCLK 1 Clock Divider Figure 37 3 Input Clock Diagram for PCM S3C6400X can provide PCM with a variety of clock PCM is able to select from two clock PCLK or AUDIO clock which is from system controller We can also select AUDIO clock...

Page 1093: ... Reset Value PCM_CTL 0x7F009000 0x7F00A000 R W PCM Main Control 0x00000000 PCM_CLKCTL 0x7F009004 0x7F00A004 R W PCM Clock and Shift control 0x00000000 PCM_TXFIFO 0x7F009008 0x7F00A008 R W PCM TxFIFO write port 0x00000000 PCM_RXFIFO 0x7F00900C 0x7F00A00C R W PCM RxFIFO read port 0x00000000 PCM_IRQ_CTL 0x7F009010 0x7F00A010 R W PCM Interrupt Control 0x00000000 PCM_IRQ_STAT 0x7F009014 0x7F00A014 R PC...

Page 1094: ...PCM_CTL Bit Description Initial State Reserved 31 19 Reserved TXFIFO_DIPSTICK 18 13 Determines when the almost_full almost_empty flags go active for the TXFIFO Almost_empty fifo_depth fifo_dipstick Almost_full fifo_depth 32 fifo_dipstick NOTE if fifo_dipstick 0 Almost_empty Almost_full are invalid NOTE NOTE for DMA loading of TX fifo Txfifo_dipstick 2 This is required since the PCM_TXDMA uses almo...

Page 1095: ...should be 0x20 This will have the effect of rx_fifo_almost_full acting as a rx_fifo_not_empty flag 0 PCM_TX_DMA_EN 6 Enable the DMA interface for the TXFIFO DMA must operate in the demand mode DMA_TX request will occur whenever the TXFIFO is not almost full 0 PCM_RX_DMA_EN 5 Enable the DMA interface for the RXFIFO DMA must operate in the demand mode DMA_RX request will occur whenever the RXFIFO is...

Page 1096: ...without notice PCM_CTL Bit Description Initial State PCM_TXFIFO_EN 2 Enable the TXFIFO 0 PCM_RXFIFO_EN 1 Enable the RXFIFO 0 PCM_PCM_ENABLE 0 PCM enable signal Enables the serial shift state machines The enable must be set HIGH for the PCM to operate When the enable is LOW the PCMSOUT will not toggle Additionally when the enable is LOW the internal divider counters are held in reset When the enabl...

Page 1097: ... bit definitions for the PCM_CTL Control Register are described below PCM_CLKCTL Bit Description Initial State Reserved 31 20 Reserved CTL_SERCLK_EN 19 Enable the serial clock division logic Must be HIGH for the PCM to operate if it is high SCLK and FSYNC is operated 0 CTL_SERCLK_SEL 18 Select the source of the serial clock 0 external_codec_clock input 1 PCLK 0 SCLK_DIV 17 9 Controls the divider u...

Page 1098: ...FO 0x7F009008 0x7F00A008 R W Control the PCM Audio Inteface 0x00000000 The bit definitions for the PCM_TXFIFO Register are described below PCM_TXFIFO Bit Description Initial State Reserved 31 17 Reserved TXFIFO_DVALID 16 TXFIFO data is valid Write Not Valid Read TXFIFO read data valid 1 valid 0 invalid probably read an empty fifo 0 TXFIFO_DATA 15 0 TXFIFO DATA Write TXFIFO_DATA is written into the...

Page 1099: ...0x7F00900C 0x7F00A00C R W Control the PCM Audio Inteface 0x00000000 The bit definitions for the PCM_RXFIFO Register are described below PCM_RXFIFO Bit Description Initial State Reserved 31 17 Reserved RXFIFO_DVALID 16 RXFIFO data is valid Write Not Valid Read TXFIFO read data valid 1 valid 0 invalid probably read an empty fifo 0 RXFIFO_DATA 15 0 RXFIFO DATA Write RXFIFO_DATA is written into the RX...

Page 1100: ...nitions for the PCM_IRQ_CTL Control Register are described below PCM_IRQ_CTL Bit Description Initial State Reserved 31 15 Reserved EN_IRQ_TO_ARM 14 Controls whether or not the PCM interrupt is sent to the ARM 1 PCM IRQ is forwarded to the ARM subsystem 0 PCM IRQ is NOT forwarded to the ARM subsystem 0 Reserved 13 Reserved 0 TRANSFER_DONE 12 Interrupt is generated every time the serial shift for a ...

Page 1101: ...FO is ALMOST full Almost full is defined as FIXME words remaining 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_ERROR_STARVE 7 Interrupt is generated for TxFIFO starve ERROR This occurs whenever the TxFIFO is read when it is still empty This is considered as a ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_ERROR_OVERFLO W 6 Interrupt is generated f...

Page 1102: ...generated whenever the RxFIFO is full 1 IRQ source enabled 0 IRQ source disabled 0 RX_FIFO_ALMOST_FULL 2 Interrupt is generated whenever the RxFIFO is ALMOST full Almost full is defined as FIXME words remaining 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ERROR_STARVE 1 Interrupt is generated for RxFIFO starve ERROR This occurs whenever the RxFIFO is read when it is still empty This is cons...

Page 1103: ...scribed below PCM_IRQ_STAT Bit Description Initial State Reserved 31 14 Reserved IRQ_PENDING 13 Controls whether or not the PCM interrupt is sent to the ARM 1 PCM IRQ is forwarded to ARM 0 PCM IRQ is NOT forwarded to ARM 0 TRANSFER_DONE 12 Interrupt is generated every time the serial shift for a word completes 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_EMPTY 11 Interrupt is generated when...

Page 1104: ...ver the TxFIFO is read when it is still empty This is considered as a ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_ERROR_OVERFLOW 6 Interrupt is generated for TxFIFO overflow ERROR This occurs whenever the TxFIFO is written when it is already full This is considered as a ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled ...

Page 1105: ...xFIFO is ALMOST full Almost full is defined as FIXME words remaining 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ERROR_STARVE 1 Interrupt is generated for RxFIFO starve ERROR This occurs whenever the RxFIFO is read when it is still empty This is considered as a ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ERROR_OVERFLOW 0 Interrupt is generated...

Page 1106: ...2 To indicate whether TXFIFO is almost empty 0 TXFIFO_FULL 11 To indicate whether TXFIFO is full 0 TXFIFO_ALMOST_FULL 10 To indicate whether TXFIFO is almost full 0 RXFIFO_COUNT 9 4 To indicate RXFIFO usage RXFIFO_EMPTY 3 To indicate whether RXFIFO is empty 0 RXFIFO_ALMOST_EMPTY 2 To indicate whether RXFIFO is almost empty 0 RX_FIFO_FULL 1 To indicate whether RXFIFO is full 0 RX_FIFO_ALMOST_FULL 0...

Page 1107: ...pment for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice The bit definitions for the PCM_CLRINT Register are described below PCM_CLRINT Bit Description Initial State Reserved 31 1 Reserved 0 CLRINT 0 Interrupt register clear 0 NOTE ...

Page 1108: ...ore supports two different types of IrDA speed MIR FIR This core can transmit Ir Infrared pulses up to 4 Mbps speed It includes configurable FIFO feature to reduce the CPU burden This makes it easy to adjust the internal FIFO sizes You can program the core by accessing 16 internal registers When receiving the Ir pulses this core detects three kinds of line errors such as CRC error PHY error and pa...

Page 1109: ...fications and information herein are subject to change without notice BLOCK DIAGRAM CLK_GEN MASTER_Control LSR ACREG MDR FCR Iinterrupt Control and payload length store IER ICR RXFLH RXFLL TXFLH TXFLL TX FIFO Control THR PLR RX FIFO Control RBR PLL FIR Mod Demodl MIR Mod Demodl MUX M MCLK 48MHz INTERRUPT DMA IRRX IRTX HRESETn TX FIFO RAM RX FIFO RAM IRSDBW MOD DEMOD MOD DEMOD AHB BUS Figure 38 1 B...

Page 1110: ...signal PRESETn 1 IN APB signal PSEL 1 IN APB signal PADDR 19 2 18 IN APB signal PWDATA 7 0 8 IN APB signal PENALBE 1 IN APB signal PWRITE 1 IN APB signal APB PRDATA 31 0 32 OUT APB signal INTR INTREQ 1 OUT INTC DMAACK 1 IN DMA DMA DMAREQ 1 OUT DMA MCLK 1 IN SYSCON IrDA operation clock must be 48MHz IrDA_Rx 1 IN PAD IrDA_Tx 1 OUT PAD IrDA special signal IrDA_SDBW 1 OUT PAD STMODE 1 IN Test signal T...

Page 1111: ...o change without notice SCLK 1 IN BIST signal MBIST_MCS_CNTR_MODE 1 IN BIST signal MBIST_MCS0_COMN_IN 1 IN BIST signal MBIST_MCS1_COMN_IN 1 IN BIST signal BISTON_BIST 1 IN BIST signal ERRORB_BIST 1 OUT BIST signal DONE_BIST 1 OUT BIST signal DIAG_BIST 1 OUT BIST signal IrDA_CSN 1 IN BIST signal PDN_RB_IrDA_RxRAM 1 IN BIST signal PDN_RB_IrDA_TxRAM 1 IN BIST signal SLN_RB_IrDA_RxRAM 1 IN BIST signal...

Page 1112: ...n it extracts the payload from the received 4PPM data until it meets the Stop Flag The core detects three different kinds of errors which may occur in the middle of transmission These errors are the Phy Error the Frame Length Error and the CRC error The CRC error is checked when the entire payload data is received The micro controller can monitor the error status of the received frame by reading t...

Page 1113: ...ransmit Pay Load Transmit CRC CRC Transmit Stop Flag Transmit ena ena pre_end str_end pay_end crc_end stp_end ena append Frame data with error crc abort by underrun abort 2u Pulse transmit sip pul_end ena 0 1 2 3 4 5 6 7 stp_end ena pul_end ena Figure 38 2 FIR modulation process Figure 38 2 shows the FIR modulation state machine The FIR transmission mode can be selected by programming ACR register...

Page 1114: ...and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 38 3 FIR demodulation process Figure 38 3 shows FIR demodulation state machine The state machine starts when ACR register bit 6 is set to logic high The incoming data will be depacketized by removing preamble and start flag and stop flag ...

Page 1115: ...ocess the basic wrapping and de wrapping processes are same as the FIR mode ㄷThe MIR mode needs a bit stuffing procedure Bit stuffing in MIR mode have the core insert zero bit per every 5 consecutive ones in transmission mode In receiving mode the stuffed bit must be removed Like the fir mode case three different kinds of errors crc phy and frame length error can be reported to the microcontroller...

Page 1116: ...uff bit Stop Flag Transmit ena ena pay_end crc_end stp_end ena append Frame data with error crc eflag abort by underrun abort 2u Pulse transmit sip pul_end ena 0 stp_end ena pul_end ena 1 2 3 4 5 6 str_end Figure 38 5 MIR modulation process Figure 38 5 describes MIR modulation state machine This machine works very similarly as FIR modulation state machine The major difference is that the MIR data ...

Page 1117: ...y Load Detect De Stuff ena flagbyte 0 1 3 str_end ena flagbyte CRC check Stp Det 2 pay_end stp_end Figure 38 6 MIR demodulation process Figure 38 6 shows the MIR demodulation state machine It has similar structure as FIR demodulation state machine Instead of 4 PPM demodulation phase it has the stage of removing stuffed bits from payload data stream Since the MIR data stream doesn t have preamble d...

Page 1118: ... 0 1 b0 and ACR 0 1 b1 For the HP type transceiver program just once in ACR 0 1 b0 to FIR MIR mode 3 Program the PLR register to select the number of preamble or start flag and TX threshold level 4 Program the RXFLL and RXFLH register maximum available receive bytes in frame 5 Program the TXFLL and TXFLH register transmit bytes in transmission frame 6 Program the FCR register FIFO size and RX thre...

Page 1119: ...half mode 4 MIR half mode When bit 4 is set to a 1 the operating speed in the MIR mode changes from 1 152 Mbps to 0 576 Mbps 0 Send IR pulse 3 Send 1 6 us IR pulse When the IrDA_MDR 3 bit equals to a 1 and the CPU writes a 1 to this bit the transmitting interface device sends a 1 6 us IR pulse at the end of the frame Bit 3 is cleared automatically by the transmitting interface device at the end of...

Page 1120: ...ise when this bit is set to a 0 SIP is generated at the end of the every FIR MIR frames If IrDA_CNT 3 is set to 0 setting this bit to 1 doesn t help to generate SIP Along with IrDA_CNT 3 bit the way of SIP generation can be controlled 0 Temic select 3 Bit 3 is Temic transceiver select bit When bit 3 is clear to 0 core automatically selects in Temic transceiver mode 0 Reserved 2 1 Reserved 00 Mode ...

Page 1121: ...eiving mode 0 Tx Underrun 5 Enables transmitter under run interrupt 0 Last byte detect 4 Detect stop flag interrupt enable If this bit is set to 1 an interrupt signal will be activated when the last byte of the received data frame comes into the demodulation block and then CRC decoding is finished 0 Rx overrun 3 Enables receiver over run interrupt 0 Last byte read from Rx FIFO 2 Bit 2 enables last...

Page 1122: ... Tx Underrun 5 Transmit under run interrupt pending When corresponding interrupt enable bit is active bit 5 is set to 1 if an under run occurs in TX FIFO Bit 5 is cleared by serving the under run 0 Last byte detect 4 Detects last byte of a frame interrupt pending If the corresponding interrupt enable bit is active bit 4 is set to 1 when the demodulation block detects the last byte of a received fr...

Page 1123: ...length error It is set to 1 when a frame exceeding the maximum frame length predefined by IrDA_RXFLL and IrDA_RXFLH register is received This bit is cleared when the microcontroller reads the IrDA_LSR register When this error is detected current frame reception is terminated Data receiving is stopped until the next BOF is detected Bit 4 is cleared to 0 when the IrDA_LSR register is read by the mic...

Page 1124: ...Must set to 1 to use 64 bytes TX and RX FIFO 0 TX FIFO Clear Notification 4 This bit will be activated when the FIFO clear is over This bit is cleared by the CPU reads this register 0 RX FIFO CLEAR NOTIFICATION 3 This bit will be activated when the FIFO clear is over This bit is cleared by the CPU reads this register 0 Tx FIFO reset 2 TX FIFO reset When set to 1 bit 2 clears all bytes in the trans...

Page 1125: ...ger level select 5 4 Transceiver FIFO trigger level selection Bit 5 Bit 4 64 byte FIFO 0 0 Reserved 0 1 48 1 0 32 1 1 08 Note Tx Trigger level value means total number data empty 01 Number of start flags in MIR mode 3 0 Number of start flags in MIR mode The number of start flags to be transmitted at the beginning of a frame is equal to the IrDA_PLR 3 0 value The minimum value is 3 0010 IRDA RECEIV...

Page 1126: ...The total number of data bytes remained in Rx FIFO 00 IRDA TRANSMIT FRAME LENGTH REGISTER LOW IRDA_TXFLL Register Address R W Description Reset Value IrDA _TXFLL 0x7F00_702C R W IrDA Transmit Frame Length Register Low 0x00 IrDA _TXFLL Bit Description Initial State Tx frame length low 7 0 TXFLL stores the lower 8 bits of the byte number of the frame to be transmitted 00 IRDA TRANSMIT FRAME LENGTH R...

Page 1127: ...received 00 IRDA RECEIVER FRAME LENGTH REGISTER HIGH IRDA_RXFLH Register Address R W Description Reset Value IrDA _RXFLH 0x7F00_7038 R W IrDA Receive Frame Length Register High 0x00 IrDA _RXFLH Bit Description Initial State Reserved 7 6 Reserved 00 Rx frame length high 5 0 TXFLL stores the upper 6 bits of the maximum byte number of the frame to be received IRDA INTERRUPT CLEAR REGISTER IRDA_INTCLR...

Page 1128: ...er clock A D converter operates with on chip sample and hold function The power down mode is supported Touch Screen Interface is controlling pads XP XM YP YM of Touch Screen and selecting pads XP XM YP YM of the Touch Screen for X position conversion Y position conversion The Touch Screen Interface contains Touch Screen Pads control logic and ADC interface logic with an interrupt generation logic ...

Page 1129: ...k diagram of A D converter and Touch Screen Interface Note The A D converter device is a recycling type Pullup Waiting for Interrupt Mode INT_WKU INT_ADC 8 1 MUX A D Converter ADC input control Touch Screen Pads control Interrupt Generation ADC interface Touch Screen Control AVDD AGND XP XM YP YM A 3 0 note note Figure 39 1 ADC and Touch Screen Interface Functional Block Diagram Note symbol When T...

Page 1130: ... method X Position Mode writes X Position Conversion Data to ADCDAT0 therefore Touch Screen Interface generates the Interrupt source to Interrupt Controller Y Position Mode writes Y Position Conversion Data to ADCDAT1 therefore Touch Screen Interface generates the Interrupt source to Interrupt Controller 3 Auto Sequential X Y Position Conversion Mode Auto Sequential X Y Position Conversion Mode is...

Page 1131: ... may be delayed because of the return time of interrupt service routine and data access time Polling method is used to check the ADCCON 15 end of conversion flag bit The read time can be determined from ADCDAT register 2 Another method to start A D conversion is provided After ADCCON 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously when converted data is read XP...

Page 1132: ...rsion flag Read only 0 A D conversion in process 1 End of A D conversion 0 PRSCEN 14 A D converter prescaler enable 0 Disable 1 Enable 0 PRSCVL 13 6 A D converter prescaler value Data value 5 255 This A D converter is designed to operate at maximum 2 5MHz clock 0xFF SEL_MUX 5 3 Analog input channel select 000 AIN 0 001 AIN 1 010 AIN 2 011 AIN 3 100 YM 101 YP 110 XM 111 XP 0 STDBM 2 Standby mode se...

Page 1133: ... Disable 1 XM_SEN 5 XM Switch Enable 0 XM Output Driver Disable 1 XM Output Driver Enable 0 XP_SEN 4 XP Switch Enable 0 XP Output Driver Enable 1 XP Output Driver Disable 1 PULL_UP 3 Pull up Switch Enable 0 XP Pull up Enable 1 XP Pull up Disable 1 AUTO_PST 2 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto Sequential measurement of X position Y position 0...

Page 1134: ...t Value ADCDLY 0x7E00B008 R W ADC Start or Interval Delay Register 0x00ff ADCDLY Bit Description Initial State FILCLKsrc 16 ADCDLY clock source 0 External input clock 1 RTC clock 0 DELAY 15 0 1 Normal Conversion Mode XY Position Mode Auto Position Mode ADC conversion start delay value 2 Waiting for Interrupt Mode When Stylus Down occurs at STOP MODE it generates Wake Up signal having interval seve...

Page 1135: ...rsion Data Register ADCDAT0 Bit Description Initial State UPDOWN 15 Up or Down state of Stylus at Waiting for Interrupt Mode 0 Stylus down state 1 Stylus up state AUTO_PST 14 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position XY_PST 13 12 Manual measurement of X Position or Y Position 00 No operation mode 01 X posi...

Page 1136: ...DAT1 0x7E00B010 R ADC Conversion Data Register ADCDAT1 Bit Description Initial State UPDOWN 15 Up or Down state of Stylus at Waiting for Interrupt Mode 0 Stylus down state 1 No stylus down state AUTO_PST 14 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position XY_PST 13 12 Manual measurement of X Position or Y Positio...

Page 1137: ...ailable Specifications and information herein are subject to change without notice ADC TOUCH SCREEN UP DOWN REGISTER ADCUPDN Register Address R W Description Reset Value ADCUPDN 0x7E00B014 R W Stylus Up or Down Interrpt Register 0x0 ADCDAT1 Bit Description Initial State TSC_DN 1 Stylus Down Interrupt 0 No stylus down status 1 Stylus down status 0 TSC_UP 0 Stylus Up Interrupt 0 No stylus up status ...

Page 1138: ... ADC TOUCH SCREEN INTERRUPT CLEAR REGISTER These registers are used to clear the interrupts Interrupt service routine is responsible for clearing interrupts after the interrupt service is completed Writing any values on this register will clear up the relevant interrupts asserted When it is read undefined value will be returned Register Address R W Description Reset Value ADCCLRINT 0x7E00B018 W Cl...

Page 1139: ...xternal keypad devices The ports multiplexed with GPIO ports provide up to 8 rows and 8 columns The events of key press or key release are detected to the CPU by an interrupt When any of the interrupt from row lines occurs the software will scan the column lines using the proper procedure to detect one or multiple key press or release It provides interrupt status register bits when key pressed or ...

Page 1140: ... The debouncing filter is supported for keypad interrupt of any key input The filtering width is approximately 62 5usec FLT_CLK two clock when the FLT_CLK is 32 KHz The keypad interrupt key pressed or key released to the CPU is an ANDed signal of the all row input lines after filtering FILTER_IN FILTER_OUT Filter width FCLK two clock Filter Clock FCLK is a FLT_CLK or the division of that clock FLT...

Page 1141: ...t up to 8 inputs and 8 outputs GPIO port Keypad interface port I O GPIOK 8 ROW_IN 0 I GPIOK 9 ROW_IN 1 I GPIOK 10 ROW_IN 2 I GPIOK 11 ROW_IN 3 I GPIOK 12 ROW_IN 4 I GPIOK 13 ROW_IN 5 I GPIOK 14 ROW_IN 6 I GPIOK 15 ROW_IN 7 I GPIOL 0 COL_OUT 0 O GPIOL 1 COL_OUT 1 O GPIOL 2 COL_OUT 2 O GPIOL 3 COL_OUT 3 O GPIOL 4 COL_OUT 4 O GPIOL 5 COL_OUT 5 O GPIOL 6 COL_OUT 6 O GPIOL 7 COL_OUT 7 O Table 40 1 Keyp...

Page 1142: ...le mode is not used these bits must be written to zeros When no key pressed state all row lines inputs are high used pull up pads When any key is pressed the corresponding row and column lines are shortened together and a low level is driven on the corresponding row line generating a keypad interrupt The CPU software writes with a LOW level on one column line and HIGH on the others to the KEYIFCOL...

Page 1143: ...rmation describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 40 4 Keypad scanning procedure II Figure 40 5 Keypad scanning procedure III ...

Page 1144: ...R proceed scanning procedure Key Release Interrupt Occured S W ISR set flag option 1st Row Key interrupt S W in ISR pressed key is detected row column 2nd Row Key pressed state 1st Row Key interrupt set to Released key state 2nd Row Key interrupt S W in ISR pressed key is detected S W detect when the 1st Row Key pressed state 2nd Row Key Interrupt set to Released key state 1st Row Key pressed stat...

Page 1145: ...reliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 40 7 Keypad I F block diagram ...

Page 1146: ...a input register Reflects input ports KEYIFFC 0x7E00A010 R W KEYPAD interface debouncing filter clock division register 0x00000000 Register Description KEYPAD INTERFACE CONTROL REGISTERS KEYIFCON Register address R W Description Reset Value KEYIFCON 0x7E00A000 R W KEYPAD interface control register 0x00 KEYIFCON Bit Description INT_F_EN 0 KEYPAD input port falling edge key pressed interrupt 0 Disab...

Page 1147: ...t each key pressed from 0 to 7 has a dedicated interrupt to it from P_INT 0 to P_INT 7 R_INT 15 8 KEYPAD input release interrupts rising edge status read and clear write Read 1 Released interrupt occurred 0 Does not occur Write Released interrupt is cleared when write data is 1 The R_INT 7 0 indicate that each key released from 0 to 7 has a dedicated interrupt to it from R_INT 0 to R_INT 7 Reserve...

Page 1148: ...eflects input ports KEYIFROW Bit Description KEYIFROW 7 0 KEYPAD interface row data input register read only This register values from input ports are not filtered data Reserved 31 8 KEYPAD INTERFACE DEBOUNCING FILTER CLOCK DIVISION REGISTER Register address R W Description Reset Value KEYIFFC 0x7E00A010 R W KEYPAD interface debouncing filter clock division register 0x0 KEYIFFC Bit Description KEY...

Page 1149: ...ted under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximumrated conditions for extended periods may affect device reliability Table 41 1 Absolute Maximum Rating Parameter Symb...

Page 1150: ...zation data and associated errata are not yet available Specifications and information herein are subject to change without notice VIN 2 5V Input buffer 0 5 3 6 VIN 3 3V Input buffer 0 5 4 6 VOUT 1 8V 0 5 2 5 VOUT 2 5V 0 5 3 6 DC Output Voltage VOUT 3 3V 0 5 4 6 DC Input Current IIN 20 mA Storage Temperature TSTG Storage Junction Temperature Range 65 to 150 o C ...

Page 1151: ...ld be used under the operating conditions contained in Table 41 2 Table 41 2 Recommended Operating Conditions Parameter Symbol Min Typ Max Unit DC Supply Voltage for Alive Block VDDALIVE 0 95 1 0 1 05 DC Supply Voltage for internal VDDAPLL VDDMPLL VDDEPLL VDDOTGI VDDINT 0 95 1 0 1 05 VDDARM 400MHz 0 95 1 0 1 05 VDDARM 533MHz 1 05 1 1 1 15 DC Supply Voltage for ARM Core VDDARM 667MHz VDDMMC 1 65 3 ...

Page 1152: ...ithout notice DC Supply Voltage for Memory Interface VDDMEM0 VDDMEM1 1 65 1 65 1 8 2 85 1 8 2 5 3 0 2 75 DC Supply Voltage for RTC VDDRTC 2 25 2 5 2 75 DC Supply Voltage for USB VDDOTG VDDUH 3 0 3 3 3 6 DC Supply Voltage for ADC VDDADC 3 0 3 3 3 6 DC Supply Voltage for DAC VDDDAC 3 0 3 3 3 6 3 0 3 3 3 6 2 3 2 5 2 7 DC Input Voltage VIN 1 65 1 8 1 95 3 0 3 3 3 6 2 3 2 5 2 7 DC Output Voltage VOUT 1...

Page 1153: ...o determine maximum DC loading and to determine maximum transition times for a given load Table 41 3 shows the DC operating conditions for the high and low strength input output and I O pins Table 41 3 Normal I O PAD DC Electrical Characteristics VDD 1 65v 3 60v TА 40 to 85 C Symbol Parameter Condition Min Typ Max Unit High Level Input Voltage VIH LVCMOS Interface 0 7 VDD VDD 0 3 V Low Level Input...

Page 1154: ...put capacitance Any Output buffer 4 pF Table 41 4 Special Memory DDR I O PAD DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VDDM0 VDDM1 Output supply voltage 1 65 1 8 2 5 3 0 2 75 V VDDINT Internal Voltage 0 9 1 0 1 1 V Temp Ambient Temperature 40 25 85 C VIH dc Input Logic High 0 8 VDDM 0 1 V VIL dc Input Logic Low 0 2 VDDM 0 1 V IIH High Level Input Current 10 10 uA IIL Low Leve...

Page 1155: ...input voltage 2 5 V VIL Low level input voltage 0 8 V IIH High level input current Vin 3 3V 10 10 μA IIL Low level input current Vin 0 0V 10 10 μA VOH Static Output High 15K to GND 2 8 3 6 V VOL Static Output Low 1 5K to 3 6V 0 3 V Table 41 6 RTC OSC DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VDD_RTC Output supply voltage 2 25 2 5 2 75 V VIH DC input logic high 0 8 VDDRTC V VI...

Page 1156: ...alternating current AC characteristics include input and output capacitance These factors determine the loading for external drivers and other load analyses The AC characteristics also include a derating factor which indicates how much the AC timings might vary with different loads 1 2 VDD_SYS 1 2 VDD_SYS tXTALCYC NOTE The clock input from the XTIpll pin Figure 41 1 XTIpll Clock Timing tEXTHIGH 1 ...

Page 1157: ...that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice HCLK internal EXTCLK tEX2HC Figure 41 3 EXTCLK HCLK in case that EXTCLK is used without the PLL Figure 41 4 Manual Reset Input Timing ...

Page 1158: ...inary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 41 5 Power On Oscillation Setting Timing ...

Page 1159: ...ch full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice XTIpll VCO Output Clock Disable FCLK Several slow clock cycles XTIpll or EXTCLK Sleep mode is initiated tOSC2 EXTCLK Wake up from sleep mode Figure 41 6 Sleep Mode Return Oscillation Setting Timing ...

Page 1160: ...o VDDALIVE tOA 0 ms VDDALIVE to VDDINT VDDARM tAI 1 us VDDARM to PWR_EN PWRRGTON tAE 1 10 ns VDDLOGIC VDDARM to Oscillator stabilization tOSC 10 cycle Oscillator stabilization to nRESET nTRST high tOR 1 us External clock input high level pulse width tEXTHIGH 20 ns External clock to HCLK without PLL tEX2HC 5 10 ns HCLK internal to CLKOUT tHC2CK 4 10 ns HCLK internal to SCLK tHC2SCLK 2 8 ns Reset as...

Page 1161: ... available Specifications and information herein are subject to change without notice HCLK Xm0ADDR Xm0CSn x Xm0OEn Xm0DQM n Xm0DATA R Xm0DATA W Tacs Tcos Tacc Tcoh Tcah tRCD tRAD tRCD tROD tROD tRBED tRDH tRDS tRBED ADDRESS tRAD DATA tRDD tRDD DATA Xm0WAITn R 3ns Sampling nWAIT Xm0WEn Tcos Tcoh tRWD tRWD Xm0WAITn W tWH tWS Figure 41 7 ROM SRAM Timing Tacs 0 Tcos 0 Tacc 2 Tcoh 0 Tcah 0 PMC 0 ST 0 D...

Page 1162: ... 0 25V 1 8V 0 15V Parameter Symbol Min Max Unit ROM SRAM Address Delay tRAD 8 50 ns ROM SRAM Chip Select 0 Delay tRCD 8 08 ns ROM SRAM Chip Select 1 Delay tRCD 7 78 ns ROM SRAM Chip Select 2 Delay tRCD 7 76 ns ROM SRAM nOE Output Enable Delay tROD 8 60 ns ROM SRAM nWE Write Enable Delay tRWD 8 21 ns ROM SRAM Byte Enable Delay tRBED 8 46 ns ROM SRAM Write Byte Enable Delay tRWBED 8 46 ns ROM SRAM O...

Page 1163: ...DY1_CLE D6 D7 D0 D1 D2 D3 D7 D0 ADDR tCER tAVDS tAVDH tRDYO tAVDO tACS tACH tIAA tOE tRDYA tRDYS tCLKH tCLKL tCEZ tOEZ tBA tBDH tCLK Xm0CSnx Xm0ADRVALID Xm0DATA Xm0OEn Xm0RDY0_ALE Xm0RDY1_CLE ADDR tCER tAAVDS tAAVDH tAVDO tAVDP tAA tOE Xm0WEn READ DATA HiZ HiZ tRC tCEZ tOEZ tOEH tCA tCE tWEA HiZ tACC ADDR WRITE DATA tAVDP WRITE DATA ADDR HiZ HiZ Asynchronous Read Timing Asynchronous Write Timing t...

Page 1164: ...sable to Output High Z tCEZ 20 ns OneNAND OEn Disable to Output High Z tOEZ 15 ns OneNAND Address Setup time to SMCLK tACS 5 ns OneNAND Address Hold time to SMCLK tACH 6 ns OneNAND ADRVALID Setup time to SMCLK tAVDS 5 ns OneNAND ADRVALID Hold time to SMCLK tAVDH 6 ns OneNAND Write Data Setup time to SMCLK tWDS 5 ns OneNAND Write Data Hold time to SMCLK tWDH 2 ns OneNAND WEn Setup time to SMCLK tWE...

Page 1165: ...t to change without notice OneNAND Address Hold to rising edge of ADRVALID tAAVDH 7 ns OneNAND CSn Setup to ADRVALID falling edge tCA 0 ns OneNAND WEn Disable to ADRVALID enable tWEA 15 ns OneNAND Address to OEn low tASO 10 ns OneNAND WEn Cycle time tWC 70 ns OneNAND Data Setup time tDS 30 ns OneNAND Data Hold time tDH 0 ns OneNAND CSn Setup time tCS 0 ns OneNAND CSn Hold time tCH 0 ns OneNAND WEn...

Page 1166: ...18 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 41 9 Nand Flash Timing ...

Page 1167: ...t to change without notice Table 41 10 NFCON Bus Timing Constants VDDINT 1 0V 0 05V TA 40 to 85 C VDDM0 2 85V 0 15V 1 8V 0 15V Parameter Symbol Min Max Unit NFCON Chip Enable delay tCED 7 83 ns NFCON CLE delay tCLED 8 96 ns NFCON ALE delay tALED 8 38 ns NFCON Write Enable delay tWED 9 42 ns NFCON Read Enable delay tRED 10 03 ns NFCON Write Data delay tWDD 8 78 ns NFCON Read Data Setup requirement ...

Page 1168: ...ct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 41 10 SDR SDRAM READ WRITE Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit ...

Page 1169: ...VDDINT 1 0V 0 05V TA 40 to 85 C VDDM1 2 5V 0 25V 1 8V 0 15V Parameter Symbol Min Max Unit SDRAM Address Delay tSAD 1 58 5 61 ns SDRAM Chip Select Delay tSCSD 1 98 5 27 ns SDRAM Row active Delay tSRD 1 88 4 67 ns SDRAM Column active Delay tSCD 1 63 3 96 ns SDRAM Byte Enable Delay tSBED 1 80 4 58 ns SDRAM Write enable Delay tSWD 2 13 5 51 ns SDRAM read Data Setup time tSDS 3 00 ns SDRAM read Data Ho...

Page 1170: ...ations and information herein are subject to change without notice Xm SCLK Xm RASn tSAD Xm CASn Xm DATA Xm ADDR Xm CKE Xm0AP Xm1ADDR 10 Xm CSnx Xm0WEndmc Xm1WEn ADDR Xm0WEndmc Xm1WEn Xm DATA Write Timing tSAD tSCSD tSRD tSCD tSWD Read Timing tDDD Xm DQS n tDDS Xm DQS n tDQSD tRPRE tSAC tRPST tDQSS tWPRES tWPREH Xm DQM n ADDR ADDR tSWD tWR tWPST tDQSL tDQSH Figure 41 11 DDR SDRAM READ WRITE Timing ...

Page 1171: ... and information herein are subject to change without notice Xm SCLK Xm RASn tSAD Xm CASn Xm DATA Xm ADDR Xm DQM n Xm CKE Xm0AP Xm1ADDR 10 Xm CSnx Xm0WEndmc Xm1WEn ADDR ADDR tSAD tSCSD tSRD tSCD tSWD tSWD tSWD tSWD tSCSD tSRD 1 HiZ 1 ADDR tSAD tSAD tSCSD tSCSD tSRD tSRD tSCD tSWD tSWD Figure 41 12 SDRAM MRS Timing and Auto Refresh Timing Trp 2 Trc 4 Note Before executing auto self refreshing comma...

Page 1172: ...RAM Byte Enable Delay tSBED 0 06 0 02 ns DDR SDRAM Write enable Delay tSWD 2 24 5 51 ns DDR SDRAM Output data access time from CK tSAC 2 00 6 00 ns DDR SDRAM Row Precharge time tRP 22 50 ns DDR SDRAM RAS to CAS delay tRCD 22 50 ns DDR SDRAM Write recovery time tWR 12 00 ns DDR SDRAM Clock low level width tCL 3 38 4 12 ns DDR SDRAM Read Preamble tRPRE 6 75 8 25 ns DDR SDRAM Read Postamble tRPST 3 0...

Page 1173: ...lopment for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Figure 41 13 TFT LCD Controller Timing ...

Page 1174: ...pulse width Tvclk 18 200 ns VCLK pulse width high Tvclkh 0 3 Pvclk 1 VCLK pulse width low Tvclkl 0 3 Pvclk Vertical sync pulse width Tvspw VSPW 1 Phclk 2 Vertical back porch delay Tvbpd VBPD 1 Phclk Vertical front porch dealy Tvfpd VFPD 1 Phclk Hsync setup to VCLK falling edge Tl2csetup 0 3 Pvclk VDEN set up to VCLK falling edge Tde2csetup 0 3 Pvclk VDEN hold from VCLK falling edge Tde2chold 0 3 P...

Page 1175: ...XhiCSn XhiWEn XhiDATA tAVWR tCSVWR tDHWR tWR tDSUWR tAWR Figure 41 14 Modem interface write timing diagram Table 41 14 Modem interface write timing VDDINT 1 0V 0 05V TA 40 to 85 C VDDHI 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Description Min ns Max ns Notes tAVWR Address valid to address invalid 16 ns tCSVWR Chip select active 16 ns tAWR Address valid to write active 4 ns tWR Write active 8 ns t...

Page 1176: ...RDDV tADH tCSRD Figure 41 15 Modem interface read timing diagram Table 41 15 Modem interface read timing VDDINT 1 0V 0 05V TA 40 to 85 C VDDHI 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Description Min ns Max ns Notes tAVRD Address valid to address invalid 50 ns tADH Address hold 0 ns tCSVRD Chip select active 50 ns tCSRD Chip select active to Read active 14 ns tRD Read active 36 ns tRDDV Read acti...

Page 1177: ...nt for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice XhiADDR Xlb_mCSn Xlb_sCSn tA2CS Xlb_RS XhiCSn_main XhiCSn_sub tC2CS tA2RS tC2RS Xlb_WEn XhiWEn tWE2WE Xlb_OEn XhiOEn tOE2OE Figure 41 16 LCD Bypass Control signal timing diagram ...

Page 1178: ...ram Table 41 16 LCD Bypass timing Timing VDDINT 1 0V 0 05V TA 40 to 85 C VDDLCD 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Description Min ns Max ns Notes tA2CS Host Address to LCD Chip Select 7 29 tC2CS Host Chip Select to LCD Chip Select 7 29 tA2RS Host Address to LCD Read Select 7 25 tC2RS Host Chip Select to LCD Read Select 7 25 tWE2WE Host Write Enable to LCD Write Enable 7 22 tOE2OE Host Read...

Page 1179: ...cts that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 41 18 Camera Interface VSYNC Timing Figure 41 19 Camera Interface HREF Timing Figure 41 20 Camera Interface Data Timing ...

Page 1180: ...mation herein are subject to change without notice Table 41 17 Camera Controller Module Signal Timing Constants VDDINT 1 0V 0 05V TA 40 to 85 C VDDEXT 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Symbol Min Typ Max Units XciVSYNC input Setup time TssVsync 0 ns XciVSYNC input Hold time ThVsync 2 ns XciHREF input Setup time TssHref 0 ns XciHREF input Hold time ThHref 2 ns XciDATA input Setup time TssDa...

Page 1181: ...e 41 21 High Speed SDMMC Interface Timing Table 41 18 High Speed SDMMC Interface Transmit Receive Timing Constants VDDINT 1 0V 0 05V TA 40 to 85 C VDDMMC 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Symbol Min Typ Max Unit SD Command output Delay time tSDCD 1 0 8 0 ns SD Command input Setup time tSDCS 14 0 1 ns SD Command input Hold time tSDCH 0 1 ns SD Data output Delay time tSDDD 1 0 8 4 ns SD Data...

Page 1182: ...ent for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice SPICLK tSPIMIH tSPIMIS XspiMOSI MO XspiMOSI SI XspiMISO MI tSPIMOD tSPISIS tSPISIH XspiMISO SO tSPISOD XspiCS tSPICSSD tSPICSSS Figure 41 22 SPI Interface Timing CPHA 0 CPOL 0 ...

Page 1183: ...I MOSI Slave Input Hold time tSPISIH 1 1 ns SPI MISO Slave output Delay time tSPISOD 1 12 173 ns SPI MISO Master Input Setup time tSPIMIS 1 1 ns SPI MISO Master Input Hold time tSPIMIH 1 1 ns SPI nSS Master Output Delay time tSPICSSD 19 20 ns Ch 0 SPI nSS Slave Input Setup time tSPICSSS 20 20 ns SPI MOSI Master Output Delay time tSPIMOD 0 8 2 9 ns SPI MOSI Slave Input Setup time tSPISIS 1 1 ns SPI...

Page 1184: ... 23 MIPI HSI Timing Diagram Table 41 19 SPI Interface Transmit Receive Timing Constants VDDINT 1 0V 0 05V TA 40 to 85 C VDDEXT 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Description 1 Mbit s 100 Mbit s 200 Mbit s TNomBit Nominal bit time 1000 ns 10 ns 5 ns TMinEdgeSep Minimum allowed separation of DATA and FLAG signal transitions 500 ns 5 ns 2 5 ns TMaxSkew Maximum allowed time for combined skew an...

Page 1185: ...nd information herein are subject to change without notice I2SLRCLK Output I2SSCLK Output I2SSDO Output TLRId TDS TDH Figure 41 24 IIS Interface Timing Master TX Table 41 15 IIS Controller Module Signal Timing Constants I2S Master TX VDDINT 1 0V 0 05V TA 40 to 85 C VDDPCM 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Symbol Min Typ Max Unit LR Clock Input Delay TLRId 5 ns Serial Data Setup Time TDS 10...

Page 1186: ...s and information herein are subject to change without notice I2SLRCLK Input I2SSCLK Input I2SSDI Input TLRId TDS TDH Figure 41 25 IIS Interface Timing Slave RX Table 41 16 IIS Controller Module Signal Timing Constants I2S Slave RX VDDINT 1 0V 0 05V TA 40 to 85 C VDDPCM 3 3V 0 3V 2 5V 0 25V 1 8V 0 15V Parameter Symbol Min Typ Max Unit LR Clock Input Delay TLRId 0 ns Serial Data Setup Time TDS 10 n...

Page 1187: ...ics Driver FS Parameter Symbol Conditions Min Typ Max Unit Rise Time Tr CL 50 pF 4 20 ns Fall Time Tf CL 50 pF 4 20 ns Differential Rise and Fall Timing Matching TRFM 90 111 11 Output Signal Crossover Voltage VCRS 1 3 2 0 V Driver Output Resistance ZDRV Steady State Drive External Resistance 39Ω 39 44 Ω 2 AC Electrical Characteristics Driver LS Parameter Symbol Conditions Min Typ Max Unit Rise Tim...

Page 1188: ...TA 42 1 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 42 MECHANICAL DATA ...

Page 1189: ...A 1 1 SK 06206 O ADSXXXXX ELECTRONICS 13 00 13 00 A B 0 10 C 2X 0 10 C 2X A1 Indicator 0 24 0 05 MAX 1 20 C 0 08 M C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 0 50 6 00 25 1 X 0 50 12 00 0 50 6 00 25 1 X 0 50 12 00 424 F 0 30 0 05 F 0 15 M C A B F 0 05 M C Datum A Datum B A1 INDEX MARK TOP VIEW SIDE VIEW BOTTOM VIEW NOT...

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