Samsung S3C6400X, User Manual, Page: 38 / 1189

PRELIMINARY
S3C6400
RISC MICROPROCESSOR PRODUCT OVERVIEW
1-35
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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MISC
Signal I/O Description
XOM[4:0] I Operation mode selection. Refer System controller
XPWRRGTON O Power Regulator enable
XSELNAND I Select Flash Memory. 0 : OneNAND, 1 : NAND.
XnBATF I Battery fault indication
1.3.1.9 Power -supply Groups
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VDD
Signal I/O Description Voltage
VDDALIVE P Internal power for alive block 1.0
VDDARM P Internal power for ARM1176 core and cache @ 533Mhz* 1.1
VDDINT P Internal power for logic 1.0
VDDMPLL P Power for MPLL core 1.0
VDDAPLL P Power for APLL core 1.0
VDDEPLL P Power for EPLL core 1.0
VDDOTG P Power for USB OTG PHY 3.3
VDDOTGI P Internal power for USB OTG PHY 1.0
VDDMMC P IO power for SDMMC 1.8~3.3
VDDHI P IO power for Host I/F 1.8~3.3
VDDLCD P IO power for LCD 1.8~3.3
VDDPCM P IO power for PCM ( Audio I/F – I2S, AC97) 1.8~3.3
VDDEXT P IO power for external I/F ( UART, I2C, Camera I/F, USB Host, etc.) 1.8~3.3
VDDSYS P IO power for system control. ( Clock, reset, operation mode, JTAG, etc) 1.8~3.3
VDDUH P Power for USB Host 3.3
VDDADC P Power for ADC core and IO 3.3
VDDDAC P Power for DAC core and IO 3.3
VDDRTC P Power for RTC logic and IO 2.5
VDDM0 P IO power for Memory Port 0 1.8~2.85
VDDM1 P IO power for Memory Port 1 1.8~2,5
*Internal power for Core and cache @ 400Mhz is 1.0V
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VSS
Signal I/O Description
VSSIP G Internal Ground for Logic& ARM1176 core and cache
VSSMEM G IO ground for memory port 0 and 1
VSSOTG G Ground for USB OTG PHY.