PRELIMINARY
S3C6400X RISC MICROPROCESSOR
IRDA
38
-13
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IRDA MODE DEFINITION REGISTER(IRDA_MDR)
Register
Address
R/W
Description
Reset Value
IrDA_MDR 0x7F00_7004 R/W
IrDA Mode Definition Register
0x00
IrDA _MDR
Bit
Description
Initial State
Reserved [7:5]
Reserved
0
SIP Select
[4]
SIP select method. If this bit is set to ‘1’ and the
IrDA_CNT[3] is set to ‘1’, the SIP pulse is appended at the
end of FIR/MIR TX frame. Likewise, when this bit is set to
a ‘0’, SIP is generated at the end of the every FIR/MIR
frames. If IrDA_CNT[3] is set to ‘0’, setting this bit to ‘1’
doesn’t help to generate SIP. Along with IrDA_CNT[3] bit,
the way of SIP generation can be controlled.
0
Temic select
[3]
Bit 3 is Temic transceiver select bit. When bit 3 is clear to
“0”, core automatically selects in Temic transceiver mode.
0
Reserved [2:1]
Reserved
00
Mode select
[0]
select the mode of operation as
0 : FIR Mode
1 : MIR Mode
0
IRDA INTERRUPT / DMA CONFIGURATION REGISTER (IRDA_CNF)
Register
Address
R/W
Description
Reset Value
IrDA_CNF 0x7F00_7008 R/W
IrDA Interrupt / DMA Configuration Register
0x00
IrDA _CNF
Bit
Description
Initial State
Reserved [7:4]
Reserved
0
DMA Enable
[3]
1 : DMA Enable
0
DMA Mode
[2]
0 : Tx DMA
1 : Rx DMA
0
Reserved [1]
Reserved
0
Interrupt Enable
[0]
The bit 0 enables Interrupt output signal.
0