Samsung S3C6400X, User Manual, Page: 213 / 1189

PRELIMINARY
CF CONTROLLER S3C6400X RISC MICROPROCESSOR
9-26
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ATA_CFG Bits Description R/W Reset
Value
BYTE_SWAP [6] Determines whether data endian is little or big in 16bit data.
0 : little endian ( data[15:8], data[7:0] )
1 : big endian ( data[7:0], data[15:8] )
R/W 0x0
ATADEV_IRQ_AL [5] Device interrupt signal level
0: active high 1: active low
R/W 0x0
DMA_DIR [4] DMA transfer direction
0 : Host read data from device
1 : Host write data to device
R/W 0x0
ATA_CLASS [3:2] ATA transfer class select
2’b00 : transfer class is PIO
2’b01 : transfer class is PIO DMA
2’b1x : transfer class is UDMA
R/W 0x0
ATA_IORDY_EN [1] Determines whether IORDY input can extend data transfer.
0 : IORDY disable( ignored )
1 : IORDY enable ( can extend )
R/W 0x0
ATA_RST [0] ATAPI device reset by this host.
0 : no reset 1 : reset
R/W 0x0
ATA_PIO_TIME
Register Address Description Reset Value
ATA_PIO_TIME 0x7030192C ATA PIO timing
0x0001_C238
ATA_PIO_TIME Bits Description R/W Reset
Value
Reserved [31:20] Reserved bits R 0x0
PIO_TEOC [19:12] PIO timing parameter, teoc, end of cycle time
It cannot have zero value.
teoc = HCLK time * (pi 1)
R/W 0x1C
PIO_T2 [11:4] PIO timing parameter, t2, DIOR/Wn pulse width
It cannot have zero value.
t2 = HCLK time * ( 1)
R/W 0x23
PIO_T1 [3:0] PIO timing parameter, t1, address valid to DIOR/Wn
t1 = HCLK time * ( 1)
R/W 0x8