Samsung S3C6400X, User Manual, Page: 875 / 1189

PRELIMINARY
USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR
26-68
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DIEPDMAn/
DOEPDMAn
Bit R/W Description Initial State
DMAAddr [31:0] R_W DMA Address
Holds the start address of the external memory for
storing or fetching endpoint data. This register is
incremented on every AHB transaction.
Note:
For control endpoints, this address stores
control OUT data packets as well as SETUP
transaction data packets. If multiple SETUP packets
are received back-to-back, the SETUP data packet
in the memory is overwritten.
32’h0
POWER AND CLOCK GATING CONTROL REGISTER (PCGCCTL)
The application can use this register to control OTG’s clock gating.
Register Address R/W Description Reset Value
PCGCCTL 0x7C00_0E00 R/W Power and Clock Gating Control Register 32 bits
DIEPTSIZ0 Bit R/W Description Initial State
[31:1] Reserved 31’h0
StopPclk [0] R_W STOP Pclk
The application sets this bit to stop the PHY clock
when the USB is suspended, the session is not valid,
or the device is disconnected. The application clears
this bit when the USB is resumed or a new session
starts.
1’b0