PRELIMINARY
SECURITY SUB-SYSTEM
S3C6400X RISC MICROPROCESSOR
13-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SECURITY SUB-SYSTEM TX FIFO MODULE
FIFO-TX CONTROL REGISTER
Register
Address
R/W
Description
Reset Value
FTx_Ctrl
0x7D80_0000 R/W FIFO-Tx
Control/Status
Reg. (Only MSB 16-bit readable)
0x0400_2000
FTx_Ctrl
Bit
Description
Initial State
WrPrivError [31]
Sets to 1 if write access to FIFO-Tx has resulted in a privilege
error (e.g. Host or the command are not allowed to access
FIFO-Tx).
0b
RdPrivError [30]
Sets to 1 if read access to FIFO-Tx has resulted in a privilege
error (e.g. Host or the command are not allowed to access
FIFO-Tx).
0b
Reserved [29:28]
Reserved
00b
Full
[27]
Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is full.
0b
Empty
[26]
Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is empty.
1b
Done [25]
Sets to 1 if FIFO-Tx has finished transferring FTx_MLen
words of data from the source.
0b
Running [24]
Sets to 1 if FIFO-Tx is transferring data from the source or
waiting for source output buffer is ready. Sets to 1 when
FTx_Start bit resets to 0.
0b
Wd2Read [23:16]
Number of words that can be read from FIFO memory
(FTx_RdBuf)
0x00
Wd2Write [15:8]
Number of words that can be written to FIFO memory
(FTx_RdBuf)
0x20
Src_Module [7:6]
Source module selection.
00 : AES
01:DES/3DES
10: SHA-1/PRNG
11: reserved
0b
Host_Rd_En
[5]
Enables Host read from FTx_Ctrl[31:16] and FTx_MLenCnt.
0b
Host_Wr_En
[4]
Enables Host read from FTx_RdBuf
0b
Reset [2]
Stops current FIFO-Tx transfer and resets FSM and all the
register.
0b
ERROR_En [1]
Enables ERROR response via HRESP port when host tries to
access FIFO-Tx and access is not enabled by FTx_Ctrl[4] or
[5].
0b
Start [0]
FIFO-Tx transfer start bit. Resets to 0 when internal FSM
starts transferring data to destination.
0b