PRELIMINARY
S3C6400X RISC MICROPROCESSOR
CAMERA INTERFACE
20-19
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
GLOBAL CONTROL REGISTER
Register
Address
R/W
Description
Reset Value
CIGCTRL
0x78000008
RW
Global control register
2000_0000
CIGCTRL
Bit
Description
Initial
State
M L
SwRst [31]
Camera interface software reset. Before setting this bit, you must
set the ITU601_656n bit of CISRCFMT as “1” temporarily at first
SFR setting. Next sequence is recommended.
(ITU601 case : ITU601_656n “1”
→
SwRst “1”
→
SwRst “0” for
first SFR setting ,
ITU656 case : ITU601_656n “1”
→
SwRst “1”
→
SwRst “0”
→
ITU601_656n “0” for first SFR setting)
0
X X
CamRst
[30]
External camera processor Reset or Power Down control
0
X X
reserved [29]
1
X X
TestPattern [28:27]
This register must be set at only ITU-T 601 8-bit mode. Not
allowed with input 16-bit mode or ITU-T 656 mode. (max. 1280 X
1024)
00 : external camera processor input (normal)
01 : color bar test pattern
10 : horizontal increment test pattern
11 . vertical increment test pattern
0
X X
InvPolPCLK
[26]
1 : inverse the polarity of PCLK 0 : normal
0
X X
InvPolVSYNC
[25]
1 : inverse the polarity of VSYNC 0 : normal
0
X X
InvPolHREF
[24]
1 : inverse the polarity of HREF 0 : normal
0
X X
reserved [23]
0
X X
IRQ_Ovfen [22]
1 : Overflow interrupt enable (Interrupt is generated during
overflow occurrence)
0 : Overflow interrupt disable (normal)
0
X X
Href_mask [21]
1 : mask out Href during Vsync high
0 : no mask
0
X X
IRQ_LEVEL [20]
1 : Level interrupt
0 : Edge trigger interrupt (default)
* This bit should be set to ‘1’ because of using level interrupt
method in S3C6400x
0
X X
IRQ_CLR_c [19]
This bit is related only to Level interrupt. Codec path interrupt is
cleared when IRQ_CLR_c is written to ‘1’. This bit Auto-clear.
0
X X
IRQ_CLR_p [18]
This bit is related only to Level interrupt. Preview path interrupt is
cleared when IRQ_CLR_p is written to ‘1’. This bit Auto-clear.
0
X X
Reserved [17:0]