PRELIMINARY
TV ENCODER
S3C6400X RISC MICROPROCESSOR
17-18
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
TVENCREG2
Register Address
R/W
Description
Reset
Value
VBPORCH
0x76200004
R/W
Vertical back porch end point
0x011C0015
VBPORCH Bit
Description
Reset
Value
[31:25]
Reserved
0
VEFBPD [24:16]
Vertical even field back porch end point
NTSC : 0x11C(284) , PAL : 0x14F(335)
0x11C
[15:8]
Reserved
0
VOFBPD [7:0]
Vertical odd field back porch end point
NTSC : 0x15(21), PAL : 0x16(22)
0x15
TVENCREG3
Register Address
R/W
Description
Reset
Value
HBPORCH 0x76200008
R/W
Horizontal
back porch end point
0x008000F4
HBPORCH Bit
Description
Reset
Value
[31:24]
Reserved
0
HSPW [23:16]
Horizontal sync pulse width
Default : 0x80(128) (NTSC, PAL)
0x80
[15:11]
Reserved
0
HBPD [10:0]
Horizontal back porch end point
NTSC : 0xF4(244), PAL : 0x108(264)
0xF4
TVENCREG4
Register Address
R/W
Description
Reset
Value
HEnhOffset 0x7620000C
R/W
Horizontal enhancer offset
0x0000041A
HEnhOffset Bit
Description
Reset
Value
[31:30]
Reserved
0
VACTWinCenCTRL [29:24]
Vertical
active window center control
0
HACTWinCenCTRL [23:16]
Horizontal
active window center contrl
0
[15:11]
Reserved
0
DTOffset [10:8]
Data input timing offset value
NTSC, PAL : 0x4(4)
0x4
[7:5]
Reserved
0
HEOV [4:0]
Horizontal enhancer offset value. The enhancer
needs 26-cycles before TV encoder starts( 0 ~ 31)
Default : 0x1A(26) (NTSC, PAL)
0x1A