PRELIMINARY
S3C6400 RISC MICROPROCESSOR
UART
31-17
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART FIFO CONTROL REGISTER
There are three UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART
block.
Note:
When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in
DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the you must check the
FIFO status and read out the rest.
Register
Address
R/W
Description
Reset Value
UFCON0 0x7F005008
R/W
UART
channel 0 FIFO control register
0x0
UFCON1 0x7F005408
R/W
UART
channel 1 FIFO control register
0x0
UFCON2 0x7F005808
R/W
UART
channel 2 FIFO control register
0x0
UFCON3 0x7F005C08
R/W
UART
channel 3 FIFO control register
0x0
UFCONn
Bit
Description
Initial State
Tx FIFO Trigger Level
[7:6] Determine the trigger level of transmit FIFO.
00 = Empty 01 = 16-byte
10 = 32-byte 11 = 48-byte
00
Rx FIFO Trigger Level
[5:4] Determine the trigger level of receive FIFO.
00 = 1-byte 01 = 8-byte
10 = 16-byte 11 = 32-byte
00
Reserved [3]
0
Tx FIFO Reset
[2]
Auto-cleared after resetting FIFO
0 = Normal 1= Tx FIFO reset
0
Rx FIFO Reset
[1]
Auto-cleared after resetting FIFO
0 = Normal 1= Rx FIFO reset
0
FIFO Enable
[0]
0 = Disable 1 = Enable
0