PRELIMINARY
S3C6400X RISC MICROPROCESSOR
IIS-BUS INTERFACE
36-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FTXEMPT
[10]
R
Tx FIFO empty status indication.
0: FIFO is not empty (ready for transmit data to channel)
1: FIFO is empty (not ready for transmit data to channel)
FRXEMPT
[9]
R
Rx FIFO empty status indication.
0: FIFO is not empty
1: FIFO is empty
FTXFULL
[8]
R
Tx FIFO full status indication.
0: FIFO is not full
1: FIFO is full
FRXFULL
[7]
R
Rx FIFO full status indication.
0: FIFO is not full (ready for receive data from channel)
1: FIFO is full (not ready for receive data from channel)
TXDMAPAUSE
[6]
R/W
Tx DMA operation pause command. Note that when this bit is
activated at any time, the DMA request will be halted after current
on-going DMA transfer is completed.
0: No pause DMA operation
1: Pause DMA operation
RXDMAPAUSE
[5]
R/W
Rx DMA operation pause command. Note that when this bit is
activated at any time, the DMA request will be halted after current
on-going DMA transfer is completed.
0: No pause DMA operation
1: Pause DMA operation
TXCHPAUSE
[4]
R/W
Tx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-
right channel data transfer is completed.
0: No pause operation
1: Pause operation
RXCHPAUSE
[3]
R/W
Rx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-
right channel data transfer is completed.
0: No pause operation
1: Pause operation